2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * written by Carsten Langgaard, carstenl@mips.com
14 #define USE_ALTERNATE_RESUME_IMPL 1
17 #include "r4k_switch.S"
20 * task_struct *resume(task_struct *prev, task_struct *next,
21 * struct thread_info *next_ti, int usedfpu)
27 LONG_S t1, THREAD_STATUS(a0)
28 cpu_save_nonscratch a0
29 LONG_S ra, THREAD_REG31(a0)
32 * check if we need to save FPU registers
37 PTR_L t3, TASK_THREAD_INFO(a0)
41 * clear saved user stack CU1 bit
50 fpu_save_double a0 t0 t1 # c0_status passed in t0
55 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
56 /* Check if we need to store CVMSEG state */
57 dmfc0 t0, $11,7 /* CvmMemCtl */
58 bbit0 t0, 6, 3f /* Is user access enabled? */
60 /* Store the CVMSEG state */
61 /* Extract the size of CVMSEG */
63 /* Multiply * (cache line size/sizeof(long)/2) */
65 li t1, -32768 /* Base address of CVMSEG */
66 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
70 LONG_L t8, 0(t1) /* Load from CVMSEG */
71 subu t0, 1 /* Decrement loop var */
72 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
73 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
74 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
75 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
76 bnez t0, 2b /* Loop until we've copied it all */
77 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
80 /* Disable access to CVMSEG */
81 dmfc0 t0, $11,7 /* CvmMemCtl */
82 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
83 dmtc0 t0, $11,7 /* CvmMemCtl */
87 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
88 PTR_LA t8, __stack_chk_guard
89 LONG_L t9, TASK_STACK_CANARY(a1)
94 * The order of restoring the registers takes care of the race
95 * updating $28, $29 and kernelsp without disabling ints.
98 cpu_restore_nonscratch a1
100 PTR_ADDU t0, $28, _THREAD_SIZE - 32
101 set_saved_sp t0, t1, t2
103 mfc0 t1, CP0_STATUS /* Do we really need this? */
106 LONG_L a2, THREAD_STATUS(a1)
116 * void octeon_cop2_save(struct octeon_cop2_state *a0)
121 LEAF(octeon_cop2_save)
123 dmfc0 t9, $9,7 /* CvmCtl register. */
125 /* Save the COP2 CRC state */
129 sd t0, OCTEON_CP2_CRC_IV(a0)
130 sd t1, OCTEON_CP2_CRC_LENGTH(a0)
131 /* Skip next instructions if CvmCtl[NODFA_CP2] set */
133 sd t2, OCTEON_CP2_CRC_POLY(a0)
135 /* Save the LLM state */
138 sd t0, OCTEON_CP2_LLM_DAT(a0)
140 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
141 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
143 /* Save the COP2 crypto state */
144 /* this part is mostly common to both pass 1 and later revisions */
149 sd t0, OCTEON_CP2_3DES_IV(a0)
151 sd t1, OCTEON_CP2_3DES_KEY(a0)
152 dmfc2 t1, 0x0111 /* only necessary for pass 1 */
153 sd t2, OCTEON_CP2_3DES_KEY+8(a0)
155 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
157 sd t0, OCTEON_CP2_3DES_RESULT(a0)
159 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
161 sd t2, OCTEON_CP2_AES_IV(a0)
163 sd t3, OCTEON_CP2_AES_IV+8(a0)
165 sd t0, OCTEON_CP2_AES_KEY(a0)
167 sd t1, OCTEON_CP2_AES_KEY+8(a0)
169 sd t2, OCTEON_CP2_AES_KEY+16(a0)
171 sd t3, OCTEON_CP2_AES_KEY+24(a0)
172 mfc0 v0, $15,0 /* Get the processor ID register */
173 sd t0, OCTEON_CP2_AES_KEYLEN(a0)
174 li v1, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
175 sd t1, OCTEON_CP2_AES_RESULT(a0)
176 /* Skip to the Pass1 version of the remainder of the COP2 state */
178 sd t2, OCTEON_CP2_AES_RESULT+8(a0)
180 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
183 ori v1, v1, 0x9500 /* lowest OCTEON III PrId*/
185 subu v1, v0, v1 /* prid - lowest OCTEON III PrId */
187 sd t1, OCTEON_CP2_HSH_DATW(a0)
189 sd t2, OCTEON_CP2_HSH_DATW+8(a0)
191 sd t3, OCTEON_CP2_HSH_DATW+16(a0)
193 sd t0, OCTEON_CP2_HSH_DATW+24(a0)
195 sd t1, OCTEON_CP2_HSH_DATW+32(a0)
197 sd t2, OCTEON_CP2_HSH_DATW+40(a0)
199 sd t3, OCTEON_CP2_HSH_DATW+48(a0)
201 sd t0, OCTEON_CP2_HSH_DATW+56(a0)
203 sd t1, OCTEON_CP2_HSH_DATW+64(a0)
205 sd t2, OCTEON_CP2_HSH_DATW+72(a0)
207 sd t3, OCTEON_CP2_HSH_DATW+80(a0)
209 sd t0, OCTEON_CP2_HSH_DATW+88(a0)
211 sd t1, OCTEON_CP2_HSH_DATW+96(a0)
213 sd t2, OCTEON_CP2_HSH_DATW+104(a0)
215 sd t3, OCTEON_CP2_HSH_DATW+112(a0)
217 sd t0, OCTEON_CP2_HSH_IVW(a0)
219 sd t1, OCTEON_CP2_HSH_IVW+8(a0)
221 sd t2, OCTEON_CP2_HSH_IVW+16(a0)
223 sd t3, OCTEON_CP2_HSH_IVW+24(a0)
225 sd t0, OCTEON_CP2_HSH_IVW+32(a0)
227 sd t1, OCTEON_CP2_HSH_IVW+40(a0)
229 sd t2, OCTEON_CP2_HSH_IVW+48(a0)
231 sd t3, OCTEON_CP2_HSH_IVW+56(a0)
233 sd t0, OCTEON_CP2_GFM_MULT(a0)
235 sd t1, OCTEON_CP2_GFM_MULT+8(a0)
236 sd t2, OCTEON_CP2_GFM_POLY(a0)
237 sd t3, OCTEON_CP2_GFM_RESULT(a0)
239 sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
240 /* OCTEON III things*/
243 sd t0, OCTEON_CP2_SHA3(a0)
244 sd t1, OCTEON_CP2_SHA3+8(a0)
249 2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
254 sd t3, OCTEON_CP2_HSH_DATW(a0)
256 sd t0, OCTEON_CP2_HSH_DATW+8(a0)
258 sd t1, OCTEON_CP2_HSH_DATW+16(a0)
260 sd t2, OCTEON_CP2_HSH_DATW+24(a0)
262 sd t3, OCTEON_CP2_HSH_DATW+32(a0)
264 sd t0, OCTEON_CP2_HSH_DATW+40(a0)
266 sd t1, OCTEON_CP2_HSH_DATW+48(a0)
267 sd t2, OCTEON_CP2_HSH_IVW(a0)
268 sd t3, OCTEON_CP2_HSH_IVW+8(a0)
269 sd t0, OCTEON_CP2_HSH_IVW+16(a0)
271 3: /* pass 1 or CvmCtl[NOCRYPTO] set */
274 END(octeon_cop2_save)
278 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
283 LEAF(octeon_cop2_restore)
284 /* First cache line was prefetched before the call */
286 dmfc0 t9, $9,7 /* CvmCtl register. */
289 ld t0, OCTEON_CP2_CRC_IV(a0)
291 ld t1, OCTEON_CP2_CRC_LENGTH(a0)
292 ld t2, OCTEON_CP2_CRC_POLY(a0)
294 /* Restore the COP2 CRC state */
297 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
300 /* Restore the LLM state */
301 ld t0, OCTEON_CP2_LLM_DAT(a0)
302 ld t1, OCTEON_CP2_LLM_DAT+8(a0)
307 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
310 /* Restore the COP2 crypto state common to pass 1 and pass 2 */
311 ld t0, OCTEON_CP2_3DES_IV(a0)
312 ld t1, OCTEON_CP2_3DES_KEY(a0)
313 ld t2, OCTEON_CP2_3DES_KEY+8(a0)
315 ld t0, OCTEON_CP2_3DES_KEY+16(a0)
317 ld t1, OCTEON_CP2_3DES_RESULT(a0)
319 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
321 ld t0, OCTEON_CP2_AES_IV(a0)
323 ld t1, OCTEON_CP2_AES_IV+8(a0)
324 dmtc2 t2, 0x010A /* only really needed for pass 1 */
325 ld t2, OCTEON_CP2_AES_KEY(a0)
327 ld t0, OCTEON_CP2_AES_KEY+8(a0)
329 ld t1, OCTEON_CP2_AES_KEY+16(a0)
331 ld t2, OCTEON_CP2_AES_KEY+24(a0)
333 ld t0, OCTEON_CP2_AES_KEYLEN(a0)
335 ld t1, OCTEON_CP2_AES_RESULT(a0)
337 ld t2, OCTEON_CP2_AES_RESULT+8(a0)
338 mfc0 t3, $15,0 /* Get the processor ID register */
340 li v0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
342 bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
345 /* this code is specific for pass 1 */
346 ld t0, OCTEON_CP2_HSH_DATW(a0)
347 ld t1, OCTEON_CP2_HSH_DATW+8(a0)
348 ld t2, OCTEON_CP2_HSH_DATW+16(a0)
350 ld t0, OCTEON_CP2_HSH_DATW+24(a0)
352 ld t1, OCTEON_CP2_HSH_DATW+32(a0)
354 ld t2, OCTEON_CP2_HSH_DATW+40(a0)
356 ld t0, OCTEON_CP2_HSH_DATW+48(a0)
358 ld t1, OCTEON_CP2_HSH_IVW(a0)
360 ld t2, OCTEON_CP2_HSH_IVW+8(a0)
362 ld t0, OCTEON_CP2_HSH_IVW+16(a0)
365 b done_restore /* unconditional branch */
368 3: /* this is post-pass1 code */
369 ld t2, OCTEON_CP2_HSH_DATW(a0)
370 ori v0, v0, 0x9500 /* lowest OCTEON III PrId*/
371 ld t0, OCTEON_CP2_HSH_DATW+8(a0)
372 ld t1, OCTEON_CP2_HSH_DATW+16(a0)
374 ld t2, OCTEON_CP2_HSH_DATW+24(a0)
376 ld t0, OCTEON_CP2_HSH_DATW+32(a0)
378 ld t1, OCTEON_CP2_HSH_DATW+40(a0)
380 ld t2, OCTEON_CP2_HSH_DATW+48(a0)
382 ld t0, OCTEON_CP2_HSH_DATW+56(a0)
384 ld t1, OCTEON_CP2_HSH_DATW+64(a0)
386 ld t2, OCTEON_CP2_HSH_DATW+72(a0)
388 ld t0, OCTEON_CP2_HSH_DATW+80(a0)
390 ld t1, OCTEON_CP2_HSH_DATW+88(a0)
392 ld t2, OCTEON_CP2_HSH_DATW+96(a0)
394 ld t0, OCTEON_CP2_HSH_DATW+104(a0)
396 ld t1, OCTEON_CP2_HSH_DATW+112(a0)
398 ld t2, OCTEON_CP2_HSH_IVW(a0)
400 ld t0, OCTEON_CP2_HSH_IVW+8(a0)
402 ld t1, OCTEON_CP2_HSH_IVW+16(a0)
404 ld t2, OCTEON_CP2_HSH_IVW+24(a0)
406 ld t0, OCTEON_CP2_HSH_IVW+32(a0)
408 ld t1, OCTEON_CP2_HSH_IVW+40(a0)
410 ld t2, OCTEON_CP2_HSH_IVW+48(a0)
412 ld t0, OCTEON_CP2_HSH_IVW+56(a0)
414 ld t1, OCTEON_CP2_GFM_MULT(a0)
416 ld t2, OCTEON_CP2_GFM_MULT+8(a0)
418 ld t0, OCTEON_CP2_GFM_POLY(a0)
420 ld t1, OCTEON_CP2_GFM_RESULT(a0)
422 ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
424 subu v0, t3, v0 /* prid - lowest OCTEON III PrId */
426 bltz v0, done_restore
428 /* OCTEON III things*/
429 ld t0, OCTEON_CP2_SHA3(a0)
430 ld t1, OCTEON_CP2_SHA3+8(a0)
436 END(octeon_cop2_restore)
440 * void octeon_mult_save()
441 * sp is assumed to point to a struct pt_regs
443 * NOTE: This is called in SAVE_TEMP in stackframe.h. It can
444 * safely modify v1,k0, k1,$10-$15, and $24. It will
445 * be overwritten with a processor specific version of the code.
450 LEAF(octeon_mult_save)
454 octeon_mult_save_end:
455 EXPORT(octeon_mult_save_end)
456 END(octeon_mult_save)
458 LEAF(octeon_mult_save2)
459 /* Save the multiplier state OCTEON II and earlier*/
462 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
464 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
467 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
469 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
471 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
473 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
474 octeon_mult_save2_end:
475 EXPORT(octeon_mult_save2_end)
476 END(octeon_mult_save2)
478 LEAF(octeon_mult_save3)
479 /* Save the multiplier state OCTEON III */
480 v3mulu $10, $0, $0 /* read P0 */
481 v3mulu $11, $0, $0 /* read P1 */
482 v3mulu $12, $0, $0 /* read P2 */
483 sd $10, PT_MTP+(0*8)(sp) /* store P0 */
484 v3mulu $10, $0, $0 /* read P3 */
485 sd $11, PT_MTP+(1*8)(sp) /* store P1 */
486 v3mulu $11, $0, $0 /* read P4 */
487 sd $12, PT_MTP+(2*8)(sp) /* store P2 */
489 v3mulu $12, $0, $0 /* read P5 */
490 sd $10, PT_MTP+(3*8)(sp) /* store P3 */
491 v3mulu $13, $13, $0 /* P4-P0 = MPL5-MPL1, $13 = MPL0 */
492 sd $11, PT_MTP+(4*8)(sp) /* store P4 */
493 v3mulu $10, $0, $0 /* read MPL1 */
494 sd $12, PT_MTP+(5*8)(sp) /* store P5 */
495 v3mulu $11, $0, $0 /* read MPL2 */
496 sd $13, PT_MPL+(0*8)(sp) /* store MPL0 */
497 v3mulu $12, $0, $0 /* read MPL3 */
498 sd $10, PT_MPL+(1*8)(sp) /* store MPL1 */
499 v3mulu $10, $0, $0 /* read MPL4 */
500 sd $11, PT_MPL+(2*8)(sp) /* store MPL2 */
501 v3mulu $11, $0, $0 /* read MPL5 */
502 sd $12, PT_MPL+(3*8)(sp) /* store MPL3 */
503 sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */
505 sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */
506 octeon_mult_save3_end:
507 EXPORT(octeon_mult_save3_end)
508 END(octeon_mult_save3)
512 * void octeon_mult_restore()
513 * sp is assumed to point to a struct pt_regs
515 * NOTE: This is called in RESTORE_TEMP in stackframe.h.
520 LEAF(octeon_mult_restore)
524 octeon_mult_restore_end:
525 EXPORT(octeon_mult_restore_end)
526 END(octeon_mult_restore)
528 LEAF(octeon_mult_restore2)
529 ld v0, PT_MPL(sp) /* MPL0 */
530 ld v1, PT_MPL+8(sp) /* MPL1 */
531 ld k0, PT_MPL+16(sp) /* MPL2 */
532 /* Restore the multiplier state */
533 ld k1, PT_MTP+16(sp) /* P2 */
535 ld v0, PT_MTP+8(sp) /* P1 */
537 ld v1, PT_MTP(sp) /* P0 */
543 octeon_mult_restore2_end:
544 EXPORT(octeon_mult_restore2_end)
545 END(octeon_mult_restore2)
547 LEAF(octeon_mult_restore3)
548 ld $12, PT_MPL+(0*8)(sp) /* read MPL0 */
549 ld $13, PT_MPL+(3*8)(sp) /* read MPL3 */
550 ld $10, PT_MPL+(1*8)(sp) /* read MPL1 */
551 ld $11, PT_MPL+(4*8)(sp) /* read MPL4 */
553 /* mtm0 $12, $13 restore MPL0 and MPL3 */
554 ld $12, PT_MPL+(2*8)(sp) /* read MPL2 */
556 /* mtm1 $10, $11 restore MPL1 and MPL4 */
557 ld $13, PT_MPL+(5*8)(sp) /* read MPL5 */
558 ld $10, PT_MTP+(0*8)(sp) /* read P0 */
559 ld $11, PT_MTP+(3*8)(sp) /* read P3 */
561 /* mtm2 $12, $13 restore MPL2 and MPL5 */
562 ld $12, PT_MTP+(1*8)(sp) /* read P1 */
564 /* mtp0 $10, $11 restore P0 and P3 */
565 ld $13, PT_MTP+(4*8)(sp) /* read P4 */
566 ld $10, PT_MTP+(2*8)(sp) /* read P2 */
567 ld $11, PT_MTP+(5*8)(sp) /* read P5 */
569 /* mtp1 $12, $13 restore P1 and P4 */
572 /* mtp2 $10, $11 restore P2 and P5 */
574 octeon_mult_restore3_end:
575 EXPORT(octeon_mult_restore3_end)
576 END(octeon_mult_restore3)