arch/mips/kernel/ptrace.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 Ross Biro
   7  * Copyright (C) Linus Torvalds
   8  * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
   9  * Copyright (C) 1996 David S. Miller
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 1999 MIPS Technologies, Inc.
  12  * Copyright (C) 2000 Ulf Carlsson
  13  *
  14  * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
  15  * binaries.
  16  */
  17 #include <linux/compiler.h>
  18 #include <linux/context_tracking.h>
  19 #include <linux/elf.h>
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/mm.h>
  23 #include <linux/errno.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/regset.h>
  26 #include <linux/smp.h>
  27 #include <linux/user.h>
  28 #include <linux/security.h>
  29 #include <linux/tracehook.h>
  30 #include <linux/audit.h>
  31 #include <linux/seccomp.h>
  32
  33 #include <asm/byteorder.h>
  34 #include <asm/cpu.h>
  35 #include <asm/dsp.h>
  36 #include <asm/fpu.h>
  37 #include <asm/mipsregs.h>
  38 #include <asm/mipsmtregs.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/page.h>
  41 #include <asm/syscall.h>
  42 #include <asm/uaccess.h>
  43 #include <asm/bootinfo.h>
  44 #include <asm/reg.h>
  45
  46 /*
  47  * Called by kernel/ptrace.c when detaching..
  48  *
  49  * Make sure single step bits etc are not set.
  50  */
  51 void ptrace_disable(struct task_struct *child)
  52 {
  53         /* Don't load the watchpoint registers for the ex-child. */
  54         clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
  55 }
  56
  57 /*
  58  * Read a general register set.  We always use the 64-bit format, even
  59  * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
  60  * Registers are sign extended to fill the available space.
  61  */
  62 int ptrace_getregs(struct task_struct *child, __s64 __user *data)
  63 {
  64         struct pt_regs *regs;
  65         int i;
  66
  67         if (!access_ok(VERIFY_WRITE, data, 38 * 8))
  68                 return -EIO;
  69
  70         regs = task_pt_regs(child);
  71
  72         for (i = 0; i < 32; i++)
  73                 __put_user((long)regs->regs[i], data + i);
  74         __put_user((long)regs->lo, data + EF_LO - EF_R0);
  75         __put_user((long)regs->hi, data + EF_HI - EF_R0);
  76         __put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
  77         __put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
  78         __put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
  79         __put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
  80
  81         return 0;
  82 }
  83
  84 /*
  85  * Write a general register set.  As for PTRACE_GETREGS, we always use
  86  * the 64-bit format.  On a 32-bit kernel only the lower order half
  87  * (according to endianness) will be used.
  88  */
  89 int ptrace_setregs(struct task_struct *child, __s64 __user *data)
  90 {
  91         struct pt_regs *regs;
  92         int i;
  93
  94         if (!access_ok(VERIFY_READ, data, 38 * 8))
  95                 return -EIO;
  96
  97         regs = task_pt_regs(child);
  98
  99         for (i = 0; i < 32; i++)
 100                 __get_user(regs->regs[i], data + i);
 101         __get_user(regs->lo, data + EF_LO - EF_R0);
 102         __get_user(regs->hi, data + EF_HI - EF_R0);
 103         __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
 104
 105         /* badvaddr, status, and cause may not be written.  */
 106
 107         return 0;
 108 }
 109
 110 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
 111 {
 112         int i;
 113         unsigned int tmp;
 114
 115         if (!access_ok(VERIFY_WRITE, data, 33 * 8))
 116                 return -EIO;
 117
 118         if (tsk_used_math(child)) {
 119                 fpureg_t *fregs = get_fpu_regs(child);
 120                 for (i = 0; i < 32; i++)
 121                         __put_user(fregs[i], i + (__u64 __user *) data);
 122         } else {
 123                 for (i = 0; i < 32; i++)
 124                         __put_user((__u64) -1, i + (__u64 __user *) data);
 125         }
 126
 127         __put_user(child->thread.fpu.fcr31, data + 64);
 128
 129         preempt_disable();
 130         if (cpu_has_fpu) {
 131                 unsigned int flags;
 132
 133                 if (cpu_has_mipsmt) {
 134                         unsigned int vpflags = dvpe();
 135                         flags = read_c0_status();
 136                         __enable_fpu();
 137                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
 138                         write_c0_status(flags);
 139                         evpe(vpflags);
 140                 } else {
 141                         flags = read_c0_status();
 142                         __enable_fpu();
 143                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
 144                         write_c0_status(flags);
 145                 }
 146         } else {
 147                 tmp = 0;
 148         }
 149         preempt_enable();
 150         __put_user(tmp, data + 65);
 151
 152         return 0;
 153 }
 154
 155 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
 156 {
 157         fpureg_t *fregs;
 158         int i;
 159
 160         if (!access_ok(VERIFY_READ, data, 33 * 8))
 161                 return -EIO;
 162
 163         fregs = get_fpu_regs(child);
 164
 165         for (i = 0; i < 32; i++)
 166                 __get_user(fregs[i], i + (__u64 __user *) data);
 167
 168         __get_user(child->thread.fpu.fcr31, data + 64);
 169
 170         /* FIR may not be written.  */
 171
 172         return 0;
 173 }
 174
 175 int ptrace_get_watch_regs(struct task_struct *child,
 176                           struct pt_watch_regs __user *addr)
 177 {
 178         enum pt_watch_style style;
 179         int i;
 180
 181         if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
 182                 return -EIO;
 183         if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
 184                 return -EIO;
 185
 186 #ifdef CONFIG_32BIT
 187         style = pt_watch_style_mips32;
 188 #define WATCH_STYLE mips32
 189 #else
 190         style = pt_watch_style_mips64;
 191 #define WATCH_STYLE mips64
 192 #endif
 193
 194         __put_user(style, &addr->style);
 195         __put_user(current_cpu_data.watch_reg_use_cnt,
 196                    &addr->WATCH_STYLE.num_valid);
 197         for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
 198                 __put_user(child->thread.watch.mips3264.watchlo[i],
 199                            &addr->WATCH_STYLE.watchlo[i]);
 200                 __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
 201                            &addr->WATCH_STYLE.watchhi[i]);
 202                 __put_user(current_cpu_data.watch_reg_masks[i],
 203                            &addr->WATCH_STYLE.watch_masks[i]);
 204         }
 205         for (; i < 8; i++) {
 206                 __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
 207                 __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
 208                 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
 209         }
 210
 211         return 0;
 212 }
 213
 214 int ptrace_set_watch_regs(struct task_struct *child,
 215                           struct pt_watch_regs __user *addr)
 216 {
 217         int i;
 218         int watch_active = 0;
 219         unsigned long lt[NUM_WATCH_REGS];
 220         u16 ht[NUM_WATCH_REGS];
 221
 222         if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
 223                 return -EIO;
 224         if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
 225                 return -EIO;
 226         /* Check the values. */
 227         for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
 228                 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
 229 #ifdef CONFIG_32BIT
 230                 if (lt[i] & __UA_LIMIT)
 231                         return -EINVAL;
 232 #else
 233                 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
 234                         if (lt[i] & 0xffffffff80000000UL)
 235                                 return -EINVAL;
 236                 } else {
 237                         if (lt[i] & __UA_LIMIT)
 238                                 return -EINVAL;
 239                 }
 240 #endif
 241                 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
 242                 if (ht[i] & ~0xff8)
 243                         return -EINVAL;
 244         }
 245         /* Install them. */
 246         for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
 247                 if (lt[i] & 7)
 248                         watch_active = 1;
 249                 child->thread.watch.mips3264.watchlo[i] = lt[i];
 250                 /* Set the G bit. */
 251                 child->thread.watch.mips3264.watchhi[i] = ht[i];
 252         }
 253
 254         if (watch_active)
 255                 set_tsk_thread_flag(child, TIF_LOAD_WATCH);
 256         else
 257                 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
 258
 259         return 0;
 260 }
 261
 262 /* regset get/set implementations */
 263
 264 static int gpr_get(struct task_struct *target,
 265                    const struct user_regset *regset,
 266                    unsigned int pos, unsigned int count,
 267                    void *kbuf, void __user *ubuf)
 268 {
 269         struct pt_regs *regs = task_pt_regs(target);
 270
 271         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 272                                    regs, 0, sizeof(*regs));
 273 }
 274
 275 static int gpr_set(struct task_struct *target,
 276                    const struct user_regset *regset,
 277                    unsigned int pos, unsigned int count,
 278                    const void *kbuf, const void __user *ubuf)
 279 {
 280         struct pt_regs newregs;
 281         int ret;
 282
 283         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 284                                  &newregs,
 285                                  0, sizeof(newregs));
 286         if (ret)
 287                 return ret;
 288
 289         *task_pt_regs(target) = newregs;
 290
 291         return 0;
 292 }
 293
 294 static int fpr_get(struct task_struct *target,
 295                    const struct user_regset *regset,
 296                    unsigned int pos, unsigned int count,
 297                    void *kbuf, void __user *ubuf)
 298 {
 299         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 300                                    &target->thread.fpu,
 301                                    0, sizeof(elf_fpregset_t));
 302         /* XXX fcr31  */
 303 }
 304
 305 static int fpr_set(struct task_struct *target,
 306                    const struct user_regset *regset,
 307                    unsigned int pos, unsigned int count,
 308                    const void *kbuf, const void __user *ubuf)
 309 {
 310         return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 311                                   &target->thread.fpu,
 312                                   0, sizeof(elf_fpregset_t));
 313         /* XXX fcr31  */
 314 }
 315
 316 enum mips_regset {
 317         REGSET_GPR,
 318         REGSET_FPR,
 319 };
 320
 321 static const struct user_regset mips_regsets[] = {
 322         [REGSET_GPR] = {
 323                 .core_note_type = NT_PRSTATUS,
 324                 .n              = ELF_NGREG,
 325                 .size           = sizeof(unsigned int),
 326                 .align          = sizeof(unsigned int),
 327                 .get            = gpr_get,
 328                 .set            = gpr_set,
 329         },
 330         [REGSET_FPR] = {
 331                 .core_note_type = NT_PRFPREG,
 332                 .n              = ELF_NFPREG,
 333                 .size           = sizeof(elf_fpreg_t),
 334                 .align          = sizeof(elf_fpreg_t),
 335                 .get            = fpr_get,
 336                 .set            = fpr_set,
 337         },
 338 };
 339
 340 static const struct user_regset_view user_mips_view = {
 341         .name           = "mips",
 342         .e_machine      = ELF_ARCH,
 343         .ei_osabi       = ELF_OSABI,
 344         .regsets        = mips_regsets,
 345         .n              = ARRAY_SIZE(mips_regsets),
 346 };
 347
 348 static const struct user_regset mips64_regsets[] = {
 349         [REGSET_GPR] = {
 350                 .core_note_type = NT_PRSTATUS,
 351                 .n              = ELF_NGREG,
 352                 .size           = sizeof(unsigned long),
 353                 .align          = sizeof(unsigned long),
 354                 .get            = gpr_get,
 355                 .set            = gpr_set,
 356         },
 357         [REGSET_FPR] = {
 358                 .core_note_type = NT_PRFPREG,
 359                 .n              = ELF_NFPREG,
 360                 .size           = sizeof(elf_fpreg_t),
 361                 .align          = sizeof(elf_fpreg_t),
 362                 .get            = fpr_get,
 363                 .set            = fpr_set,
 364         },
 365 };
 366
 367 static const struct user_regset_view user_mips64_view = {
 368         .name           = "mips",
 369         .e_machine      = ELF_ARCH,
 370         .ei_osabi       = ELF_OSABI,
 371         .regsets        = mips64_regsets,
 372         .n              = ARRAY_SIZE(mips_regsets),
 373 };
 374
 375 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
 376 {
 377 #ifdef CONFIG_32BIT
 378         return &user_mips_view;
 379 #endif
 380
 381 #ifdef CONFIG_MIPS32_O32
 382                 if (test_thread_flag(TIF_32BIT_REGS))
 383                         return &user_mips_view;
 384 #endif
 385
 386         return &user_mips64_view;
 387 }
 388
 389 long arch_ptrace(struct task_struct *child, long request,
 390                  unsigned long addr, unsigned long data)
 391 {
 392         int ret;
 393         void __user *addrp = (void __user *) addr;
 394         void __user *datavp = (void __user *) data;
 395         unsigned long __user *datalp = (void __user *) data;
 396
 397         switch (request) {
 398         /* when I and D space are separate, these will need to be fixed. */
 399         case PTRACE_PEEKTEXT: /* read word at location addr. */
 400         case PTRACE_PEEKDATA:
 401                 ret = generic_ptrace_peekdata(child, addr, data);
 402                 break;
 403
 404         /* Read the word at location addr in the USER area. */
 405         case PTRACE_PEEKUSR: {
 406                 struct pt_regs *regs;
 407                 unsigned long tmp = 0;
 408
 409                 regs = task_pt_regs(child);
 410                 ret = 0;  /* Default return value. */
 411
 412                 switch (addr) {
 413                 case 0 ... 31:
 414                         tmp = regs->regs[addr];
 415                         break;
 416                 case FPR_BASE ... FPR_BASE + 31:
 417                         if (tsk_used_math(child)) {
 418                                 fpureg_t *fregs = get_fpu_regs(child);
 419
 420 #ifdef CONFIG_32BIT
 421                                 /*
 422                                  * The odd registers are actually the high
 423                                  * order bits of the values stored in the even
 424                                  * registers - unless we're using r2k_switch.S.
 425                                  */
 426                                 if (addr & 1)
 427                                         tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
 428                                 else
 429                                         tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
 430 #endif
 431 #ifdef CONFIG_64BIT
 432                                 tmp = fregs[addr - FPR_BASE];
 433 #endif
 434                         } else {
 435                                 tmp = -1;       /* FP not yet used  */
 436                         }
 437                         break;
 438                 case PC:
 439                         tmp = regs->cp0_epc;
 440                         break;
 441                 case CAUSE:
 442                         tmp = regs->cp0_cause;
 443                         break;
 444                 case BADVADDR:
 445                         tmp = regs->cp0_badvaddr;
 446                         break;
 447                 case MMHI:
 448                         tmp = regs->hi;
 449                         break;
 450                 case MMLO:
 451                         tmp = regs->lo;
 452                         break;
 453 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 454                 case ACX:
 455                         tmp = regs->acx;
 456                         break;
 457 #endif
 458                 case FPC_CSR:
 459                         tmp = child->thread.fpu.fcr31;
 460                         break;
 461                 case FPC_EIR: { /* implementation / version register */
 462                         unsigned int flags;
 463 #ifdef CONFIG_MIPS_MT_SMTC
 464                         unsigned long irqflags;
 465                         unsigned int mtflags;
 466 #endif /* CONFIG_MIPS_MT_SMTC */
 467
 468                         preempt_disable();
 469                         if (!cpu_has_fpu) {
 470                                 preempt_enable();
 471                                 break;
 472                         }
 473
 474 #ifdef CONFIG_MIPS_MT_SMTC
 475                         /* Read-modify-write of Status must be atomic */
 476                         local_irq_save(irqflags);
 477                         mtflags = dmt();
 478 #endif /* CONFIG_MIPS_MT_SMTC */
 479                         if (cpu_has_mipsmt) {
 480                                 unsigned int vpflags = dvpe();
 481                                 flags = read_c0_status();
 482                                 __enable_fpu();
 483                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 484                                 write_c0_status(flags);
 485                                 evpe(vpflags);
 486                         } else {
 487                                 flags = read_c0_status();
 488                                 __enable_fpu();
 489                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 490                                 write_c0_status(flags);
 491                         }
 492 #ifdef CONFIG_MIPS_MT_SMTC
 493                         emt(mtflags);
 494                         local_irq_restore(irqflags);
 495 #endif /* CONFIG_MIPS_MT_SMTC */
 496                         preempt_enable();
 497                         break;
 498                 }
 499                 case DSP_BASE ... DSP_BASE + 5: {
 500                         dspreg_t *dregs;
 501
 502                         if (!cpu_has_dsp) {
 503                                 tmp = 0;
 504                                 ret = -EIO;
 505                                 goto out;
 506                         }
 507                         dregs = __get_dsp_regs(child);
 508                         tmp = (unsigned long) (dregs[addr - DSP_BASE]);
 509                         break;
 510                 }
 511                 case DSP_CONTROL:
 512                         if (!cpu_has_dsp) {
 513                                 tmp = 0;
 514                                 ret = -EIO;
 515                                 goto out;
 516                         }
 517                         tmp = child->thread.dsp.dspcontrol;
 518                         break;
 519                 default:
 520                         tmp = 0;
 521                         ret = -EIO;
 522                         goto out;
 523                 }
 524                 ret = put_user(tmp, datalp);
 525                 break;
 526         }
 527
 528         /* when I and D space are separate, this will have to be fixed. */
 529         case PTRACE_POKETEXT: /* write the word at location addr. */
 530         case PTRACE_POKEDATA:
 531                 ret = generic_ptrace_pokedata(child, addr, data);
 532                 break;
 533
 534         case PTRACE_POKEUSR: {
 535                 struct pt_regs *regs;
 536                 ret = 0;
 537                 regs = task_pt_regs(child);
 538
 539                 switch (addr) {
 540                 case 0 ... 31:
 541                         regs->regs[addr] = data;
 542                         break;
 543                 case FPR_BASE ... FPR_BASE + 31: {
 544                         fpureg_t *fregs = get_fpu_regs(child);
 545
 546                         if (!tsk_used_math(child)) {
 547                                 /* FP not yet used  */
 548                                 memset(&child->thread.fpu, ~0,
 549                                        sizeof(child->thread.fpu));
 550                                 child->thread.fpu.fcr31 = 0;
 551                         }
 552 #ifdef CONFIG_32BIT
 553                         /*
 554                          * The odd registers are actually the high order bits
 555                          * of the values stored in the even registers - unless
 556                          * we're using r2k_switch.S.
 557                          */
 558                         if (addr & 1) {
 559                                 fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
 560                                 fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
 561                         } else {
 562                                 fregs[addr - FPR_BASE] &= ~0xffffffffLL;
 563                                 fregs[addr - FPR_BASE] |= data;
 564                         }
 565 #endif
 566 #ifdef CONFIG_64BIT
 567                         fregs[addr - FPR_BASE] = data;
 568 #endif
 569                         break;
 570                 }
 571                 case PC:
 572                         regs->cp0_epc = data;
 573                         break;
 574                 case MMHI:
 575                         regs->hi = data;
 576                         break;
 577                 case MMLO:
 578                         regs->lo = data;
 579                         break;
 580 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 581                 case ACX:
 582                         regs->acx = data;
 583                         break;
 584 #endif
 585                 case FPC_CSR:
 586                         child->thread.fpu.fcr31 = data;
 587                         break;
 588                 case DSP_BASE ... DSP_BASE + 5: {
 589                         dspreg_t *dregs;
 590
 591                         if (!cpu_has_dsp) {
 592                                 ret = -EIO;
 593                                 break;
 594                         }
 595
 596                         dregs = __get_dsp_regs(child);
 597                         dregs[addr - DSP_BASE] = data;
 598                         break;
 599                 }
 600                 case DSP_CONTROL:
 601                         if (!cpu_has_dsp) {
 602                                 ret = -EIO;
 603                                 break;
 604                         }
 605                         child->thread.dsp.dspcontrol = data;
 606                         break;
 607                 default:
 608                         /* The rest are not allowed. */
 609                         ret = -EIO;
 610                         break;
 611                 }
 612                 break;
 613                 }
 614
 615         case PTRACE_GETREGS:
 616                 ret = ptrace_getregs(child, datavp);
 617                 break;
 618
 619         case PTRACE_SETREGS:
 620                 ret = ptrace_setregs(child, datavp);
 621                 break;
 622
 623         case PTRACE_GETFPREGS:
 624                 ret = ptrace_getfpregs(child, datavp);
 625                 break;
 626
 627         case PTRACE_SETFPREGS:
 628                 ret = ptrace_setfpregs(child, datavp);
 629                 break;
 630
 631         case PTRACE_GET_THREAD_AREA:
 632                 ret = put_user(task_thread_info(child)->tp_value, datalp);
 633                 break;
 634
 635         case PTRACE_GET_WATCH_REGS:
 636                 ret = ptrace_get_watch_regs(child, addrp);
 637                 break;
 638
 639         case PTRACE_SET_WATCH_REGS:
 640                 ret = ptrace_set_watch_regs(child, addrp);
 641                 break;
 642
 643         default:
 644                 ret = ptrace_request(child, request, addr, data);
 645                 break;
 646         }
 647  out:
 648         return ret;
 649 }
 650
 651 /*
 652  * Notification of system call entry/exit
 653  * - triggered by current->work.syscall_trace
 654  */
 655 asmlinkage void syscall_trace_enter(struct pt_regs *regs)
 656 {
 657         long ret = 0;
 658         user_exit();
 659
 660         /* do the secure computing check first */
 661         secure_computing_strict(regs->regs[2]);
 662
 663         if (test_thread_flag(TIF_SYSCALL_TRACE) &&
 664             tracehook_report_syscall_entry(regs))
 665                 ret = -1;
 666
 667         audit_syscall_entry(__syscall_get_arch(),
 668                             regs->regs[2],
 669                             regs->regs[4], regs->regs[5],
 670                             regs->regs[6], regs->regs[7]);
 671 }
 672
 673 /*
 674  * Notification of system call entry/exit
 675  * - triggered by current->work.syscall_trace
 676  */
 677 asmlinkage void syscall_trace_leave(struct pt_regs *regs)
 678 {
 679         /*
 680          * We may come here right after calling schedule_user()
 681          * or do_notify_resume(), in which case we can be in RCU
 682          * user mode.
 683          */
 684         user_exit();
 685
 686         audit_syscall_exit(regs);
 687
 688         if (test_thread_flag(TIF_SYSCALL_TRACE))
 689                 tracehook_report_syscall_exit(regs, 0);
 690
 691         user_enter();
 692 }