arch/mips/kernel/smp-bmips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
   7  *
   8  * SMP support for BMIPS
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/sched.h>
  13 #include <linux/sched/hotplug.h>
  14 #include <linux/mm.h>
  15 #include <linux/delay.h>
  16 #include <linux/smp.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/cpu.h>
  20 #include <linux/cpumask.h>
  21 #include <linux/reboot.h>
  22 #include <linux/io.h>
  23 #include <linux/compiler.h>
  24 #include <linux/linkage.h>
  25 #include <linux/bug.h>
  26 #include <linux/kernel.h>
  27
  28 #include <asm/time.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/processor.h>
  31 #include <asm/bootinfo.h>
  32 #include <asm/pmon.h>
  33 #include <asm/cacheflush.h>
  34 #include <asm/tlbflush.h>
  35 #include <asm/mipsregs.h>
  36 #include <asm/bmips.h>
  37 #include <asm/traps.h>
  38 #include <asm/barrier.h>
  39 #include <asm/cpu-features.h>
  40
  41 static int __maybe_unused max_cpus = 1;
  42
  43 /* these may be configured by the platform code */
  44 int bmips_smp_enabled = 1;
  45 int bmips_cpu_offset;
  46 cpumask_t bmips_booted_mask;
  47 unsigned long bmips_tp1_irqs = IE_IRQ1;
  48
  49 #define RESET_FROM_KSEG0                0x80080800
  50 #define RESET_FROM_KSEG1                0xa0080800
  51
  52 static void bmips_set_reset_vec(int cpu, u32 val);
  53
  54 #ifdef CONFIG_SMP
  55
  56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
  57 unsigned long bmips_smp_boot_sp;
  58 unsigned long bmips_smp_boot_gp;
  59
  60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
  61 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
  62 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
  63 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
  64
  65 /* SW interrupts 0,1 are used for interprocessor signaling */
  66 #define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
  67 #define IPI1_IRQ                        (MIPS_CPU_IRQ_BASE + 1)
  68
  69 #define CPUNUM(cpu, shift)              (((cpu) + bmips_cpu_offset) << (shift))
  70 #define ACTION_CLR_IPI(cpu, ipi)        (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  71 #define ACTION_SET_IPI(cpu, ipi)        (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  72 #define ACTION_BOOT_THREAD(cpu)         (0x08 | CPUNUM(cpu, 0))
  73
  74 static void __init bmips_smp_setup(void)
  75 {
  76         int i, cpu = 1, boot_cpu = 0;
  77         int cpu_hw_intr;
  78
  79         switch (current_cpu_type()) {
  80         case CPU_BMIPS4350:
  81         case CPU_BMIPS4380:
  82                 /* arbitration priority */
  83                 clear_c0_brcm_cmt_ctrl(0x30);
  84
  85                 /* NBK and weak order flags */
  86                 set_c0_brcm_config_0(0x30000);
  87
  88                 /* Find out if we are running on TP0 or TP1 */
  89                 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
  90
  91                 /*
  92                  * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
  93                  * thread
  94                  * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  95                  * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  96                  */
  97                 if (boot_cpu == 0)
  98                         cpu_hw_intr = 0x02;
  99                 else
 100                         cpu_hw_intr = 0x1d;
 101
 102                 change_c0_brcm_cmt_intr(0xf8018000,
 103                                         (cpu_hw_intr << 27) | (0x03 << 15));
 104
 105                 /* single core, 2 threads (2 pipelines) */
 106                 max_cpus = 2;
 107
 108                 break;
 109         case CPU_BMIPS5000:
 110                 /* enable raceless SW interrupts */
 111                 set_c0_brcm_config(0x03 << 22);
 112
 113                 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
 114                 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
 115
 116                 /* N cores, 2 threads per core */
 117                 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
 118
 119                 /* clear any pending SW interrupts */
 120                 for (i = 0; i < max_cpus; i++) {
 121                         write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
 122                         write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
 123                 }
 124
 125                 break;
 126         default:
 127                 max_cpus = 1;
 128         }
 129
 130         if (!bmips_smp_enabled)
 131                 max_cpus = 1;
 132
 133         /* this can be overridden by the BSP */
 134         if (!board_ebase_setup)
 135                 board_ebase_setup = &bmips_ebase_setup;
 136
 137         __cpu_number_map[boot_cpu] = 0;
 138         __cpu_logical_map[0] = boot_cpu;
 139
 140         for (i = 0; i < max_cpus; i++) {
 141                 if (i != boot_cpu) {
 142                         __cpu_number_map[i] = cpu;
 143                         __cpu_logical_map[cpu] = i;
 144                         cpu++;
 145                 }
 146                 set_cpu_possible(i, 1);
 147                 set_cpu_present(i, 1);
 148         }
 149 }
 150
 151 /*
 152  * IPI IRQ setup - runs on CPU0
 153  */
 154 static void bmips_prepare_cpus(unsigned int max_cpus)
 155 {
 156         irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
 157
 158         switch (current_cpu_type()) {
 159         case CPU_BMIPS4350:
 160         case CPU_BMIPS4380:
 161                 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
 162                 break;
 163         case CPU_BMIPS5000:
 164                 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
 165                 break;
 166         default:
 167                 return;
 168         }
 169
 170         if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
 171                         "smp_ipi0", NULL))
 172                 panic("Can't request IPI0 interrupt");
 173         if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
 174                         "smp_ipi1", NULL))
 175                 panic("Can't request IPI1 interrupt");
 176 }
 177
 178 /*
 179  * Tell the hardware to boot CPUx - runs on CPU0
 180  */
 181 static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 182 {
 183         bmips_smp_boot_sp = __KSTK_TOS(idle);
 184         bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
 185         mb();
 186
 187         /*
 188          * Initial boot sequence for secondary CPU:
 189          *   bmips_reset_nmi_vec @ a000_0000 ->
 190          *   bmips_smp_entry ->
 191          *   plat_wired_tlb_setup (cached function call; optional) ->
 192          *   start_secondary (cached jump)
 193          *
 194          * Warm restart sequence:
 195          *   play_dead WAIT loop ->
 196          *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
 197          *   eret to play_dead ->
 198          *   bmips_secondary_reentry ->
 199          *   start_secondary
 200          */
 201
 202         pr_info("SMP: Booting CPU%d...\n", cpu);
 203
 204         if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
 205                 /* kseg1 might not exist if this CPU enabled XKS01 */
 206                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
 207
 208                 switch (current_cpu_type()) {
 209                 case CPU_BMIPS4350:
 210                 case CPU_BMIPS4380:
 211                         bmips43xx_send_ipi_single(cpu, 0);
 212                         break;
 213                 case CPU_BMIPS5000:
 214                         bmips5000_send_ipi_single(cpu, 0);
 215                         break;
 216                 }
 217         } else {
 218                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
 219
 220                 switch (current_cpu_type()) {
 221                 case CPU_BMIPS4350:
 222                 case CPU_BMIPS4380:
 223                         /* Reset slave TP1 if booting from TP0 */
 224                         if (cpu_logical_map(cpu) == 1)
 225                                 set_c0_brcm_cmt_ctrl(0x01);
 226                         break;
 227                 case CPU_BMIPS5000:
 228                         write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
 229                         break;
 230                 }
 231                 cpumask_set_cpu(cpu, &bmips_booted_mask);
 232         }
 233 }
 234
 235 /*
 236  * Early setup - runs on secondary CPU after cache probe
 237  */
 238 static void bmips_init_secondary(void)
 239 {
 240         switch (current_cpu_type()) {
 241         case CPU_BMIPS4350:
 242         case CPU_BMIPS4380:
 243                 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
 244                 break;
 245         case CPU_BMIPS5000:
 246                 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 247                 current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
 248                 break;
 249         }
 250 }
 251
 252 /*
 253  * Late setup - runs on secondary CPU before entering the idle loop
 254  */
 255 static void bmips_smp_finish(void)
 256 {
 257         pr_info("SMP: CPU%d is running\n", smp_processor_id());
 258
 259         /* make sure there won't be a timer interrupt for a little while */
 260         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 261
 262         irq_enable_hazard();
 263         set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
 264         irq_enable_hazard();
 265 }
 266
 267 /*
 268  * BMIPS5000 raceless IPIs
 269  *
 270  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
 271  * IPI0 is used for SMP_RESCHEDULE_YOURSELF
 272  * IPI1 is used for SMP_CALL_FUNCTION
 273  */
 274
 275 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
 276 {
 277         write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
 278 }
 279
 280 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
 281 {
 282         int action = irq - IPI0_IRQ;
 283
 284         write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
 285
 286         if (action == 0)
 287                 scheduler_ipi();
 288         else
 289                 generic_smp_call_function_interrupt();
 290
 291         return IRQ_HANDLED;
 292 }
 293
 294 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
 295         unsigned int action)
 296 {
 297         unsigned int i;
 298
 299         for_each_cpu(i, mask)
 300                 bmips5000_send_ipi_single(i, action);
 301 }
 302
 303 /*
 304  * BMIPS43xx racey IPIs
 305  *
 306  * We use one inbound SW IRQ for each CPU.
 307  *
 308  * A spinlock must be held in order to keep CPUx from accidentally clearing
 309  * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
 310  * same spinlock is used to protect the action masks.
 311  */
 312
 313 static DEFINE_SPINLOCK(ipi_lock);
 314 static DEFINE_PER_CPU(int, ipi_action_mask);
 315
 316 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
 317 {
 318         unsigned long flags;
 319
 320         spin_lock_irqsave(&ipi_lock, flags);
 321         set_c0_cause(cpu ? C_SW1 : C_SW0);
 322         per_cpu(ipi_action_mask, cpu) |= action;
 323         irq_enable_hazard();
 324         spin_unlock_irqrestore(&ipi_lock, flags);
 325 }
 326
 327 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
 328 {
 329         unsigned long flags;
 330         int action, cpu = irq - IPI0_IRQ;
 331
 332         spin_lock_irqsave(&ipi_lock, flags);
 333         action = __this_cpu_read(ipi_action_mask);
 334         per_cpu(ipi_action_mask, cpu) = 0;
 335         clear_c0_cause(cpu ? C_SW1 : C_SW0);
 336         spin_unlock_irqrestore(&ipi_lock, flags);
 337
 338         if (action & SMP_RESCHEDULE_YOURSELF)
 339                 scheduler_ipi();
 340         if (action & SMP_CALL_FUNCTION)
 341                 generic_smp_call_function_interrupt();
 342
 343         return IRQ_HANDLED;
 344 }
 345
 346 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
 347         unsigned int action)
 348 {
 349         unsigned int i;
 350
 351         for_each_cpu(i, mask)
 352                 bmips43xx_send_ipi_single(i, action);
 353 }
 354
 355 #ifdef CONFIG_HOTPLUG_CPU
 356
 357 static int bmips_cpu_disable(void)
 358 {
 359         unsigned int cpu = smp_processor_id();
 360
 361         if (cpu == 0)
 362                 return -EBUSY;
 363
 364         pr_info("SMP: CPU%d is offline\n", cpu);
 365
 366         set_cpu_online(cpu, false);
 367         calculate_cpu_foreign_map();
 368         irq_cpu_offline();
 369         clear_c0_status(IE_IRQ5);
 370
 371         local_flush_tlb_all();
 372         local_flush_icache_range(0, ~0);
 373
 374         return 0;
 375 }
 376
 377 static void bmips_cpu_die(unsigned int cpu)
 378 {
 379 }
 380
 381 void __ref play_dead(void)
 382 {
 383         idle_task_exit();
 384
 385         /* flush data cache */
 386         _dma_cache_wback_inv(0, ~0);
 387
 388         /*
 389          * Wakeup is on SW0 or SW1; disable everything else
 390          * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
 391          * IRQ handlers; this clears ST0_IE and returns immediately.
 392          */
 393         clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
 394         change_c0_status(
 395                 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
 396                 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
 397         irq_disable_hazard();
 398
 399         /*
 400          * wait for SW interrupt from bmips_boot_secondary(), then jump
 401          * back to start_secondary()
 402          */
 403         __asm__ __volatile__(
 404         "       wait\n"
 405         "       j       bmips_secondary_reentry\n"
 406         : : : "memory");
 407 }
 408
 409 #endif /* CONFIG_HOTPLUG_CPU */
 410
 411 struct plat_smp_ops bmips43xx_smp_ops = {
 412         .smp_setup              = bmips_smp_setup,
 413         .prepare_cpus           = bmips_prepare_cpus,
 414         .boot_secondary         = bmips_boot_secondary,
 415         .smp_finish             = bmips_smp_finish,
 416         .init_secondary         = bmips_init_secondary,
 417         .send_ipi_single        = bmips43xx_send_ipi_single,
 418         .send_ipi_mask          = bmips43xx_send_ipi_mask,
 419 #ifdef CONFIG_HOTPLUG_CPU
 420         .cpu_disable            = bmips_cpu_disable,
 421         .cpu_die                = bmips_cpu_die,
 422 #endif
 423 };
 424
 425 struct plat_smp_ops bmips5000_smp_ops = {
 426         .smp_setup              = bmips_smp_setup,
 427         .prepare_cpus           = bmips_prepare_cpus,
 428         .boot_secondary         = bmips_boot_secondary,
 429         .smp_finish             = bmips_smp_finish,
 430         .init_secondary         = bmips_init_secondary,
 431         .send_ipi_single        = bmips5000_send_ipi_single,
 432         .send_ipi_mask          = bmips5000_send_ipi_mask,
 433 #ifdef CONFIG_HOTPLUG_CPU
 434         .cpu_disable            = bmips_cpu_disable,
 435         .cpu_die                = bmips_cpu_die,
 436 #endif
 437 };
 438
 439 #endif /* CONFIG_SMP */
 440
 441 /***********************************************************************
 442  * BMIPS vector relocation
 443  * This is primarily used for SMP boot, but it is applicable to some
 444  * UP BMIPS systems as well.
 445  ***********************************************************************/
 446
 447 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
 448 {
 449         memcpy((void *)dst, start, end - start);
 450         dma_cache_wback(dst, end - start);
 451         local_flush_icache_range(dst, dst + (end - start));
 452         instruction_hazard();
 453 }
 454
 455 static inline void bmips_nmi_handler_setup(void)
 456 {
 457         bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
 458                 &bmips_reset_nmi_vec_end);
 459         bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
 460                 &bmips_smp_int_vec_end);
 461 }
 462
 463 struct reset_vec_info {
 464         int cpu;
 465         u32 val;
 466 };
 467
 468 static void bmips_set_reset_vec_remote(void *vinfo)
 469 {
 470         struct reset_vec_info *info = vinfo;
 471         int shift = info->cpu & 0x01 ? 16 : 0;
 472         u32 mask = ~(0xffff << shift), val = info->val >> 16;
 473
 474         preempt_disable();
 475         if (smp_processor_id() > 0) {
 476                 smp_call_function_single(0, &bmips_set_reset_vec_remote,
 477                                          info, 1);
 478         } else {
 479                 if (info->cpu & 0x02) {
 480                         /* BMIPS5200 "should" use mask/shift, but it's buggy */
 481                         bmips_write_zscm_reg(0xa0, (val << 16) | val);
 482                         bmips_read_zscm_reg(0xa0);
 483                 } else {
 484                         write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
 485                                               (val << shift));
 486                 }
 487         }
 488         preempt_enable();
 489 }
 490
 491 static void bmips_set_reset_vec(int cpu, u32 val)
 492 {
 493         struct reset_vec_info info;
 494
 495         if (current_cpu_type() == CPU_BMIPS5000) {
 496                 /* this needs to run from CPU0 (which is always online) */
 497                 info.cpu = cpu;
 498                 info.val = val;
 499                 bmips_set_reset_vec_remote(&info);
 500         } else {
 501                 void __iomem *cbr = BMIPS_GET_CBR();
 502
 503                 if (cpu == 0)
 504                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
 505                 else {
 506                         if (current_cpu_type() != CPU_BMIPS4380)
 507                                 return;
 508                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
 509                 }
 510         }
 511         __sync();
 512         back_to_back_c0_hazard();
 513 }
 514
 515 void bmips_ebase_setup(void)
 516 {
 517         unsigned long new_ebase = ebase;
 518
 519         BUG_ON(ebase != CKSEG0);
 520
 521         switch (current_cpu_type()) {
 522         case CPU_BMIPS4350:
 523                 /*
 524                  * BMIPS4350 cannot relocate the normal vectors, but it
 525                  * can relocate the BEV=1 vectors.  So CPU1 starts up at
 526                  * the relocated BEV=1, IV=0 general exception vector @
 527                  * 0xa000_0380.
 528                  *
 529                  * set_uncached_handler() is used here because:
 530                  *  - CPU1 will run this from uncached space
 531                  *  - None of the cacheflush functions are set up yet
 532                  */
 533                 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
 534                         &bmips_smp_int_vec, 0x80);
 535                 __sync();
 536                 return;
 537         case CPU_BMIPS3300:
 538         case CPU_BMIPS4380:
 539                 /*
 540                  * 0x8000_0000: reset/NMI (initially in kseg1)
 541                  * 0x8000_0400: normal vectors
 542                  */
 543                 new_ebase = 0x80000400;
 544                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 545                 break;
 546         case CPU_BMIPS5000:
 547                 /*
 548                  * 0x8000_0000: reset/NMI (initially in kseg1)
 549                  * 0x8000_1000: normal vectors
 550                  */
 551                 new_ebase = 0x80001000;
 552                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 553                 write_c0_ebase(new_ebase);
 554                 break;
 555         default:
 556                 return;
 557         }
 558
 559         board_nmi_handler_setup = &bmips_nmi_handler_setup;
 560         ebase = new_ebase;
 561 }
 562
 563 asmlinkage void __weak plat_wired_tlb_setup(void)
 564 {
 565         /*
 566          * Called when starting/restarting a secondary CPU.
 567          * Kernel stacks and other important data might only be accessible
 568          * once the wired entries are present.
 569          */
 570 }
 571
 572 void __init bmips_cpu_setup(void)
 573 {
 574         void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
 575         u32 __maybe_unused cfg;
 576
 577         switch (current_cpu_type()) {
 578         case CPU_BMIPS3300:
 579                 /* Set BIU to async mode */
 580                 set_c0_brcm_bus_pll(BIT(22));
 581                 __sync();
 582
 583                 /* put the BIU back in sync mode */
 584                 clear_c0_brcm_bus_pll(BIT(22));
 585
 586                 /* clear BHTD to enable branch history table */
 587                 clear_c0_brcm_reset(BIT(16));
 588
 589                 /* Flush and enable RAC */
 590                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 591                 __raw_writel(cfg | 0x100, BMIPS_RAC_CONFIG);
 592                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 593
 594                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 595                 __raw_writel(cfg | 0xf, BMIPS_RAC_CONFIG);
 596                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 597
 598                 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 599                 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
 600                 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 601                 break;
 602
 603         case CPU_BMIPS4380:
 604                 /* CBG workaround for early BMIPS4380 CPUs */
 605                 switch (read_c0_prid()) {
 606                 case 0x2a040:
 607                 case 0x2a042:
 608                 case 0x2a044:
 609                 case 0x2a060:
 610                         cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
 611                         __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
 612                         __raw_readl(cbr + BMIPS_L2_CONFIG);
 613                 }
 614
 615                 /* clear BHTD to enable branch history table */
 616                 clear_c0_brcm_config_0(BIT(21));
 617
 618                 /* XI/ROTR enable */
 619                 set_c0_brcm_config_0(BIT(23));
 620                 set_c0_brcm_cmt_ctrl(BIT(15));
 621                 break;
 622
 623         case CPU_BMIPS5000:
 624                 /* enable RDHWR, BRDHWR */
 625                 set_c0_brcm_config(BIT(17) | BIT(21));
 626
 627                 /* Disable JTB */
 628                 __asm__ __volatile__(
 629                 "       .set    noreorder\n"
 630                 "       li      $8, 0x5a455048\n"
 631                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 632                 "       .word   0x4008b008\n"   /* mfc0 t0, $22, 8 */
 633                 "       li      $9, 0x00008000\n"
 634                 "       or      $8, $8, $9\n"
 635                 "       .word   0x4088b008\n"   /* mtc0 t0, $22, 8 */
 636                 "       sync\n"
 637                 "       li      $8, 0x0\n"
 638                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 639                 "       .set    reorder\n"
 640                 : : : "$8", "$9");
 641
 642                 /* XI enable */
 643                 set_c0_brcm_config(BIT(27));
 644
 645                 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
 646                 __asm__ __volatile__(
 647                 "       li      $8, 0x5a455048\n"
 648                 "       .word   0x4088b00f\n"   /* mtc0 $8, $22, 15 */
 649                 "       nop; nop; nop\n"
 650                 "       .word   0x4008b008\n"   /* mfc0 $8, $22, 8 */
 651                 "       lui     $9, 0x0100\n"
 652                 "       or      $8, $9\n"
 653                 "       .word   0x4088b008\n"   /* mtc0 $8, $22, 8 */
 654                 : : : "$8", "$9");
 655                 break;
 656         }
 657 }