2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
8 * SMP support for BMIPS
11 #include <linux/init.h>
12 #include <linux/sched.h>
14 #include <linux/delay.h>
15 #include <linux/smp.h>
16 #include <linux/interrupt.h>
17 #include <linux/spinlock.h>
18 #include <linux/cpu.h>
19 #include <linux/cpumask.h>
20 #include <linux/reboot.h>
22 #include <linux/compiler.h>
23 #include <linux/linkage.h>
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
28 #include <asm/pgtable.h>
29 #include <asm/processor.h>
30 #include <asm/bootinfo.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <asm/mipsregs.h>
35 #include <asm/bmips.h>
36 #include <asm/traps.h>
37 #include <asm/barrier.h>
39 static int __maybe_unused max_cpus = 1;
41 /* these may be configured by the platform code */
42 int bmips_smp_enabled = 1;
44 cpumask_t bmips_booted_mask;
48 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
49 unsigned long bmips_smp_boot_sp;
50 unsigned long bmips_smp_boot_gp;
52 static void bmips_send_ipi_single(int cpu, unsigned int action);
53 static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
55 /* SW interrupts 0,1 are used for interprocessor signaling */
56 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
57 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
59 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
60 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
61 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
62 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
64 static void __init bmips_smp_setup(void)
66 int i, cpu = 1, boot_cpu = 0;
68 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
69 /* arbitration priority */
70 clear_c0_brcm_cmt_ctrl(0x30);
72 /* NBK and weak order flags */
73 set_c0_brcm_config_0(0x30000);
75 /* Find out if we are running on TP0 or TP1 */
76 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
79 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
80 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
81 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
83 * If booting from TP1, leave the existing CMT interrupt routing
84 * such that TP0 responds to SW1 and TP1 responds to SW0.
87 change_c0_brcm_cmt_intr(0xf8018000,
88 (0x02 << 27) | (0x03 << 15));
90 change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
92 /* single core, 2 threads (2 pipelines) */
94 #elif defined(CONFIG_CPU_BMIPS5000)
95 /* enable raceless SW interrupts */
96 set_c0_brcm_config(0x03 << 22);
98 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
99 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
101 /* N cores, 2 threads per core */
102 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
104 /* clear any pending SW interrupts */
105 for (i = 0; i < max_cpus; i++) {
106 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
107 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
111 if (!bmips_smp_enabled)
114 /* this can be overridden by the BSP */
115 if (!board_ebase_setup)
116 board_ebase_setup = &bmips_ebase_setup;
118 __cpu_number_map[boot_cpu] = 0;
119 __cpu_logical_map[0] = boot_cpu;
121 for (i = 0; i < max_cpus; i++) {
123 __cpu_number_map[i] = cpu;
124 __cpu_logical_map[cpu] = i;
127 set_cpu_possible(i, 1);
128 set_cpu_present(i, 1);
133 * IPI IRQ setup - runs on CPU0
135 static void bmips_prepare_cpus(unsigned int max_cpus)
137 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
139 panic("Can't request IPI0 interrupt\n");
140 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
142 panic("Can't request IPI1 interrupt\n");
146 * Tell the hardware to boot CPUx - runs on CPU0
148 static void bmips_boot_secondary(int cpu, struct task_struct *idle)
150 bmips_smp_boot_sp = __KSTK_TOS(idle);
151 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
155 * Initial boot sequence for secondary CPU:
156 * bmips_reset_nmi_vec @ a000_0000 ->
158 * plat_wired_tlb_setup (cached function call; optional) ->
159 * start_secondary (cached jump)
161 * Warm restart sequence:
162 * play_dead WAIT loop ->
163 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
164 * eret to play_dead ->
165 * bmips_secondary_reentry ->
169 pr_info("SMP: Booting CPU%d...\n", cpu);
171 if (cpumask_test_cpu(cpu, &bmips_booted_mask))
172 bmips_send_ipi_single(cpu, 0);
174 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
175 /* Reset slave TP1 if booting from TP0 */
176 if (cpu_logical_map(cpu) == 1)
177 set_c0_brcm_cmt_ctrl(0x01);
178 #elif defined(CONFIG_CPU_BMIPS5000)
180 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
183 * core N thread 0 was already booted; just
186 bmips_write_zscm_reg(0x210, 0xc0000000);
188 bmips_write_zscm_reg(0x210, 0x00);
191 cpumask_set_cpu(cpu, &bmips_booted_mask);
196 * Early setup - runs on secondary CPU after cache probe
198 static void bmips_init_secondary(void)
200 /* move NMI vector to kseg0, in case XKS01 is enabled */
202 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
203 void __iomem *cbr = BMIPS_GET_CBR();
204 unsigned long old_vec;
206 old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
207 __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
209 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
210 #elif defined(CONFIG_CPU_BMIPS5000)
211 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
212 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
214 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
219 * Late setup - runs on secondary CPU before entering the idle loop
221 static void bmips_smp_finish(void)
223 pr_info("SMP: CPU%d is running\n", smp_processor_id());
225 /* make sure there won't be a timer interrupt for a little while */
226 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
229 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
234 * Runs on CPU0 after all CPUs have been booted
236 static void bmips_cpus_done(void)
240 #if defined(CONFIG_CPU_BMIPS5000)
243 * BMIPS5000 raceless IPIs
245 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
246 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
247 * IPI1 is used for SMP_CALL_FUNCTION
250 static void bmips_send_ipi_single(int cpu, unsigned int action)
252 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
255 static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
257 int action = irq - IPI0_IRQ;
259 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
264 smp_call_function_interrupt();
272 * BMIPS43xx racey IPIs
274 * We use one inbound SW IRQ for each CPU.
276 * A spinlock must be held in order to keep CPUx from accidentally clearing
277 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
278 * same spinlock is used to protect the action masks.
281 static DEFINE_SPINLOCK(ipi_lock);
282 static DEFINE_PER_CPU(int, ipi_action_mask);
284 static void bmips_send_ipi_single(int cpu, unsigned int action)
288 spin_lock_irqsave(&ipi_lock, flags);
289 set_c0_cause(cpu ? C_SW1 : C_SW0);
290 per_cpu(ipi_action_mask, cpu) |= action;
292 spin_unlock_irqrestore(&ipi_lock, flags);
295 static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
298 int action, cpu = irq - IPI0_IRQ;
300 spin_lock_irqsave(&ipi_lock, flags);
301 action = __get_cpu_var(ipi_action_mask);
302 per_cpu(ipi_action_mask, cpu) = 0;
303 clear_c0_cause(cpu ? C_SW1 : C_SW0);
304 spin_unlock_irqrestore(&ipi_lock, flags);
306 if (action & SMP_RESCHEDULE_YOURSELF)
308 if (action & SMP_CALL_FUNCTION)
309 smp_call_function_interrupt();
314 #endif /* BMIPS type */
316 static void bmips_send_ipi_mask(const struct cpumask *mask,
321 for_each_cpu(i, mask)
322 bmips_send_ipi_single(i, action);
325 #ifdef CONFIG_HOTPLUG_CPU
327 static int bmips_cpu_disable(void)
329 unsigned int cpu = smp_processor_id();
334 pr_info("SMP: CPU%d is offline\n", cpu);
336 set_cpu_online(cpu, false);
337 cpu_clear(cpu, cpu_callin_map);
339 local_flush_tlb_all();
340 local_flush_icache_range(0, ~0);
345 static void bmips_cpu_die(unsigned int cpu)
349 void __ref play_dead(void)
353 /* flush data cache */
354 _dma_cache_wback_inv(0, ~0);
357 * Wakeup is on SW0 or SW1; disable everything else
358 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
359 * IRQ handlers; this clears ST0_IE and returns immediately.
361 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
362 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
363 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
364 irq_disable_hazard();
367 * wait for SW interrupt from bmips_boot_secondary(), then jump
368 * back to start_secondary()
370 __asm__ __volatile__(
372 " j bmips_secondary_reentry\n"
376 #endif /* CONFIG_HOTPLUG_CPU */
378 struct plat_smp_ops bmips_smp_ops = {
379 .smp_setup = bmips_smp_setup,
380 .prepare_cpus = bmips_prepare_cpus,
381 .boot_secondary = bmips_boot_secondary,
382 .smp_finish = bmips_smp_finish,
383 .init_secondary = bmips_init_secondary,
384 .cpus_done = bmips_cpus_done,
385 .send_ipi_single = bmips_send_ipi_single,
386 .send_ipi_mask = bmips_send_ipi_mask,
387 #ifdef CONFIG_HOTPLUG_CPU
388 .cpu_disable = bmips_cpu_disable,
389 .cpu_die = bmips_cpu_die,
393 #endif /* CONFIG_SMP */
395 /***********************************************************************
396 * BMIPS vector relocation
397 * This is primarily used for SMP boot, but it is applicable to some
398 * UP BMIPS systems as well.
399 ***********************************************************************/
401 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
403 memcpy((void *)dst, start, end - start);
404 dma_cache_wback((unsigned long)start, end - start);
405 local_flush_icache_range(dst, dst + (end - start));
406 instruction_hazard();
409 static inline void bmips_nmi_handler_setup(void)
411 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
412 &bmips_reset_nmi_vec_end);
413 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
414 &bmips_smp_int_vec_end);
417 void bmips_ebase_setup(void)
419 unsigned long new_ebase = ebase;
420 void __iomem __maybe_unused *cbr;
422 BUG_ON(ebase != CKSEG0);
424 #if defined(CONFIG_CPU_BMIPS4350)
426 * BMIPS4350 cannot relocate the normal vectors, but it
427 * can relocate the BEV=1 vectors. So CPU1 starts up at
428 * the relocated BEV=1, IV=0 general exception vector @
431 * set_uncached_handler() is used here because:
432 * - CPU1 will run this from uncached space
433 * - None of the cacheflush functions are set up yet
435 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
436 &bmips_smp_int_vec, 0x80);
439 #elif defined(CONFIG_CPU_BMIPS4380)
441 * 0x8000_0000: reset/NMI (initially in kseg1)
442 * 0x8000_0400: normal vectors
444 new_ebase = 0x80000400;
445 cbr = BMIPS_GET_CBR();
446 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
447 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
448 #elif defined(CONFIG_CPU_BMIPS5000)
450 * 0x8000_0000: reset/NMI (initially in kseg1)
451 * 0x8000_1000: normal vectors
453 new_ebase = 0x80001000;
454 write_c0_brcm_bootvec(0xa0088008);
455 write_c0_ebase(new_ebase);
457 bmips_write_zscm_reg(0xa0, 0xa008a008);
461 board_nmi_handler_setup = &bmips_nmi_handler_setup;
465 asmlinkage void __weak plat_wired_tlb_setup(void)
468 * Called when starting/restarting a secondary CPU.
469 * Kernel stacks and other important data might only be accessible
470 * once the wired entries are present.