2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
16 * Elizabeth Clarke (beth@mips.com)
17 * Ralf Baechle (ralf@linux-mips.org)
18 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/compiler.h>
26 #include <asm/atomic.h>
27 #include <asm/cacheflush.h>
29 #include <asm/processor.h>
30 #include <asm/system.h>
31 #include <asm/hardirq.h>
32 #include <asm/mmu_context.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mipsmtregs.h>
37 #include <asm/mips_mt.h>
38 #include <asm/mips-boards/maltaint.h> /* This is f*cking wrong */
40 #define MIPS_CPU_IPI_RESCHED_IRQ 0
41 #define MIPS_CPU_IPI_CALL_IRQ 1
43 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
46 static void dump_mtregisters(int vpe, int tc)
48 printk("vpe %d tc %d\n", vpe, tc);
52 printk(" c0 status 0x%lx\n", read_vpe_c0_status());
53 printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
54 printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0());
55 printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus());
56 printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart());
57 printk(" tcbind 0x%lx\n", read_tc_c0_tcbind());
58 printk(" tchalt 0x%lx\n", read_tc_c0_tchalt());
62 void __init sanitize_tlb_entries(void)
65 unsigned long mvpconf0, ncpu;
71 set_c0_mvpcontrol(MVPCONTROL_VPC);
73 back_to_back_c0_hazard();
75 /* Disable TLB sharing */
76 clear_c0_mvpcontrol(MVPCONTROL_STLB);
78 mvpconf0 = read_c0_mvpconf0();
80 printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
81 (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
82 (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
84 tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
85 ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
87 printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
90 /* share them out across the vpe's */
93 printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
95 for (i = 0; i < ncpu; i++) {
99 write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
101 write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
106 clear_c0_mvpcontrol(MVPCONTROL_VPC);
109 static void ipi_resched_dispatch (struct pt_regs *regs)
111 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ, regs);
114 static void ipi_call_dispatch (struct pt_regs *regs)
116 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ, regs);
119 irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs)
124 irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
126 smp_call_function_interrupt();
131 static struct irqaction irq_resched = {
132 .handler = ipi_resched_interrupt,
133 .flags = SA_INTERRUPT,
134 .name = "IPI_resched"
137 static struct irqaction irq_call = {
138 .handler = ipi_call_interrupt,
139 .flags = SA_INTERRUPT,
144 * Common setup before any secondaries are started
145 * Make sure all CPU's are in a sensible state before we boot any of the
148 void plat_smp_setup(void)
156 /* disable MT so we can configure */
160 mips_mt_set_cpuoptions();
162 /* Put MVPE's into 'configuration state' */
163 set_c0_mvpcontrol(MVPCONTROL_VPC);
165 val = read_c0_mvpconf0();
167 /* we'll always have more TC's than VPE's, so loop setting everything
168 to a sensible state */
169 for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) {
173 if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) {
175 /* deactivate all but vpe0 */
177 unsigned long tmp = read_vpe_c0_vpeconf0();
179 tmp &= ~VPECONF0_VPA;
183 write_vpe_c0_vpeconf0(tmp);
185 /* Record this as available CPU */
186 cpu_set(i, phys_cpu_present_map);
187 __cpu_number_map[i] = ++num;
188 __cpu_logical_map[num] = i;
191 /* disable multi-threading with TC's */
192 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
195 write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
197 /* set config to be the same as vpe0, particularly kseg0 coherency alg */
198 write_vpe_c0_config( read_c0_config());
200 /* make sure there are no software interrupts pending */
201 write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0));
203 /* Propagate Config7 */
204 write_vpe_c0_config7(read_c0_config7());
214 /* bind a TC to each VPE, May as well put all excess TC's
216 if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) )
217 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) );
219 write_tc_c0_tcbind( read_tc_c0_tcbind() | i);
222 write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT));
225 tmp = read_tc_c0_tcstatus();
227 /* mark not allocated and not dynamically allocatable */
228 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
229 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
230 write_tc_c0_tcstatus(tmp);
232 write_tc_c0_tchalt(TCHALT_H);
236 /* Release config state */
237 clear_c0_mvpcontrol(MVPCONTROL_VPC);
239 /* We'll wait until starting the secondaries before starting MVPE */
241 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
244 void __init plat_prepare_cpus(unsigned int max_cpus)
246 /* set up ipi interrupts */
248 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
249 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
252 cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
253 cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
255 setup_irq(cpu_ipi_resched_irq, &irq_resched);
256 setup_irq(cpu_ipi_call_irq, &irq_call);
258 /* need to mark IPI's as IRQ_PER_CPU */
259 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
260 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
264 * Setup the PC, SP, and GP of a secondary processor and start it
266 * smp_bootstrap is the place to resume from
267 * __KSTK_TOS(idle) is apparently the stack pointer
268 * (unsigned long)idle->thread_info the gp
269 * assumes a 1:1 mapping of TC => VPE
271 void prom_boot_secondary(int cpu, struct task_struct *idle)
273 struct thread_info *gp = task_thread_info(idle);
275 set_c0_mvpcontrol(MVPCONTROL_VPC);
280 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
282 /* enable the tc this vpe/cpu will be running */
283 write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
285 write_tc_c0_tchalt(0);
288 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
291 write_tc_gpr_sp( __KSTK_TOS(idle));
294 write_tc_gpr_gp((unsigned long)gp);
296 flush_icache_range((unsigned long)gp,
297 (unsigned long)(gp + sizeof(struct thread_info)));
299 /* finally out of configuration and into chaos */
300 clear_c0_mvpcontrol(MVPCONTROL_VPC);
305 void prom_init_secondary(void)
307 write_c0_status((read_c0_status() & ~ST0_IM ) |
308 (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7));
311 void prom_smp_finish(void)
313 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
318 void prom_cpus_done(void)
322 void core_send_ipi(int cpu, unsigned int action)
328 local_irq_save (flags);
330 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
333 case SMP_CALL_FUNCTION:
337 case SMP_RESCHEDULE_YOURSELF:
343 /* 1:1 mapping of vpe and tc... */
345 write_vpe_c0_cause(read_vpe_c0_cause() | i);
348 local_irq_restore(flags);