2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2004 Mips Technologies, Inc
17 * Copyright (C) 2008 Kevin D. Kissell
20 #include <linux/clockchips.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/cpumask.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/module.h>
30 #include <asm/processor.h>
31 #include <asm/atomic.h>
32 #include <asm/system.h>
33 #include <asm/hardirq.h>
34 #include <asm/hazards.h>
36 #include <asm/mmu_context.h>
37 #include <asm/mipsregs.h>
38 #include <asm/cacheflush.h>
40 #include <asm/addrspace.h>
42 #include <asm/smtc_proc.h>
45 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
46 * in do_IRQ. These are passed in setup_irq_smtc() and stored
49 unsigned long irq_hwmask[NR_IRQS];
51 #define LOCK_MT_PRA() \
52 local_irq_save(flags); \
55 #define UNLOCK_MT_PRA() \
57 local_irq_restore(flags)
59 #define LOCK_CORE_PRA() \
60 local_irq_save(flags); \
63 #define UNLOCK_CORE_PRA() \
65 local_irq_restore(flags)
68 * Data structures purely associated with SMTC parallelism
73 * Table for tracking ASIDs whose lifetime is prolonged.
76 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
80 * Number of InterProcessor Interrupt (IPI) message buffers to allocate
83 #define IPIBUF_PER_CPU 4
85 struct smtc_ipi_q IPIQ[NR_CPUS];
86 static struct smtc_ipi_q freeIPIq;
89 /* Forward declarations */
91 void ipi_decode(struct smtc_ipi *);
92 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
93 static void setup_cross_vpe_interrupts(unsigned int nvpe);
94 void init_smtc_stats(void);
96 /* Global SMTC Status */
98 unsigned int smtc_status;
100 /* Boot command line configuration overrides */
102 static int vpe0limit;
103 static int ipibuffers;
106 unsigned long smtc_asid_mask = 0xff;
108 static int __init vpe0tcs(char *str)
110 get_option(&str, &vpe0limit);
115 static int __init ipibufs(char *str)
117 get_option(&str, &ipibuffers);
121 static int __init stlb_disable(char *s)
127 static int __init asidmask_set(char *str)
129 get_option(&str, &asidmask);
139 smtc_asid_mask = (unsigned long)asidmask;
142 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask);
147 __setup("vpe0tcs=", vpe0tcs);
148 __setup("ipibufs=", ipibufs);
149 __setup("nostlb", stlb_disable);
150 __setup("asidmask=", asidmask_set);
152 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
154 static int hang_trig;
156 static int __init hangtrig_enable(char *s)
163 __setup("hangtrig", hangtrig_enable);
165 #define DEFAULT_BLOCKED_IPI_LIMIT 32
167 static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT;
169 static int __init tintq(char *str)
171 get_option(&str, &timerq_limit);
175 __setup("tintq=", tintq);
177 static int imstuckcount[2][8];
178 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
179 static int vpemask[2][8] = {
180 {0, 0, 1, 0, 0, 0, 0, 1},
181 {0, 0, 0, 0, 0, 0, 0, 1}
183 int tcnoprog[NR_CPUS];
184 static atomic_t idle_hook_initialized = {0};
185 static int clock_hang_reported[NR_CPUS];
187 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
190 * Configure shared TLB - VPC configuration bit must be set by caller
193 static void smtc_configure_tlb(void)
196 unsigned long mvpconf0;
197 unsigned long config1val;
199 /* Set up ASID preservation table */
200 for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) {
201 for(i = 0; i < MAX_SMTC_ASIDS; i++) {
202 smtc_live_asid[vpes][i] = 0;
205 mvpconf0 = read_c0_mvpconf0();
207 if ((vpes = ((mvpconf0 & MVPCONF0_PVPE)
208 >> MVPCONF0_PVPE_SHIFT) + 1) > 1) {
209 /* If we have multiple VPEs, try to share the TLB */
210 if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) {
212 * If TLB sizing is programmable, shared TLB
213 * size is the total available complement.
214 * Otherwise, we have to take the sum of all
215 * static VPE TLB entries.
217 if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE)
218 >> MVPCONF0_PTLBE_SHIFT)) == 0) {
220 * If there's more than one VPE, there had better
221 * be more than one TC, because we need one to bind
222 * to each VPE in turn to be able to read
223 * its configuration state!
226 /* Stop the TC from doing anything foolish */
227 write_tc_c0_tchalt(TCHALT_H);
229 /* No need to un-Halt - that happens later anyway */
230 for (i=0; i < vpes; i++) {
231 write_tc_c0_tcbind(i);
233 * To be 100% sure we're really getting the right
234 * information, we exit the configuration state
235 * and do an IHB after each rebinding.
238 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
241 * Only count if the MMU Type indicated is TLB
243 if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
244 config1val = read_vpe_c0_config1();
245 tlbsiz += ((config1val >> 25) & 0x3f) + 1;
248 /* Put core back in configuration state */
250 read_c0_mvpcontrol() | MVPCONTROL_VPC );
254 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
258 * Setup kernel data structures to use software total,
259 * rather than read the per-VPE Config1 value. The values
260 * for "CPU 0" gets copied to all the other CPUs as part
261 * of their initialization in smtc_cpu_setup().
264 /* MIPS32 limits TLB indices to 64 */
267 cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
268 smtc_status |= SMTC_TLB_SHARED;
269 local_flush_tlb_all();
271 printk("TLB of %d entry pairs shared by %d VPEs\n",
274 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
281 * Incrementally build the CPU map out of constituent MIPS MT cores,
282 * using the specified available VPEs and TCs. Plaform code needs
283 * to ensure that each MIPS MT core invokes this routine on reset,
286 * This version of the build_cpu_map and prepare_cpus routines assumes
287 * that *all* TCs of a MIPS MT core will be used for Linux, and that
288 * they will be spread across *all* available VPEs (to minimise the
289 * loss of efficiency due to exception service serialization).
290 * An improved version would pick up configuration information and
291 * possibly leave some TCs/VPEs as "slave" processors.
293 * Use c0_MVPConf0 to find out how many TCs are available, setting up
294 * cpu_possible_map and the logical/physical mappings.
297 int __init smtc_build_cpu_map(int start_cpu_slot)
302 * The CPU map isn't actually used for anything at this point,
303 * so it's not clear what else we should do apart from set
304 * everything up so that "logical" = "physical".
306 ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
307 for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) {
308 cpu_set(i, cpu_possible_map);
309 __cpu_number_map[i] = i;
310 __cpu_logical_map[i] = i;
312 #ifdef CONFIG_MIPS_MT_FPAFF
313 /* Initialize map of CPUs with FPUs */
314 cpus_clear(mt_fpu_cpumask);
317 /* One of those TC's is the one booting, and not a secondary... */
318 printk("%i available secondary CPU TC(s)\n", i - 1);
324 * Common setup before any secondaries are started
325 * Make sure all CPU's are in a sensible state before we boot any of the
328 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
329 * as possible across the available VPEs.
332 static void smtc_tc_setup(int vpe, int tc, int cpu)
335 write_tc_c0_tchalt(TCHALT_H);
337 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
338 & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
341 * TCContext gets an offset from the base of the IPIQ array
342 * to be used in low-level code to detect the presence of
343 * an active IPI queue
345 write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
347 write_tc_c0_tcbind(vpe);
348 /* In general, all TCs should have the same cpu_data indications */
349 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
350 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
351 if (cpu_data[0].cputype == CPU_34K ||
352 cpu_data[0].cputype == CPU_1004K)
353 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
354 cpu_data[cpu].vpe_id = vpe;
355 cpu_data[cpu].tc_id = tc;
356 /* Multi-core SMTC hasn't been tested, but be prepared */
357 cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
361 * Tweak to get Count registes in as close a sync as possible.
362 * Value seems good for 34K-class cores.
367 void smtc_prepare_cpus(int cpus)
369 int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
373 struct smtc_ipi *pipi;
375 /* disable interrupts so we can disable MT */
376 local_irq_save(flags);
377 /* disable MT so we can configure */
381 spin_lock_init(&freeIPIq.lock);
384 * We probably don't have as many VPEs as we do SMP "CPUs",
385 * but it's possible - and in any case we'll never use more!
387 for (i=0; i<NR_CPUS; i++) {
388 IPIQ[i].head = IPIQ[i].tail = NULL;
389 spin_lock_init(&IPIQ[i].lock);
393 /* cpu_data index starts at zero */
395 cpu_data[cpu].vpe_id = 0;
396 cpu_data[cpu].tc_id = 0;
397 cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
400 /* Report on boot-time options */
401 mips_mt_set_cpuoptions();
403 printk("Limit of %d VPEs set\n", vpelimit);
405 printk("Limit of %d TCs set\n", tclimit);
407 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
410 printk("ASID mask value override to 0x%x\n", asidmask);
413 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
415 printk("Logic Analyser Trigger on suspected TC hang\n");
416 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
418 /* Put MVPE's into 'configuration state' */
419 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC );
421 val = read_c0_mvpconf0();
422 nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
423 if (vpelimit > 0 && nvpe > vpelimit)
425 ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
428 if (tclimit > 0 && ntc > tclimit)
431 for (i = 0; i < nvpe; i++) {
432 tcpervpe[i] = ntc / nvpe;
434 if((slop - i) > 0) tcpervpe[i]++;
437 /* Handle command line override for VPE0 */
438 if (vpe0limit > ntc) vpe0limit = ntc;
441 if (vpe0limit < tcpervpe[0]) {
442 /* Reducing TC count - distribute to others */
443 slop = tcpervpe[0] - vpe0limit;
444 slopslop = slop % (nvpe - 1);
445 tcpervpe[0] = vpe0limit;
446 for (i = 1; i < nvpe; i++) {
447 tcpervpe[i] += slop / (nvpe - 1);
448 if(slopslop && ((slopslop - (i - 1) > 0)))
451 } else if (vpe0limit > tcpervpe[0]) {
452 /* Increasing TC count - steal from others */
453 slop = vpe0limit - tcpervpe[0];
454 slopslop = slop % (nvpe - 1);
455 tcpervpe[0] = vpe0limit;
456 for (i = 1; i < nvpe; i++) {
457 tcpervpe[i] -= slop / (nvpe - 1);
458 if(slopslop && ((slopslop - (i - 1) > 0)))
464 /* Set up shared TLB */
465 smtc_configure_tlb();
467 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
468 if (tcpervpe[vpe] == 0)
472 printk("VPE %d: TC", vpe);
473 for (i = 0; i < tcpervpe[vpe]; i++) {
475 * TC 0 is bound to VPE 0 at reset,
476 * and is presumably executing this
477 * code. Leave it alone!
480 smtc_tc_setup(vpe, tc, cpu);
488 * Allow this VPE to control others.
490 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
494 * Clear any stale software interrupts from VPE's Cause
496 write_vpe_c0_cause(0);
499 * Clear ERL/EXL of VPEs other than 0
500 * and set restricted interrupt enable/mask.
502 write_vpe_c0_status((read_vpe_c0_status()
503 & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM))
504 | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7
507 * set config to be the same as vpe0,
508 * particularly kseg0 coherency alg
510 write_vpe_c0_config(read_c0_config());
511 /* Clear any pending timer interrupt */
512 write_vpe_c0_compare(0);
513 /* Propagate Config7 */
514 write_vpe_c0_config7(read_c0_config7());
515 write_vpe_c0_count(read_c0_count() + CP0_SKEW);
518 /* enable multi-threading within VPE */
519 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
521 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
525 * Pull any physically present but unused TCs out of circulation.
527 while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) {
528 cpu_clear(tc, cpu_possible_map);
529 cpu_clear(tc, cpu_present_map);
533 /* release config state */
534 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
538 /* Set up coprocessor affinity CPU mask(s) */
540 #ifdef CONFIG_MIPS_MT_FPAFF
541 for (tc = 0; tc < ntc; tc++) {
542 if (cpu_data[tc].options & MIPS_CPU_FPU)
543 cpu_set(tc, mt_fpu_cpumask);
547 /* set up ipi interrupts... */
549 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
551 setup_cross_vpe_interrupts(nvpe);
553 /* Set up queue of free IPI "messages". */
554 nipi = NR_CPUS * IPIBUF_PER_CPU;
558 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
560 panic("kmalloc of IPI message buffers failed\n");
562 printk("IPI buffer pool of %d buffers\n", nipi);
563 for (i = 0; i < nipi; i++) {
564 smtc_ipi_nq(&freeIPIq, pipi);
568 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
571 local_irq_restore(flags);
572 /* Initialize SMTC /proc statistics/diagnostics */
578 * Setup the PC, SP, and GP of a secondary processor and start it
580 * smp_bootstrap is the place to resume from
581 * __KSTK_TOS(idle) is apparently the stack pointer
582 * (unsigned long)idle->thread_info the gp
585 void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
587 extern u32 kernelsp[NR_CPUS];
592 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
595 settc(cpu_data[cpu].tc_id);
598 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
601 kernelsp[cpu] = __KSTK_TOS(idle);
602 write_tc_gpr_sp(__KSTK_TOS(idle));
605 write_tc_gpr_gp((unsigned long)task_thread_info(idle));
607 smtc_status |= SMTC_MTC_ACTIVE;
608 write_tc_c0_tchalt(0);
609 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
615 void smtc_init_secondary(void)
620 void smtc_smp_finish(void)
622 int cpu = smp_processor_id();
625 * Lowest-numbered CPU per VPE starts a clock tick.
626 * Like per_cpu_trap_init() hack, this assumes that
627 * SMTC init code assigns TCs consdecutively and
628 * in ascending order across available VPEs.
630 if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
631 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
633 printk("TC %d going on-line as CPU %d\n",
634 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
637 void smtc_cpus_done(void)
642 * Support for SMTC-optimized driver IRQ registration
646 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
647 * in do_IRQ. These are passed in setup_irq_smtc() and stored
651 int setup_irq_smtc(unsigned int irq, struct irqaction * new,
652 unsigned long hwmask)
654 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
655 unsigned int vpe = current_cpu_data.vpe_id;
657 vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
659 irq_hwmask[irq] = hwmask;
661 return setup_irq(irq, new);
664 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
666 * Support for IRQ affinity to TCs
669 void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
672 * If a "fast path" cache of quickly decodable affinity state
673 * is maintained, this is where it gets done, on a call up
674 * from the platform affinity code.
678 void smtc_forward_irq(unsigned int irq)
683 * OK wise guy, now figure out how to get the IRQ
684 * to be serviced on an authorized "CPU".
686 * Ideally, to handle the situation where an IRQ has multiple
687 * eligible CPUS, we would maintain state per IRQ that would
688 * allow a fair distribution of service requests. Since the
689 * expected use model is any-or-only-one, for simplicity
690 * and efficiency, we just pick the easiest one to find.
693 target = cpumask_first(irq_desc[irq].affinity);
696 * We depend on the platform code to have correctly processed
697 * IRQ affinity change requests to ensure that the IRQ affinity
698 * mask has been purged of bits corresponding to nonexistent and
699 * offline "CPUs", and to TCs bound to VPEs other than the VPE
700 * connected to the physical interrupt input for the interrupt
701 * in question. Otherwise we have a nasty problem with interrupt
702 * mask management. This is best handled in non-performance-critical
703 * platform IRQ affinity setting code, to minimize interrupt-time
707 /* If no one is eligible, service locally */
708 if (target >= NR_CPUS) {
709 do_IRQ_no_affinity(irq);
713 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
716 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
719 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
720 * Within a VPE one TC can interrupt another by different approaches.
721 * The easiest to get right would probably be to make all TCs except
722 * the target IXMT and set a software interrupt, but an IXMT-based
723 * scheme requires that a handler must run before a new IPI could
724 * be sent, which would break the "broadcast" loops in MIPS MT.
725 * A more gonzo approach within a VPE is to halt the TC, extract
726 * its Restart, Status, and a couple of GPRs, and program the Restart
727 * address to emulate an interrupt.
729 * Within a VPE, one can be confident that the target TC isn't in
730 * a critical EXL state when halted, since the write to the Halt
731 * register could not have issued on the writing thread if the
732 * halting thread had EXL set. So k0 and k1 of the target TC
733 * can be used by the injection code. Across VPEs, one can't
734 * be certain that the target TC isn't in a critical exception
735 * state. So we try a two-step process of sending a software
736 * interrupt to the target VPE, which either handles the event
737 * itself (if it was the target) or injects the event within
741 static void smtc_ipi_qdump(void)
745 for (i = 0; i < NR_CPUS ;i++) {
746 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
747 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
753 * The standard atomic.h primitives don't quite do what we want
754 * here: We need an atomic add-and-return-previous-value (which
755 * could be done with atomic_add_return and a decrement) and an
756 * atomic set/zero-and-return-previous-value (which can't really
757 * be done with the atomic.h primitives). And since this is
758 * MIPS MT, we can assume that we have LL/SC.
760 static inline int atomic_postincrement(atomic_t *v)
762 unsigned long result;
766 __asm__ __volatile__(
772 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
779 void smtc_send_ipi(int cpu, int type, unsigned int action)
782 struct smtc_ipi *pipi;
785 unsigned long tcrestart;
786 extern void r4k_wait_irqoff(void), __pastwait(void);
788 if (cpu == smp_processor_id()) {
789 printk("Cannot Send IPI to self!\n");
792 /* Set up a descriptor, to be delivered either promptly or queued */
793 pipi = smtc_ipi_dq(&freeIPIq);
796 mips_mt_regdump(dvpe());
797 panic("IPI Msg. Buffers Depleted\n");
800 pipi->arg = (void *)action;
802 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
803 /* If not on same VPE, enqueue and send cross-VPE interrupt */
804 smtc_ipi_nq(&IPIQ[cpu], pipi);
806 settc(cpu_data[cpu].tc_id);
807 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1);
811 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
812 * since ASID shootdown on the other VPE may
813 * collide with this operation.
816 settc(cpu_data[cpu].tc_id);
817 /* Halt the targeted TC */
818 write_tc_c0_tchalt(TCHALT_H);
822 * Inspect TCStatus - if IXMT is set, we have to queue
823 * a message. Otherwise, we set up the "interrupt"
826 tcstatus = read_tc_c0_tcstatus();
828 if ((tcstatus & TCSTATUS_IXMT) != 0) {
830 * If we're in the the irq-off version of the wait
831 * loop, we need to force exit from the wait and
832 * do a direct post of the IPI.
834 if (cpu_wait == r4k_wait_irqoff) {
835 tcrestart = read_tc_c0_tcrestart();
836 if (tcrestart >= (unsigned long)r4k_wait_irqoff
837 && tcrestart < (unsigned long)__pastwait) {
838 write_tc_c0_tcrestart(__pastwait);
839 tcstatus &= ~TCSTATUS_IXMT;
840 write_tc_c0_tcstatus(tcstatus);
845 * Otherwise we queue the message for the target TC
846 * to pick up when he does a local_irq_restore()
848 write_tc_c0_tchalt(0);
850 smtc_ipi_nq(&IPIQ[cpu], pipi);
853 post_direct_ipi(cpu, pipi);
854 write_tc_c0_tchalt(0);
861 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
863 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
865 struct pt_regs *kstack;
866 unsigned long tcstatus;
867 unsigned long tcrestart;
868 extern u32 kernelsp[NR_CPUS];
869 extern void __smtc_ipi_vector(void);
870 //printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
872 /* Extract Status, EPC from halted TC */
873 tcstatus = read_tc_c0_tcstatus();
874 tcrestart = read_tc_c0_tcrestart();
875 /* If TCRestart indicates a WAIT instruction, advance the PC */
876 if ((tcrestart & 0x80000000)
877 && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) {
881 * Save on TC's future kernel stack
883 * CU bit of Status is indicator that TC was
884 * already running on a kernel stack...
886 if (tcstatus & ST0_CU0) {
887 /* Note that this "- 1" is pointer arithmetic */
888 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
890 kstack = ((struct pt_regs *)kernelsp[cpu]) - 1;
893 kstack->cp0_epc = (long)tcrestart;
895 kstack->cp0_tcstatus = tcstatus;
896 /* Pass token of operation to be performed kernel stack pad area */
897 kstack->pad0[4] = (unsigned long)pipi;
898 /* Pass address of function to be called likewise */
899 kstack->pad0[5] = (unsigned long)&ipi_decode;
900 /* Set interrupt exempt and kernel mode */
901 tcstatus |= TCSTATUS_IXMT;
902 tcstatus &= ~TCSTATUS_TKSU;
903 write_tc_c0_tcstatus(tcstatus);
905 /* Set TC Restart address to be SMTC IPI vector */
906 write_tc_c0_tcrestart(__smtc_ipi_vector);
909 static void ipi_resched_interrupt(void)
911 /* Return from interrupt should be enough to cause scheduler check */
914 static void ipi_call_interrupt(void)
916 /* Invoke generic function invocation code in smp.c */
917 smp_call_function_interrupt();
920 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
922 void ipi_decode(struct smtc_ipi *pipi)
924 unsigned int cpu = smp_processor_id();
925 struct clock_event_device *cd;
926 void *arg_copy = pipi->arg;
927 int type_copy = pipi->type;
928 int irq = MIPS_CPU_IRQ_BASE + 1;
930 smtc_ipi_nq(&freeIPIq, pipi);
933 case SMTC_CLOCK_TICK:
935 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
936 cd = &per_cpu(mips_clockevent_device, cpu);
937 cd->event_handler(cd);
942 switch ((int)arg_copy) {
943 case SMP_RESCHEDULE_YOURSELF:
944 ipi_resched_interrupt();
946 case SMP_CALL_FUNCTION:
947 ipi_call_interrupt();
950 printk("Impossible SMTC IPI Argument 0x%x\n",
955 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
956 case IRQ_AFFINITY_IPI:
958 * Accept a "forwarded" interrupt that was initially
959 * taken by a TC who doesn't have affinity for the IRQ.
961 do_IRQ_no_affinity((int)arg_copy);
963 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
965 printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
971 * Similar to smtc_ipi_replay(), but invoked from context restore,
972 * so it reuses the current exception frame rather than set up a
973 * new one with self_ipi.
976 void deferred_smtc_ipi(void)
978 int cpu = smp_processor_id();
981 * Test is not atomic, but much faster than a dequeue,
982 * and the vast majority of invocations will have a null queue.
983 * If irq_disabled when this was called, then any IPIs queued
984 * after we test last will be taken on the next irq_enable/restore.
985 * If interrupts were enabled, then any IPIs added after the
986 * last test will be taken directly.
989 while (IPIQ[cpu].head != NULL) {
990 struct smtc_ipi_q *q = &IPIQ[cpu];
991 struct smtc_ipi *pipi;
995 * It may be possible we'll come in with interrupts
998 local_irq_save(flags);
1000 spin_lock(&q->lock);
1001 pipi = __smtc_ipi_dq(q);
1002 spin_unlock(&q->lock);
1006 * The use of the __raw_local restore isn't
1007 * as obviously necessary here as in smtc_ipi_replay(),
1008 * but it's more efficient, given that we're already
1009 * running down the IPI queue.
1011 __raw_local_irq_restore(flags);
1016 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
1017 * set via cross-VPE MTTR manipulation of the Cause register. It would be
1018 * in some regards preferable to have external logic for "doorbell" hardware
1022 static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
1024 static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
1026 int my_vpe = cpu_data[smp_processor_id()].vpe_id;
1027 int my_tc = cpu_data[smp_processor_id()].tc_id;
1029 struct smtc_ipi *pipi;
1030 unsigned long tcstatus;
1032 unsigned long flags;
1033 unsigned int mtflags;
1034 unsigned int vpflags;
1037 * So long as cross-VPE interrupts are done via
1038 * MFTR/MTTR read-modify-writes of Cause, we need
1039 * to stop other VPEs whenever the local VPE does
1042 local_irq_save(flags);
1044 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ);
1045 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ);
1046 irq_enable_hazard();
1048 local_irq_restore(flags);
1051 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
1052 * queued for TCs on this VPE other than the current one.
1053 * Return-from-interrupt should cause us to drain the queue
1054 * for the current TC, so we ought not to have to do it explicitly here.
1057 for_each_online_cpu(cpu) {
1058 if (cpu_data[cpu].vpe_id != my_vpe)
1061 pipi = smtc_ipi_dq(&IPIQ[cpu]);
1063 if (cpu_data[cpu].tc_id != my_tc) {
1066 settc(cpu_data[cpu].tc_id);
1067 write_tc_c0_tchalt(TCHALT_H);
1069 tcstatus = read_tc_c0_tcstatus();
1070 if ((tcstatus & TCSTATUS_IXMT) == 0) {
1071 post_direct_ipi(cpu, pipi);
1074 write_tc_c0_tchalt(0);
1077 smtc_ipi_req(&IPIQ[cpu], pipi);
1081 * ipi_decode() should be called
1082 * with interrupts off
1084 local_irq_save(flags);
1086 local_irq_restore(flags);
1094 static void ipi_irq_dispatch(void)
1096 do_IRQ(cpu_ipi_irq);
1099 static struct irqaction irq_ipi = {
1100 .handler = ipi_interrupt,
1101 .flags = IRQF_DISABLED,
1103 .flags = IRQF_PERCPU
1106 static void setup_cross_vpe_interrupts(unsigned int nvpe)
1112 panic("SMTC Kernel requires Vectored Interrupt support");
1114 set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
1116 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1118 set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
1122 * SMTC-specific hacks invoked from elsewhere in the kernel.
1126 * smtc_ipi_replay is called from raw_local_irq_restore
1129 void smtc_ipi_replay(void)
1131 unsigned int cpu = smp_processor_id();
1134 * To the extent that we've ever turned interrupts off,
1135 * we may have accumulated deferred IPIs. This is subtle.
1136 * we should be OK: If we pick up something and dispatch
1137 * it here, that's great. If we see nothing, but concurrent
1138 * with this operation, another TC sends us an IPI, IXMT
1139 * is clear, and we'll handle it as a real pseudo-interrupt
1140 * and not a pseudo-pseudo interrupt. The important thing
1141 * is to do the last check for queued message *after* the
1142 * re-enabling of interrupts.
1144 while (IPIQ[cpu].head != NULL) {
1145 struct smtc_ipi_q *q = &IPIQ[cpu];
1146 struct smtc_ipi *pipi;
1147 unsigned long flags;
1150 * It's just possible we'll come in with interrupts
1153 local_irq_save(flags);
1155 spin_lock(&q->lock);
1156 pipi = __smtc_ipi_dq(q);
1157 spin_unlock(&q->lock);
1159 ** But use a raw restore here to avoid recursion.
1161 __raw_local_irq_restore(flags);
1165 smtc_cpu_stats[cpu].selfipis++;
1170 EXPORT_SYMBOL(smtc_ipi_replay);
1172 void smtc_idle_loop_hook(void)
1174 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1183 * printk within DMT-protected regions can deadlock,
1184 * so buffer diagnostic messages for later output.
1187 char id_ho_db_msg[768]; /* worst-case use should be less than 700 */
1189 if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */
1190 if (atomic_add_return(1, &idle_hook_initialized) == 1) {
1192 /* Tedious stuff to just do once */
1193 mvpconf0 = read_c0_mvpconf0();
1194 hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
1195 if (hook_ntcs > NR_CPUS)
1196 hook_ntcs = NR_CPUS;
1197 for (tc = 0; tc < hook_ntcs; tc++) {
1199 clock_hang_reported[tc] = 0;
1201 for (vpe = 0; vpe < 2; vpe++)
1202 for (im = 0; im < 8; im++)
1203 imstuckcount[vpe][im] = 0;
1204 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs);
1205 atomic_set(&idle_hook_initialized, 1000);
1207 /* Someone else is initializing in parallel - let 'em finish */
1208 while (atomic_read(&idle_hook_initialized) < 1000)
1213 /* Have we stupidly left IXMT set somewhere? */
1214 if (read_c0_tcstatus() & 0x400) {
1215 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1217 printk("Dangling IXMT in cpu_idle()\n");
1220 /* Have we stupidly left an IM bit turned off? */
1221 #define IM_LIMIT 2000
1222 local_irq_save(flags);
1224 pdb_msg = &id_ho_db_msg[0];
1225 im = read_c0_status();
1226 vpe = current_cpu_data.vpe_id;
1227 for (bit = 0; bit < 8; bit++) {
1229 * In current prototype, I/O interrupts
1230 * are masked for VPE > 0
1232 if (vpemask[vpe][bit]) {
1233 if (!(im & (0x100 << bit)))
1234 imstuckcount[vpe][bit]++;
1236 imstuckcount[vpe][bit] = 0;
1237 if (imstuckcount[vpe][bit] > IM_LIMIT) {
1238 set_c0_status(0x100 << bit);
1240 imstuckcount[vpe][bit] = 0;
1241 pdb_msg += sprintf(pdb_msg,
1242 "Dangling IM %d fixed for VPE %d\n", bit,
1249 local_irq_restore(flags);
1250 if (pdb_msg != &id_ho_db_msg[0])
1251 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
1252 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1257 void smtc_soft_dump(void)
1261 printk("Counter Interrupts taken per CPU (TC)\n");
1262 for (i=0; i < NR_CPUS; i++) {
1263 printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints);
1265 printk("Self-IPI invocations:\n");
1266 for (i=0; i < NR_CPUS; i++) {
1267 printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
1270 printk("%d Recoveries of \"stolen\" FPU\n",
1271 atomic_read(&smtc_fpu_recoveries));
1276 * TLB management routines special to SMTC
1279 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1281 unsigned long flags, mtflags, tcstat, prevhalt, asid;
1285 * It would be nice to be able to use a spinlock here,
1286 * but this is invoked from within TLB flush routines
1287 * that protect themselves with DVPE, so if a lock is
1288 * held by another TC, it'll never be freed.
1290 * DVPE/DMT must not be done with interrupts enabled,
1291 * so even so most callers will already have disabled
1292 * them, let's be really careful...
1295 local_irq_save(flags);
1296 if (smtc_status & SMTC_TLB_SHARED) {
1301 tlb = cpu_data[cpu].vpe_id;
1303 asid = asid_cache(cpu);
1306 if (!((asid += ASID_INC) & ASID_MASK) ) {
1307 if (cpu_has_vtag_icache)
1309 /* Traverse all online CPUs (hack requires contigous range) */
1310 for_each_online_cpu(i) {
1312 * We don't need to worry about our own CPU, nor those of
1313 * CPUs who don't share our TLB.
1315 if ((i != smp_processor_id()) &&
1316 ((smtc_status & SMTC_TLB_SHARED) ||
1317 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) {
1318 settc(cpu_data[i].tc_id);
1319 prevhalt = read_tc_c0_tchalt() & TCHALT_H;
1321 write_tc_c0_tchalt(TCHALT_H);
1324 tcstat = read_tc_c0_tcstatus();
1325 smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
1327 write_tc_c0_tchalt(0);
1330 if (!asid) /* fix version if needed */
1331 asid = ASID_FIRST_VERSION;
1332 local_flush_tlb_all(); /* start new asid cycle */
1334 } while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
1337 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1339 for_each_online_cpu(i) {
1340 if ((smtc_status & SMTC_TLB_SHARED) ||
1341 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1342 cpu_context(i, mm) = asid_cache(i) = asid;
1345 if (smtc_status & SMTC_TLB_SHARED)
1349 local_irq_restore(flags);
1353 * Invoked from macros defined in mmu_context.h
1354 * which must already have disabled interrupts
1355 * and done a DVPE or DMT as appropriate.
1358 void smtc_flush_tlb_asid(unsigned long asid)
1363 entry = read_c0_wired();
1365 /* Traverse all non-wired entries */
1366 while (entry < current_cpu_data.tlbsize) {
1367 write_c0_index(entry);
1371 ehi = read_c0_entryhi();
1372 if ((ehi & ASID_MASK) == asid) {
1374 * Invalidate only entries with specified ASID,
1375 * makiing sure all entries differ.
1377 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
1378 write_c0_entrylo0(0);
1379 write_c0_entrylo1(0);
1381 tlb_write_indexed();
1385 write_c0_index(PARKED_INDEX);
1390 * Support for single-threading cache flush operations.
1393 static int halt_state_save[NR_CPUS];
1396 * To really, really be sure that nothing is being done
1397 * by other TCs, halt them all. This code assumes that
1398 * a DVPE has already been done, so while their Halted
1399 * state is theoretically architecturally unstable, in
1400 * practice, it's not going to change while we're looking
1404 void smtc_cflush_lockdown(void)
1408 for_each_online_cpu(cpu) {
1409 if (cpu != smp_processor_id()) {
1410 settc(cpu_data[cpu].tc_id);
1411 halt_state_save[cpu] = read_tc_c0_tchalt();
1412 write_tc_c0_tchalt(TCHALT_H);
1418 /* It would be cheating to change the cpu_online states during a flush! */
1420 void smtc_cflush_release(void)
1425 * Start with a hazard barrier to ensure
1426 * that all CACHE ops have played through.
1430 for_each_online_cpu(cpu) {
1431 if (cpu != smp_processor_id()) {
1432 settc(cpu_data[cpu].tc_id);
1433 write_tc_c0_tchalt(halt_state_save[cpu]);