2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (c) 2003, 2004 Maciej W. Rozycki
6 * Common time service routines for MIPS machines. See
7 * Documentation/mips/time.README.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 #include <linux/clockchips.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/param.h>
20 #include <linux/profile.h>
21 #include <linux/time.h>
22 #include <linux/timex.h>
23 #include <linux/smp.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/spinlock.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/kallsyms.h>
30 #include <asm/bootinfo.h>
31 #include <asm/cache.h>
32 #include <asm/compiler.h>
34 #include <asm/cpu-features.h>
35 #include <asm/div64.h>
36 #include <asm/sections.h>
37 #include <asm/smtc_ipi.h>
43 * The integer part of the number of usecs per jiffy is taken from tick,
44 * but the fractional part is not recorded, so we calculate it using the
45 * initial value of HZ. This aids systems where tick isn't really an
46 * integer (e.g. for HZ = 128).
48 #define USECS_PER_JIFFY TICK_SIZE
49 #define USECS_PER_JIFFY_FRAC ((unsigned long)(u32)((1000000ULL << 32) / HZ))
51 #define TICK_SIZE (tick_nsec / 1000)
56 DEFINE_SPINLOCK(rtc_lock);
57 EXPORT_SYMBOL(rtc_lock);
59 int __weak rtc_mips_set_time(unsigned long sec)
63 EXPORT_SYMBOL(rtc_mips_set_time);
65 int __weak rtc_mips_set_mmss(unsigned long nowtime)
67 return rtc_mips_set_time(nowtime);
70 int update_persistent_clock(struct timespec now)
72 return rtc_mips_set_mmss(now.tv_sec);
76 * Null high precision timer functions for systems lacking one.
78 static cycle_t null_hpt_read(void)
84 * Timer ack for an R4k-compatible timer of a known frequency.
86 static void c0_timer_ack(void)
88 write_c0_compare(read_c0_compare());
92 * High precision timer functions for a R4k-compatible timer.
94 static cycle_t c0_hpt_read(void)
96 return read_c0_count();
99 int (*mips_timer_state)(void);
102 * local_timer_interrupt() does profiling and process accounting
103 * on a per-CPU basis.
105 * In UP mode, it is invoked from the (global) timer_interrupt.
107 * In SMP mode, it might invoked by per-CPU timer interrupt, or
108 * a broadcasted inter-processor interrupt which itself is triggered
109 * by the global timer interrupt.
111 void local_timer_interrupt(int irq, void *dev_id)
113 profile_tick(CPU_PROFILING);
114 update_process_times(user_mode(get_irq_regs()));
117 int null_perf_irq(void)
122 EXPORT_SYMBOL(null_perf_irq);
124 int (*perf_irq)(void) = null_perf_irq;
126 EXPORT_SYMBOL(perf_irq);
134 * Performance counter IRQ or -1 if shared with timer
136 int cp0_perfcount_irq;
137 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
140 * Possibly handle a performance counter interrupt.
141 * Return true if the timer interrupt should not be checked
143 static inline int handle_perf_irq(int r2)
146 * The performance counter overflow interrupt may be shared with the
147 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
148 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
149 * and we can't reliably determine if a counter interrupt has also
150 * happened (!r2) then don't check for a timer interrupt.
152 return (cp0_perfcount_irq < 0) &&
153 perf_irq() == IRQ_HANDLED &&
158 * time_init() - it does the following things.
160 * 1) plat_time_init() -
161 * a) (optional) set up RTC routines,
162 * b) (optional) calibrate and set the mips_hpt_frequency
163 * (only needed if you intended to use cpu counter as timer interrupt
165 * 2) calculate a couple of cached variables for later usage
166 * 3) plat_timer_setup() -
167 * a) (optional) over-write any choices made above by time_init().
168 * b) machine specific code should setup the timer irqaction.
169 * c) enable the timer interrupt
172 unsigned int mips_hpt_frequency;
174 static unsigned int __init calibrate_hpt(void)
176 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
178 const int loops = HZ / 10;
183 * We want to calibrate for 0.1s, but to avoid a 64-bit
184 * division we round the number of loops up to the nearest
187 while (loops > 1 << log_2_loops)
189 i = 1 << log_2_loops;
192 * Wait for a rising edge of the timer interrupt.
194 while (mips_timer_state());
195 while (!mips_timer_state());
198 * Now see how many high precision timer ticks happen
199 * during the calculated number of periods between timer
202 hpt_start = clocksource_mips.read();
204 while (mips_timer_state());
205 while (!mips_timer_state());
207 hpt_end = clocksource_mips.read();
209 hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
211 frequency = hpt_count * hz;
213 return frequency >> log_2_loops;
216 struct clocksource clocksource_mips = {
218 .mask = CLOCKSOURCE_MASK(32),
219 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
222 static int mips_next_event(unsigned long delta,
223 struct clock_event_device *evt)
228 #ifdef CONFIG_MIPS_MT_SMTC
230 unsigned long flags, vpflags;
231 local_irq_save(flags);
234 cnt = read_c0_count();
236 write_c0_compare(cnt);
237 res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
238 #ifdef CONFIG_MIPS_MT_SMTC
240 local_irq_restore(flags);
246 static void mips_set_mode(enum clock_event_mode mode,
247 struct clock_event_device *evt)
249 /* Nothing to do ... */
252 static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
253 static int cp0_timer_irq_installed;
255 static irqreturn_t timer_interrupt(int irq, void *dev_id)
257 const int r2 = cpu_has_mips_r2;
258 struct clock_event_device *cd;
259 int cpu = smp_processor_id();
263 * Before R2 of the architecture there was no way to see if a
264 * performance counter interrupt was pending, so we have to run
265 * the performance counter interrupt handler anyway.
267 if (handle_perf_irq(r2))
271 * The same applies to performance counter interrupts. But with the
272 * above we now know that the reason we got here must be a timer
273 * interrupt. Being the paranoiacs we are we check anyway.
275 if (!r2 || (read_c0_cause() & (1 << 30))) {
277 #ifdef CONFIG_MIPS_MT_SMTC
278 if (cpu_data[cpu].vpe_id)
282 cd = &per_cpu(mips_clockevent_device, cpu);
283 cd->event_handler(cd);
290 static struct irqaction timer_irqaction = {
291 .handler = timer_interrupt,
292 #ifdef CONFIG_MIPS_MT_SMTC
293 .flags = IRQF_DISABLED,
295 .flags = IRQF_DISABLED | IRQF_PERCPU,
300 static void __init init_mips_clocksource(void)
305 if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
308 /* Calclate a somewhat reasonable rating value */
309 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
310 /* Find a shift value */
311 for (shift = 32; shift > 0; shift--) {
312 temp = (u64) NSEC_PER_SEC << shift;
313 do_div(temp, mips_hpt_frequency);
314 if ((temp >> 32) == 0)
317 clocksource_mips.shift = shift;
318 clocksource_mips.mult = (u32)temp;
320 clocksource_register(&clocksource_mips);
323 void __init __weak plat_time_init(void)
327 void __init __weak plat_timer_setup(struct irqaction *irq)
331 #ifdef CONFIG_MIPS_MT_SMTC
332 DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
334 static void smtc_set_mode(enum clock_event_mode mode,
335 struct clock_event_device *evt)
339 int dummycnt[NR_CPUS];
341 static void mips_broadcast(cpumask_t mask)
345 for_each_cpu_mask(cpu, mask)
346 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
349 static void setup_smtc_dummy_clockevent_device(void)
351 //uint64_t mips_freq = mips_hpt_^frequency;
352 unsigned int cpu = smp_processor_id();
353 struct clock_event_device *cd;
355 cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
358 cd->features = CLOCK_EVT_FEAT_DUMMY;
360 /* Calculate the min / max delta */
361 cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
363 cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
364 cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
369 // cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
371 cd->cpumask = cpumask_of_cpu(cpu);
373 cd->set_mode = smtc_set_mode;
375 cd->broadcast = mips_broadcast;
377 clockevents_register_device(cd);
381 static void mips_event_handler(struct clock_event_device *dev)
386 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
388 static int c0_compare_int_pending(void)
390 return (read_c0_cause() >> cp0_compare_irq) & 0x100;
393 static int c0_compare_int_usable(void)
395 const unsigned int delta = 0x300000;
399 * IP7 already pending? Try to clear it by acking the timer.
401 if (c0_compare_int_pending()) {
402 write_c0_compare(read_c0_compare());
403 irq_disable_hazard();
404 if (c0_compare_int_pending())
408 cnt = read_c0_count();
410 write_c0_compare(cnt);
412 while ((long)(read_c0_count() - cnt) <= 0)
413 ; /* Wait for expiry */
415 if (!c0_compare_int_pending())
418 write_c0_compare(read_c0_compare());
419 irq_disable_hazard();
420 if (c0_compare_int_pending())
424 * Feels like a real count / compare timer.
429 void __cpuinit mips_clockevent_init(void)
431 uint64_t mips_freq = mips_hpt_frequency;
432 unsigned int cpu = smp_processor_id();
433 struct clock_event_device *cd;
434 unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
436 if (!cpu_has_counter)
439 #ifdef CONFIG_MIPS_MT_SMTC
440 setup_smtc_dummy_clockevent_device();
443 * On SMTC we only register VPE0's compare interrupt as clockevent
450 if (!c0_compare_int_usable())
453 cd = &per_cpu(mips_clockevent_device, cpu);
456 cd->features = CLOCK_EVT_FEAT_ONESHOT;
458 /* Calculate the min / max delta */
459 cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
461 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
462 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
466 #ifdef CONFIG_MIPS_MT_SMTC
467 cd->cpumask = CPU_MASK_ALL;
469 cd->cpumask = cpumask_of_cpu(cpu);
471 cd->set_next_event = mips_next_event;
472 cd->set_mode = mips_set_mode;
473 cd->event_handler = mips_event_handler;
475 clockevents_register_device(cd);
477 if (!cp0_timer_irq_installed) {
478 #ifdef CONFIG_MIPS_MT_SMTC
479 #define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
480 setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT);
482 setup_irq(irq, &timer_irqaction);
483 #endif /* CONFIG_MIPS_MT_SMTC */
484 cp0_timer_irq_installed = 1;
488 void __init time_init(void)
492 /* Choose appropriate high precision timer routines. */
493 if (!cpu_has_counter && !clocksource_mips.read)
494 /* No high precision timer -- sorry. */
495 clocksource_mips.read = null_hpt_read;
496 else if (!mips_hpt_frequency && !mips_timer_state) {
497 /* A high precision timer of unknown frequency. */
498 if (!clocksource_mips.read)
499 /* No external high precision timer -- use R4k. */
500 clocksource_mips.read = c0_hpt_read;
502 /* We know counter frequency. Or we can get it. */
503 if (!clocksource_mips.read) {
504 /* No external high precision timer -- use R4k. */
505 clocksource_mips.read = c0_hpt_read;
507 if (!mips_hpt_frequency)
508 mips_hpt_frequency = calibrate_hpt();
510 /* Report the high precision timer rate for a reference. */
511 printk("Using %u.%03u MHz high precision timer.\n",
512 ((mips_hpt_frequency + 500) / 1000) / 1000,
513 ((mips_hpt_frequency + 500) / 1000) % 1000);
515 #ifdef CONFIG_IRQ_CPU
516 setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction);
521 * Call board specific timer interrupt setup.
523 * this pointer must be setup in machine setup routine.
525 * Even if a machine chooses to use a low-level timer interrupt,
526 * it still needs to setup the timer_irqaction.
527 * In that case, it might be better to set timer_irqaction.handler
528 * to be NULL function so that we are sure the high-level code
529 * is not invoked accidentally.
531 plat_timer_setup(&timer_irqaction);
533 init_mips_clocksource();
534 mips_clockevent_init();