2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/debug.h>
28 #include <linux/smp.h>
29 #include <linux/spinlock.h>
30 #include <linux/kallsyms.h>
31 #include <linux/bootmem.h>
32 #include <linux/interrupt.h>
33 #include <linux/ptrace.h>
34 #include <linux/kgdb.h>
35 #include <linux/kdebug.h>
36 #include <linux/kprobes.h>
37 #include <linux/notifier.h>
38 #include <linux/kdb.h>
39 #include <linux/irq.h>
40 #include <linux/perf_event.h>
42 #include <asm/addrspace.h>
43 #include <asm/bootinfo.h>
44 #include <asm/branch.h>
45 #include <asm/break.h>
48 #include <asm/cpu-type.h>
51 #include <asm/fpu_emulator.h>
53 #include <asm/mips-cm.h>
54 #include <asm/mips-r2-to-r6-emul.h>
55 #include <asm/mips-cm.h>
56 #include <asm/mipsregs.h>
57 #include <asm/mipsmtregs.h>
58 #include <asm/module.h>
60 #include <asm/pgtable.h>
61 #include <asm/ptrace.h>
62 #include <asm/sections.h>
63 #include <asm/siginfo.h>
64 #include <asm/tlbdebug.h>
65 #include <asm/traps.h>
66 #include <linux/uaccess.h>
67 #include <asm/watch.h>
68 #include <asm/mmu_context.h>
69 #include <asm/types.h>
70 #include <asm/stacktrace.h>
73 extern void check_wait(void);
74 extern asmlinkage void rollback_handle_int(void);
75 extern asmlinkage void handle_int(void);
76 extern u32 handle_tlbl[];
77 extern u32 handle_tlbs[];
78 extern u32 handle_tlbm[];
79 extern asmlinkage void handle_adel(void);
80 extern asmlinkage void handle_ades(void);
81 extern asmlinkage void handle_ibe(void);
82 extern asmlinkage void handle_dbe(void);
83 extern asmlinkage void handle_sys(void);
84 extern asmlinkage void handle_bp(void);
85 extern asmlinkage void handle_ri(void);
86 extern asmlinkage void handle_ri_rdhwr_tlbp(void);
87 extern asmlinkage void handle_ri_rdhwr(void);
88 extern asmlinkage void handle_cpu(void);
89 extern asmlinkage void handle_ov(void);
90 extern asmlinkage void handle_tr(void);
91 extern asmlinkage void handle_msa_fpe(void);
92 extern asmlinkage void handle_fpe(void);
93 extern asmlinkage void handle_ftlb(void);
94 extern asmlinkage void handle_msa(void);
95 extern asmlinkage void handle_mdmx(void);
96 extern asmlinkage void handle_watch(void);
97 extern asmlinkage void handle_mt(void);
98 extern asmlinkage void handle_dsp(void);
99 extern asmlinkage void handle_mcheck(void);
100 extern asmlinkage void handle_reserved(void);
101 extern void tlb_do_page_fault_0(void);
103 void (*board_be_init)(void);
104 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
105 void (*board_nmi_handler_setup)(void);
106 void (*board_ejtag_handler_setup)(void);
107 void (*board_bind_eic_interrupt)(int irq, int regset);
108 void (*board_ebase_setup)(void);
109 void(*board_cache_error_setup)(void);
111 static void show_raw_backtrace(unsigned long reg29)
113 unsigned long *sp = (unsigned long *)(reg29 & ~3);
116 printk("Call Trace:");
117 #ifdef CONFIG_KALLSYMS
120 while (!kstack_end(sp)) {
121 unsigned long __user *p =
122 (unsigned long __user *)(unsigned long)sp++;
123 if (__get_user(addr, p)) {
124 printk(" (Bad stack address)");
127 if (__kernel_text_address(addr))
133 #ifdef CONFIG_KALLSYMS
135 static int __init set_raw_show_trace(char *str)
140 __setup("raw_show_trace", set_raw_show_trace);
143 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
145 unsigned long sp = regs->regs[29];
146 unsigned long ra = regs->regs[31];
147 unsigned long pc = regs->cp0_epc;
152 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
153 show_raw_backtrace(sp);
156 printk("Call Trace:\n");
159 pc = unwind_stack(task, &sp, pc, &ra);
165 * This routine abuses get_user()/put_user() to reference pointers
166 * with at least a bit of error checking ...
168 static void show_stacktrace(struct task_struct *task,
169 const struct pt_regs *regs)
171 const int field = 2 * sizeof(unsigned long);
174 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
178 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
179 if (i && ((i % (64 / field)) == 0)) {
188 if (__get_user(stackdata, sp++)) {
189 pr_cont(" (Bad stack address)");
193 pr_cont(" %0*lx", field, stackdata);
197 show_backtrace(task, regs);
200 void show_stack(struct task_struct *task, unsigned long *sp)
203 mm_segment_t old_fs = get_fs();
205 regs.regs[29] = (unsigned long)sp;
209 if (task && task != current) {
210 regs.regs[29] = task->thread.reg29;
212 regs.cp0_epc = task->thread.reg31;
213 #ifdef CONFIG_KGDB_KDB
214 } else if (atomic_read(&kgdb_active) != -1 &&
216 memcpy(®s, kdb_current_regs, sizeof(regs));
217 #endif /* CONFIG_KGDB_KDB */
219 prepare_frametrace(®s);
223 * show_stack() deals exclusively with kernel mode, so be sure to access
224 * the stack in the kernel (not user) address space.
227 show_stacktrace(task, ®s);
231 static void show_code(unsigned int __user *pc)
234 unsigned short __user *pc16 = NULL;
238 if ((unsigned long)pc & 1)
239 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
240 for(i = -3 ; i < 6 ; i++) {
242 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
243 pr_cont(" (Bad address in epc)\n");
246 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
251 static void __show_regs(const struct pt_regs *regs)
253 const int field = 2 * sizeof(unsigned long);
254 unsigned int cause = regs->cp0_cause;
255 unsigned int exccode;
258 show_regs_print_info(KERN_DEFAULT);
261 * Saved main processor registers
263 for (i = 0; i < 32; ) {
267 pr_cont(" %0*lx", field, 0UL);
268 else if (i == 26 || i == 27)
269 pr_cont(" %*s", field, "");
271 pr_cont(" %0*lx", field, regs->regs[i]);
278 #ifdef CONFIG_CPU_HAS_SMARTMIPS
279 printk("Acx : %0*lx\n", field, regs->acx);
281 printk("Hi : %0*lx\n", field, regs->hi);
282 printk("Lo : %0*lx\n", field, regs->lo);
285 * Saved cp0 registers
287 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
288 (void *) regs->cp0_epc);
289 printk("ra : %0*lx %pS\n", field, regs->regs[31],
290 (void *) regs->regs[31]);
292 printk("Status: %08x ", (uint32_t) regs->cp0_status);
295 if (regs->cp0_status & ST0_KUO)
297 if (regs->cp0_status & ST0_IEO)
299 if (regs->cp0_status & ST0_KUP)
301 if (regs->cp0_status & ST0_IEP)
303 if (regs->cp0_status & ST0_KUC)
305 if (regs->cp0_status & ST0_IEC)
307 } else if (cpu_has_4kex) {
308 if (regs->cp0_status & ST0_KX)
310 if (regs->cp0_status & ST0_SX)
312 if (regs->cp0_status & ST0_UX)
314 switch (regs->cp0_status & ST0_KSU) {
319 pr_cont("SUPERVISOR ");
325 pr_cont("BAD_MODE ");
328 if (regs->cp0_status & ST0_ERL)
330 if (regs->cp0_status & ST0_EXL)
332 if (regs->cp0_status & ST0_IE)
337 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
338 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
340 if (1 <= exccode && exccode <= 5)
341 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
343 printk("PrId : %08x (%s)\n", read_c0_prid(),
348 * FIXME: really the generic show_regs should take a const pointer argument.
350 void show_regs(struct pt_regs *regs)
352 __show_regs((struct pt_regs *)regs);
355 void show_registers(struct pt_regs *regs)
357 const int field = 2 * sizeof(unsigned long);
358 mm_segment_t old_fs = get_fs();
362 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
363 current->comm, current->pid, current_thread_info(), current,
364 field, current_thread_info()->tp_value);
365 if (cpu_has_userlocal) {
368 tls = read_c0_userlocal();
369 if (tls != current_thread_info()->tp_value)
370 printk("*HwTLS: %0*lx\n", field, tls);
373 if (!user_mode(regs))
374 /* Necessary for getting the correct stack content */
376 show_stacktrace(current, regs);
377 show_code((unsigned int __user *) regs->cp0_epc);
382 static DEFINE_RAW_SPINLOCK(die_lock);
384 void __noreturn die(const char *str, struct pt_regs *regs)
386 static int die_counter;
391 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
392 SIGSEGV) == NOTIFY_STOP)
396 raw_spin_lock_irq(&die_lock);
399 printk("%s[#%d]:\n", str, ++die_counter);
400 show_registers(regs);
401 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
402 raw_spin_unlock_irq(&die_lock);
407 panic("Fatal exception in interrupt");
410 panic("Fatal exception");
412 if (regs && kexec_should_crash(current))
418 extern struct exception_table_entry __start___dbe_table[];
419 extern struct exception_table_entry __stop___dbe_table[];
422 " .section __dbe_table, \"a\"\n"
425 /* Given an address, look for it in the exception tables. */
426 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
428 const struct exception_table_entry *e;
430 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
432 e = search_module_dbetables(addr);
436 asmlinkage void do_be(struct pt_regs *regs)
438 const int field = 2 * sizeof(unsigned long);
439 const struct exception_table_entry *fixup = NULL;
440 int data = regs->cp0_cause & 4;
441 int action = MIPS_BE_FATAL;
442 enum ctx_state prev_state;
444 prev_state = exception_enter();
445 /* XXX For now. Fixme, this searches the wrong table ... */
446 if (data && !user_mode(regs))
447 fixup = search_dbe_tables(exception_epc(regs));
450 action = MIPS_BE_FIXUP;
452 if (board_be_handler)
453 action = board_be_handler(regs, fixup != NULL);
455 mips_cm_error_report();
458 case MIPS_BE_DISCARD:
462 regs->cp0_epc = fixup->nextinsn;
471 * Assume it would be too dangerous to continue ...
473 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
474 data ? "Data" : "Instruction",
475 field, regs->cp0_epc, field, regs->regs[31]);
476 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
477 SIGBUS) == NOTIFY_STOP)
480 die_if_kernel("Oops", regs);
481 force_sig(SIGBUS, current);
484 exception_exit(prev_state);
488 * ll/sc, rdhwr, sync emulation
491 #define OPCODE 0xfc000000
492 #define BASE 0x03e00000
493 #define RT 0x001f0000
494 #define OFFSET 0x0000ffff
495 #define LL 0xc0000000
496 #define SC 0xe0000000
497 #define SPEC0 0x00000000
498 #define SPEC3 0x7c000000
499 #define RD 0x0000f800
500 #define FUNC 0x0000003f
501 #define SYNC 0x0000000f
502 #define RDHWR 0x0000003b
504 /* microMIPS definitions */
505 #define MM_POOL32A_FUNC 0xfc00ffff
506 #define MM_RDHWR 0x00006b3c
507 #define MM_RS 0x001f0000
508 #define MM_RT 0x03e00000
511 * The ll_bit is cleared by r*_switch.S
515 struct task_struct *ll_task;
517 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
519 unsigned long value, __user *vaddr;
523 * analyse the ll instruction that just caused a ri exception
524 * and put the referenced address to addr.
527 /* sign extend offset */
528 offset = opcode & OFFSET;
532 vaddr = (unsigned long __user *)
533 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
535 if ((unsigned long)vaddr & 3)
537 if (get_user(value, vaddr))
542 if (ll_task == NULL || ll_task == current) {
551 regs->regs[(opcode & RT) >> 16] = value;
556 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
558 unsigned long __user *vaddr;
563 * analyse the sc instruction that just caused a ri exception
564 * and put the referenced address to addr.
567 /* sign extend offset */
568 offset = opcode & OFFSET;
572 vaddr = (unsigned long __user *)
573 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
574 reg = (opcode & RT) >> 16;
576 if ((unsigned long)vaddr & 3)
581 if (ll_bit == 0 || ll_task != current) {
589 if (put_user(regs->regs[reg], vaddr))
598 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
599 * opcodes are supposed to result in coprocessor unusable exceptions if
600 * executed on ll/sc-less processors. That's the theory. In practice a
601 * few processors such as NEC's VR4100 throw reserved instruction exceptions
602 * instead, so we're doing the emulation thing in both exception handlers.
604 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
606 if ((opcode & OPCODE) == LL) {
607 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
609 return simulate_ll(regs, opcode);
611 if ((opcode & OPCODE) == SC) {
612 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
614 return simulate_sc(regs, opcode);
617 return -1; /* Must be something else ... */
621 * Simulate trapping 'rdhwr' instructions to provide user accessible
622 * registers not implemented in hardware.
624 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
626 struct thread_info *ti = task_thread_info(current);
628 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
631 case MIPS_HWR_CPUNUM: /* CPU number */
632 regs->regs[rt] = smp_processor_id();
634 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
635 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
636 current_cpu_data.icache.linesz);
638 case MIPS_HWR_CC: /* Read count register */
639 regs->regs[rt] = read_c0_count();
641 case MIPS_HWR_CCRES: /* Count register resolution */
642 switch (current_cpu_type()) {
651 case MIPS_HWR_ULR: /* Read UserLocal register */
652 regs->regs[rt] = ti->tp_value;
659 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
661 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
662 int rd = (opcode & RD) >> 11;
663 int rt = (opcode & RT) >> 16;
665 simulate_rdhwr(regs, rd, rt);
673 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
675 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
676 int rd = (opcode & MM_RS) >> 16;
677 int rt = (opcode & MM_RT) >> 21;
678 simulate_rdhwr(regs, rd, rt);
686 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
688 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
689 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
694 return -1; /* Must be something else ... */
697 asmlinkage void do_ov(struct pt_regs *regs)
699 enum ctx_state prev_state;
702 .si_code = FPE_INTOVF,
703 .si_addr = (void __user *)regs->cp0_epc,
706 prev_state = exception_enter();
707 die_if_kernel("Integer overflow", regs);
709 force_sig_info(SIGFPE, &info, current);
710 exception_exit(prev_state);
714 * Send SIGFPE according to FCSR Cause bits, which must have already
715 * been masked against Enable bits. This is impotant as Inexact can
716 * happen together with Overflow or Underflow, and `ptrace' can set
719 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
720 struct task_struct *tsk)
722 struct siginfo si = { .si_addr = fault_addr, .si_signo = SIGFPE };
724 if (fcr31 & FPU_CSR_INV_X)
725 si.si_code = FPE_FLTINV;
726 else if (fcr31 & FPU_CSR_DIV_X)
727 si.si_code = FPE_FLTDIV;
728 else if (fcr31 & FPU_CSR_OVF_X)
729 si.si_code = FPE_FLTOVF;
730 else if (fcr31 & FPU_CSR_UDF_X)
731 si.si_code = FPE_FLTUND;
732 else if (fcr31 & FPU_CSR_INE_X)
733 si.si_code = FPE_FLTRES;
735 si.si_code = __SI_FAULT;
736 force_sig_info(SIGFPE, &si, tsk);
739 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
741 struct siginfo si = { 0 };
742 struct vm_area_struct *vma;
749 force_fcr31_sig(fcr31, fault_addr, current);
753 si.si_addr = fault_addr;
755 si.si_code = BUS_ADRERR;
756 force_sig_info(sig, &si, current);
760 si.si_addr = fault_addr;
762 down_read(¤t->mm->mmap_sem);
763 vma = find_vma(current->mm, (unsigned long)fault_addr);
764 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
765 si.si_code = SEGV_ACCERR;
767 si.si_code = SEGV_MAPERR;
768 up_read(¤t->mm->mmap_sem);
769 force_sig_info(sig, &si, current);
773 force_sig(sig, current);
778 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
779 unsigned long old_epc, unsigned long old_ra)
781 union mips_instruction inst = { .word = opcode };
782 void __user *fault_addr;
786 /* If it's obviously not an FP instruction, skip it */
787 switch (inst.i_format.opcode) {
801 * do_ri skipped over the instruction via compute_return_epc, undo
802 * that for the FPU emulator.
804 regs->cp0_epc = old_epc;
805 regs->regs[31] = old_ra;
807 /* Save the FP context to struct thread_struct */
810 /* Run the emulator */
811 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
815 * We can't allow the emulated instruction to leave any
816 * enabled Cause bits set in $fcr31.
818 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
819 current->thread.fpu.fcr31 &= ~fcr31;
821 /* Restore the hardware register state */
824 /* Send a signal if required. */
825 process_fpemu_return(sig, fault_addr, fcr31);
831 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
833 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
835 enum ctx_state prev_state;
836 void __user *fault_addr;
839 prev_state = exception_enter();
840 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
841 SIGFPE) == NOTIFY_STOP)
844 /* Clear FCSR.Cause before enabling interrupts */
845 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
848 die_if_kernel("FP exception in kernel code", regs);
850 if (fcr31 & FPU_CSR_UNI_X) {
852 * Unimplemented operation exception. If we've got the full
853 * software emulator on-board, let's use it...
855 * Force FPU to dump state into task/thread context. We're
856 * moving a lot of data here for what is probably a single
857 * instruction, but the alternative is to pre-decode the FP
858 * register operands before invoking the emulator, which seems
859 * a bit extreme for what should be an infrequent event.
861 /* Ensure 'resume' not overwrite saved fp context again. */
864 /* Run the emulator */
865 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
869 * We can't allow the emulated instruction to leave any
870 * enabled Cause bits set in $fcr31.
872 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
873 current->thread.fpu.fcr31 &= ~fcr31;
875 /* Restore the hardware register state */
876 own_fpu(1); /* Using the FPU again. */
879 fault_addr = (void __user *) regs->cp0_epc;
882 /* Send a signal if required. */
883 process_fpemu_return(sig, fault_addr, fcr31);
886 exception_exit(prev_state);
889 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
892 siginfo_t info = { 0 };
895 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
896 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
897 SIGTRAP) == NOTIFY_STOP)
899 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
901 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
902 SIGTRAP) == NOTIFY_STOP)
906 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
907 * insns, even for trap and break codes that indicate arithmetic
908 * failures. Weird ...
909 * But should we continue the brokenness??? --macro
914 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
915 die_if_kernel(b, regs);
916 if (code == BRK_DIVZERO)
917 info.si_code = FPE_INTDIV;
919 info.si_code = FPE_INTOVF;
920 info.si_signo = SIGFPE;
921 info.si_addr = (void __user *) regs->cp0_epc;
922 force_sig_info(SIGFPE, &info, current);
925 die_if_kernel("Kernel bug detected", regs);
926 force_sig(SIGTRAP, current);
930 * This breakpoint code is used by the FPU emulator to retake
931 * control of the CPU after executing the instruction from the
932 * delay slot of an emulated branch.
934 * Terminate if exception was recognized as a delay slot return
935 * otherwise handle as normal.
937 if (do_dsemulret(regs))
940 die_if_kernel("Math emu break/trap", regs);
941 force_sig(SIGTRAP, current);
944 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
945 die_if_kernel(b, regs);
947 info.si_signo = SIGTRAP;
948 info.si_code = si_code;
949 force_sig_info(SIGTRAP, &info, current);
951 force_sig(SIGTRAP, current);
956 asmlinkage void do_bp(struct pt_regs *regs)
958 unsigned long epc = msk_isa16_mode(exception_epc(regs));
959 unsigned int opcode, bcode;
960 enum ctx_state prev_state;
964 if (!user_mode(regs))
967 prev_state = exception_enter();
968 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
969 if (get_isa16_mode(regs->cp0_epc)) {
972 if (__get_user(instr[0], (u16 __user *)epc))
975 if (!cpu_has_mmips) {
977 bcode = (instr[0] >> 5) & 0x3f;
978 } else if (mm_insn_16bit(instr[0])) {
979 /* 16-bit microMIPS BREAK */
980 bcode = instr[0] & 0xf;
982 /* 32-bit microMIPS BREAK */
983 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
985 opcode = (instr[0] << 16) | instr[1];
986 bcode = (opcode >> 6) & ((1 << 20) - 1);
989 if (__get_user(opcode, (unsigned int __user *)epc))
991 bcode = (opcode >> 6) & ((1 << 20) - 1);
995 * There is the ancient bug in the MIPS assemblers that the break
996 * code starts left to bit 16 instead to bit 6 in the opcode.
997 * Gas is bug-compatible, but not always, grrr...
998 * We handle both cases with a simple heuristics. --macro
1000 if (bcode >= (1 << 10))
1001 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
1004 * notify the kprobe handlers, if instruction is likely to
1009 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1010 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1014 case BRK_UPROBE_XOL:
1015 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1016 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1021 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1022 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1026 case BRK_KPROBE_SSTEPBP:
1027 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1028 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1036 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1040 exception_exit(prev_state);
1044 force_sig(SIGSEGV, current);
1048 asmlinkage void do_tr(struct pt_regs *regs)
1050 u32 opcode, tcode = 0;
1051 enum ctx_state prev_state;
1054 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1057 if (!user_mode(regs))
1060 prev_state = exception_enter();
1061 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1062 if (get_isa16_mode(regs->cp0_epc)) {
1063 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1064 __get_user(instr[1], (u16 __user *)(epc + 2)))
1066 opcode = (instr[0] << 16) | instr[1];
1067 /* Immediate versions don't provide a code. */
1068 if (!(opcode & OPCODE))
1069 tcode = (opcode >> 12) & ((1 << 4) - 1);
1071 if (__get_user(opcode, (u32 __user *)epc))
1073 /* Immediate versions don't provide a code. */
1074 if (!(opcode & OPCODE))
1075 tcode = (opcode >> 6) & ((1 << 10) - 1);
1078 do_trap_or_bp(regs, tcode, 0, "Trap");
1082 exception_exit(prev_state);
1086 force_sig(SIGSEGV, current);
1090 asmlinkage void do_ri(struct pt_regs *regs)
1092 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1093 unsigned long old_epc = regs->cp0_epc;
1094 unsigned long old31 = regs->regs[31];
1095 enum ctx_state prev_state;
1096 unsigned int opcode = 0;
1100 * Avoid any kernel code. Just emulate the R2 instruction
1101 * as quickly as possible.
1103 if (mipsr2_emulation && cpu_has_mips_r6 &&
1104 likely(user_mode(regs)) &&
1105 likely(get_user(opcode, epc) >= 0)) {
1106 unsigned long fcr31 = 0;
1108 status = mipsr2_decoder(regs, opcode, &fcr31);
1116 process_fpemu_return(status,
1117 ¤t->thread.cp0_baduaddr,
1125 prev_state = exception_enter();
1126 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1128 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1129 SIGILL) == NOTIFY_STOP)
1132 die_if_kernel("Reserved instruction in kernel code", regs);
1134 if (unlikely(compute_return_epc(regs) < 0))
1137 if (!get_isa16_mode(regs->cp0_epc)) {
1138 if (unlikely(get_user(opcode, epc) < 0))
1141 if (!cpu_has_llsc && status < 0)
1142 status = simulate_llsc(regs, opcode);
1145 status = simulate_rdhwr_normal(regs, opcode);
1148 status = simulate_sync(regs, opcode);
1151 status = simulate_fp(regs, opcode, old_epc, old31);
1152 } else if (cpu_has_mmips) {
1153 unsigned short mmop[2] = { 0 };
1155 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1157 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1160 opcode = (opcode << 16) | mmop[1];
1163 status = simulate_rdhwr_mm(regs, opcode);
1169 if (unlikely(status > 0)) {
1170 regs->cp0_epc = old_epc; /* Undo skip-over. */
1171 regs->regs[31] = old31;
1172 force_sig(status, current);
1176 exception_exit(prev_state);
1180 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1181 * emulated more than some threshold number of instructions, force migration to
1182 * a "CPU" that has FP support.
1184 static void mt_ase_fp_affinity(void)
1186 #ifdef CONFIG_MIPS_MT_FPAFF
1187 if (mt_fpemul_threshold > 0 &&
1188 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1190 * If there's no FPU present, or if the application has already
1191 * restricted the allowed set to exclude any CPUs with FPUs,
1192 * we'll skip the procedure.
1194 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1197 current->thread.user_cpus_allowed
1198 = current->cpus_allowed;
1199 cpumask_and(&tmask, ¤t->cpus_allowed,
1201 set_cpus_allowed_ptr(current, &tmask);
1202 set_thread_flag(TIF_FPUBOUND);
1205 #endif /* CONFIG_MIPS_MT_FPAFF */
1209 * No lock; only written during early bootup by CPU 0.
1211 static RAW_NOTIFIER_HEAD(cu2_chain);
1213 int __ref register_cu2_notifier(struct notifier_block *nb)
1215 return raw_notifier_chain_register(&cu2_chain, nb);
1218 int cu2_notifier_call_chain(unsigned long val, void *v)
1220 return raw_notifier_call_chain(&cu2_chain, val, v);
1223 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1226 struct pt_regs *regs = data;
1228 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1229 "instruction", regs);
1230 force_sig(SIGILL, current);
1235 static int wait_on_fp_mode_switch(atomic_t *p)
1238 * The FP mode for this task is currently being switched. That may
1239 * involve modifications to the format of this tasks FP context which
1240 * make it unsafe to proceed with execution for the moment. Instead,
1241 * schedule some other task.
1247 static int enable_restore_fp_context(int msa)
1249 int err, was_fpu_owner, prior_msa;
1252 * If an FP mode switch is currently underway, wait for it to
1253 * complete before proceeding.
1255 wait_on_atomic_t(¤t->mm->context.fp_mode_switching,
1256 wait_on_fp_mode_switch, TASK_KILLABLE);
1259 /* First time FP context user. */
1265 set_thread_flag(TIF_USEDMSA);
1266 set_thread_flag(TIF_MSA_CTX_LIVE);
1275 * This task has formerly used the FP context.
1277 * If this thread has no live MSA vector context then we can simply
1278 * restore the scalar FP context. If it has live MSA vector context
1279 * (that is, it has or may have used MSA since last performing a
1280 * function call) then we'll need to restore the vector context. This
1281 * applies even if we're currently only executing a scalar FP
1282 * instruction. This is because if we were to later execute an MSA
1283 * instruction then we'd either have to:
1285 * - Restore the vector context & clobber any registers modified by
1286 * scalar FP instructions between now & then.
1290 * - Not restore the vector context & lose the most significant bits
1291 * of all vector registers.
1293 * Neither of those options is acceptable. We cannot restore the least
1294 * significant bits of the registers now & only restore the most
1295 * significant bits later because the most significant bits of any
1296 * vector registers whose aliased FP register is modified now will have
1297 * been zeroed. We'd have no way to know that when restoring the vector
1298 * context & thus may load an outdated value for the most significant
1299 * bits of a vector register.
1301 if (!msa && !thread_msa_context_live())
1305 * This task is using or has previously used MSA. Thus we require
1306 * that Status.FR == 1.
1309 was_fpu_owner = is_fpu_owner();
1310 err = own_fpu_inatomic(0);
1315 write_msa_csr(current->thread.fpu.msacsr);
1316 set_thread_flag(TIF_USEDMSA);
1319 * If this is the first time that the task is using MSA and it has
1320 * previously used scalar FP in this time slice then we already nave
1321 * FP context which we shouldn't clobber. We do however need to clear
1322 * the upper 64b of each vector register so that this task has no
1323 * opportunity to see data left behind by another.
1325 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1326 if (!prior_msa && was_fpu_owner) {
1334 * Restore the least significant 64b of each vector register
1335 * from the existing scalar FP context.
1337 _restore_fp(current);
1340 * The task has not formerly used MSA, so clear the upper 64b
1341 * of each vector register such that it cannot see data left
1342 * behind by another task.
1346 /* We need to restore the vector context. */
1347 restore_msa(current);
1349 /* Restore the scalar FP control & status register */
1351 write_32bit_cp1_register(CP1_STATUS,
1352 current->thread.fpu.fcr31);
1361 asmlinkage void do_cpu(struct pt_regs *regs)
1363 enum ctx_state prev_state;
1364 unsigned int __user *epc;
1365 unsigned long old_epc, old31;
1366 void __user *fault_addr;
1367 unsigned int opcode;
1368 unsigned long fcr31;
1373 prev_state = exception_enter();
1374 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1377 die_if_kernel("do_cpu invoked from kernel context!", regs);
1381 epc = (unsigned int __user *)exception_epc(regs);
1382 old_epc = regs->cp0_epc;
1383 old31 = regs->regs[31];
1387 if (unlikely(compute_return_epc(regs) < 0))
1390 if (!get_isa16_mode(regs->cp0_epc)) {
1391 if (unlikely(get_user(opcode, epc) < 0))
1394 if (!cpu_has_llsc && status < 0)
1395 status = simulate_llsc(regs, opcode);
1401 if (unlikely(status > 0)) {
1402 regs->cp0_epc = old_epc; /* Undo skip-over. */
1403 regs->regs[31] = old31;
1404 force_sig(status, current);
1411 * The COP3 opcode space and consequently the CP0.Status.CU3
1412 * bit and the CP0.Cause.CE=3 encoding have been removed as
1413 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1414 * up the space has been reused for COP1X instructions, that
1415 * are enabled by the CP0.Status.CU1 bit and consequently
1416 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1417 * exceptions. Some FPU-less processors that implement one
1418 * of these ISAs however use this code erroneously for COP1X
1419 * instructions. Therefore we redirect this trap to the FP
1422 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1423 force_sig(SIGILL, current);
1429 err = enable_restore_fp_context(0);
1431 if (raw_cpu_has_fpu && !err)
1434 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1438 * We can't allow the emulated instruction to leave
1439 * any enabled Cause bits set in $fcr31.
1441 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1442 current->thread.fpu.fcr31 &= ~fcr31;
1444 /* Send a signal if required. */
1445 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1446 mt_ase_fp_affinity();
1451 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1455 exception_exit(prev_state);
1458 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1460 enum ctx_state prev_state;
1462 prev_state = exception_enter();
1463 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1464 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1465 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1468 /* Clear MSACSR.Cause before enabling interrupts */
1469 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1472 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1473 force_sig(SIGFPE, current);
1475 exception_exit(prev_state);
1478 asmlinkage void do_msa(struct pt_regs *regs)
1480 enum ctx_state prev_state;
1483 prev_state = exception_enter();
1485 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1486 force_sig(SIGILL, current);
1490 die_if_kernel("do_msa invoked from kernel context!", regs);
1492 err = enable_restore_fp_context(1);
1494 force_sig(SIGILL, current);
1496 exception_exit(prev_state);
1499 asmlinkage void do_mdmx(struct pt_regs *regs)
1501 enum ctx_state prev_state;
1503 prev_state = exception_enter();
1504 force_sig(SIGILL, current);
1505 exception_exit(prev_state);
1509 * Called with interrupts disabled.
1511 asmlinkage void do_watch(struct pt_regs *regs)
1513 siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
1514 enum ctx_state prev_state;
1516 prev_state = exception_enter();
1518 * Clear WP (bit 22) bit of cause register so we don't loop
1521 clear_c0_cause(CAUSEF_WP);
1524 * If the current thread has the watch registers loaded, save
1525 * their values and send SIGTRAP. Otherwise another thread
1526 * left the registers set, clear them and continue.
1528 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1529 mips_read_watch_registers();
1531 force_sig_info(SIGTRAP, &info, current);
1533 mips_clear_watch_registers();
1536 exception_exit(prev_state);
1539 asmlinkage void do_mcheck(struct pt_regs *regs)
1541 int multi_match = regs->cp0_status & ST0_TS;
1542 enum ctx_state prev_state;
1543 mm_segment_t old_fs = get_fs();
1545 prev_state = exception_enter();
1554 if (!user_mode(regs))
1557 show_code((unsigned int __user *) regs->cp0_epc);
1562 * Some chips may have other causes of machine check (e.g. SB1
1565 panic("Caught Machine Check exception - %scaused by multiple "
1566 "matching entries in the TLB.",
1567 (multi_match) ? "" : "not ");
1570 asmlinkage void do_mt(struct pt_regs *regs)
1574 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1575 >> VPECONTROL_EXCPT_SHIFT;
1578 printk(KERN_DEBUG "Thread Underflow\n");
1581 printk(KERN_DEBUG "Thread Overflow\n");
1584 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1587 printk(KERN_DEBUG "Gating Storage Exception\n");
1590 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1593 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1596 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1600 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1602 force_sig(SIGILL, current);
1606 asmlinkage void do_dsp(struct pt_regs *regs)
1609 panic("Unexpected DSP exception");
1611 force_sig(SIGILL, current);
1614 asmlinkage void do_reserved(struct pt_regs *regs)
1617 * Game over - no way to handle this if it ever occurs. Most probably
1618 * caused by a new unknown cpu type or after another deadly
1619 * hard/software error.
1622 panic("Caught reserved exception %ld - should not happen.",
1623 (regs->cp0_cause & 0x7f) >> 2);
1626 static int __initdata l1parity = 1;
1627 static int __init nol1parity(char *s)
1632 __setup("nol1par", nol1parity);
1633 static int __initdata l2parity = 1;
1634 static int __init nol2parity(char *s)
1639 __setup("nol2par", nol2parity);
1642 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1643 * it different ways.
1645 static inline void parity_protection_init(void)
1647 #define ERRCTL_PE 0x80000000
1648 #define ERRCTL_L2P 0x00800000
1650 if (mips_cm_revision() >= CM_REV_CM3) {
1651 ulong gcr_ectl, cp0_ectl;
1654 * With CM3 systems we need to ensure that the L1 & L2
1655 * parity enables are set to the same value, since this
1656 * is presumed by the hardware engineers.
1658 * If the user disabled either of L1 or L2 ECC checking,
1661 l1parity &= l2parity;
1662 l2parity &= l1parity;
1664 /* Probe L1 ECC support */
1665 cp0_ectl = read_c0_ecc();
1666 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1667 back_to_back_c0_hazard();
1668 cp0_ectl = read_c0_ecc();
1670 /* Probe L2 ECC support */
1671 gcr_ectl = read_gcr_err_control();
1673 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK) ||
1674 !(cp0_ectl & ERRCTL_PE)) {
1676 * One of L1 or L2 ECC checking isn't supported,
1677 * so we cannot enable either.
1679 l1parity = l2parity = 0;
1682 /* Configure L1 ECC checking */
1684 cp0_ectl |= ERRCTL_PE;
1686 cp0_ectl &= ~ERRCTL_PE;
1687 write_c0_ecc(cp0_ectl);
1688 back_to_back_c0_hazard();
1689 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1691 /* Configure L2 ECC checking */
1693 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1695 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1696 write_gcr_err_control(gcr_ectl);
1697 gcr_ectl = read_gcr_err_control();
1698 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1699 WARN_ON(!!gcr_ectl != l2parity);
1701 pr_info("Cache parity protection %sabled\n",
1702 l1parity ? "en" : "dis");
1706 switch (current_cpu_type()) {
1712 case CPU_INTERAPTIV:
1715 case CPU_QEMU_GENERIC:
1718 unsigned long errctl;
1719 unsigned int l1parity_present, l2parity_present;
1721 errctl = read_c0_ecc();
1722 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1724 /* probe L1 parity support */
1725 write_c0_ecc(errctl | ERRCTL_PE);
1726 back_to_back_c0_hazard();
1727 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1729 /* probe L2 parity support */
1730 write_c0_ecc(errctl|ERRCTL_L2P);
1731 back_to_back_c0_hazard();
1732 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1734 if (l1parity_present && l2parity_present) {
1736 errctl |= ERRCTL_PE;
1737 if (l1parity ^ l2parity)
1738 errctl |= ERRCTL_L2P;
1739 } else if (l1parity_present) {
1741 errctl |= ERRCTL_PE;
1742 } else if (l2parity_present) {
1744 errctl |= ERRCTL_L2P;
1746 /* No parity available */
1749 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1751 write_c0_ecc(errctl);
1752 back_to_back_c0_hazard();
1753 errctl = read_c0_ecc();
1754 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1756 if (l1parity_present)
1757 printk(KERN_INFO "Cache parity protection %sabled\n",
1758 (errctl & ERRCTL_PE) ? "en" : "dis");
1760 if (l2parity_present) {
1761 if (l1parity_present && l1parity)
1762 errctl ^= ERRCTL_L2P;
1763 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1764 (errctl & ERRCTL_L2P) ? "en" : "dis");
1772 write_c0_ecc(0x80000000);
1773 back_to_back_c0_hazard();
1774 /* Set the PE bit (bit 31) in the c0_errctl register. */
1775 printk(KERN_INFO "Cache parity protection %sabled\n",
1776 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1780 /* Clear the DE bit (bit 16) in the c0_status register. */
1781 printk(KERN_INFO "Enable cache parity protection for "
1782 "MIPS 20KC/25KF CPUs.\n");
1783 clear_c0_status(ST0_DE);
1790 asmlinkage void cache_parity_error(void)
1792 const int field = 2 * sizeof(unsigned long);
1793 unsigned int reg_val;
1795 /* For the moment, report the problem and hang. */
1796 printk("Cache error exception:\n");
1797 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1798 reg_val = read_c0_cacheerr();
1799 printk("c0_cacheerr == %08x\n", reg_val);
1801 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1802 reg_val & (1<<30) ? "secondary" : "primary",
1803 reg_val & (1<<31) ? "data" : "insn");
1804 if ((cpu_has_mips_r2_r6) &&
1805 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1806 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1807 reg_val & (1<<29) ? "ED " : "",
1808 reg_val & (1<<28) ? "ET " : "",
1809 reg_val & (1<<27) ? "ES " : "",
1810 reg_val & (1<<26) ? "EE " : "",
1811 reg_val & (1<<25) ? "EB " : "",
1812 reg_val & (1<<24) ? "EI " : "",
1813 reg_val & (1<<23) ? "E1 " : "",
1814 reg_val & (1<<22) ? "E0 " : "");
1816 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1817 reg_val & (1<<29) ? "ED " : "",
1818 reg_val & (1<<28) ? "ET " : "",
1819 reg_val & (1<<26) ? "EE " : "",
1820 reg_val & (1<<25) ? "EB " : "",
1821 reg_val & (1<<24) ? "EI " : "",
1822 reg_val & (1<<23) ? "E1 " : "",
1823 reg_val & (1<<22) ? "E0 " : "");
1825 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1827 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1828 if (reg_val & (1<<22))
1829 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1831 if (reg_val & (1<<23))
1832 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1835 panic("Can't handle the cache error!");
1838 asmlinkage void do_ftlb(void)
1840 const int field = 2 * sizeof(unsigned long);
1841 unsigned int reg_val;
1843 /* For the moment, report the problem and hang. */
1844 if ((cpu_has_mips_r2_r6) &&
1845 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1846 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1847 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1849 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1850 reg_val = read_c0_cacheerr();
1851 pr_err("c0_cacheerr == %08x\n", reg_val);
1853 if ((reg_val & 0xc0000000) == 0xc0000000) {
1854 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1856 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1857 reg_val & (1<<30) ? "secondary" : "primary",
1858 reg_val & (1<<31) ? "data" : "insn");
1861 pr_err("FTLB error exception\n");
1863 /* Just print the cacheerr bits for now */
1864 cache_parity_error();
1868 * SDBBP EJTAG debug exception handler.
1869 * We skip the instruction and return to the next instruction.
1871 void ejtag_exception_handler(struct pt_regs *regs)
1873 const int field = 2 * sizeof(unsigned long);
1874 unsigned long depc, old_epc, old_ra;
1877 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1878 depc = read_c0_depc();
1879 debug = read_c0_debug();
1880 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1881 if (debug & 0x80000000) {
1883 * In branch delay slot.
1884 * We cheat a little bit here and use EPC to calculate the
1885 * debug return address (DEPC). EPC is restored after the
1888 old_epc = regs->cp0_epc;
1889 old_ra = regs->regs[31];
1890 regs->cp0_epc = depc;
1891 compute_return_epc(regs);
1892 depc = regs->cp0_epc;
1893 regs->cp0_epc = old_epc;
1894 regs->regs[31] = old_ra;
1897 write_c0_depc(depc);
1900 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1901 write_c0_debug(debug | 0x100);
1906 * NMI exception handler.
1907 * No lock; only written during early bootup by CPU 0.
1909 static RAW_NOTIFIER_HEAD(nmi_chain);
1911 int register_nmi_notifier(struct notifier_block *nb)
1913 return raw_notifier_chain_register(&nmi_chain, nb);
1916 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1921 raw_notifier_call_chain(&nmi_chain, 0, regs);
1923 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1924 smp_processor_id(), regs->cp0_epc);
1925 regs->cp0_epc = read_c0_errorepc();
1930 #define VECTORSPACING 0x100 /* for EI/VI mode */
1932 unsigned long ebase;
1933 EXPORT_SYMBOL_GPL(ebase);
1934 unsigned long exception_handlers[32];
1935 unsigned long vi_handlers[64];
1937 void __init *set_except_vector(int n, void *addr)
1939 unsigned long handler = (unsigned long) addr;
1940 unsigned long old_handler;
1942 #ifdef CONFIG_CPU_MICROMIPS
1944 * Only the TLB handlers are cache aligned with an even
1945 * address. All other handlers are on an odd address and
1946 * require no modification. Otherwise, MIPS32 mode will
1947 * be entered when handling any TLB exceptions. That
1948 * would be bad...since we must stay in microMIPS mode.
1950 if (!(handler & 0x1))
1953 old_handler = xchg(&exception_handlers[n], handler);
1955 if (n == 0 && cpu_has_divec) {
1956 #ifdef CONFIG_CPU_MICROMIPS
1957 unsigned long jump_mask = ~((1 << 27) - 1);
1959 unsigned long jump_mask = ~((1 << 28) - 1);
1961 u32 *buf = (u32 *)(ebase + 0x200);
1962 unsigned int k0 = 26;
1963 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1964 uasm_i_j(&buf, handler & ~jump_mask);
1967 UASM_i_LA(&buf, k0, handler);
1968 uasm_i_jr(&buf, k0);
1971 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1973 return (void *)old_handler;
1976 static void do_default_vi(void)
1978 show_regs(get_irq_regs());
1979 panic("Caught unexpected vectored interrupt.");
1982 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1984 unsigned long handler;
1985 unsigned long old_handler = vi_handlers[n];
1986 int srssets = current_cpu_data.srsets;
1990 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1993 handler = (unsigned long) do_default_vi;
1996 handler = (unsigned long) addr;
1997 vi_handlers[n] = handler;
1999 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
2002 panic("Shadow register set %d not supported", srs);
2005 if (board_bind_eic_interrupt)
2006 board_bind_eic_interrupt(n, srs);
2007 } else if (cpu_has_vint) {
2008 /* SRSMap is only defined if shadow sets are implemented */
2010 change_c0_srsmap(0xf << n*4, srs << n*4);
2015 * If no shadow set is selected then use the default handler
2016 * that does normal register saving and standard interrupt exit
2018 extern char except_vec_vi, except_vec_vi_lui;
2019 extern char except_vec_vi_ori, except_vec_vi_end;
2020 extern char rollback_except_vec_vi;
2021 char *vec_start = using_rollback_handler() ?
2022 &rollback_except_vec_vi : &except_vec_vi;
2023 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2024 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
2025 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
2027 const int lui_offset = &except_vec_vi_lui - vec_start;
2028 const int ori_offset = &except_vec_vi_ori - vec_start;
2030 const int handler_len = &except_vec_vi_end - vec_start;
2032 if (handler_len > VECTORSPACING) {
2034 * Sigh... panicing won't help as the console
2035 * is probably not configured :(
2037 panic("VECTORSPACING too small");
2040 set_handler(((unsigned long)b - ebase), vec_start,
2041 #ifdef CONFIG_CPU_MICROMIPS
2046 h = (u16 *)(b + lui_offset);
2047 *h = (handler >> 16) & 0xffff;
2048 h = (u16 *)(b + ori_offset);
2049 *h = (handler & 0xffff);
2050 local_flush_icache_range((unsigned long)b,
2051 (unsigned long)(b+handler_len));
2055 * In other cases jump directly to the interrupt handler. It
2056 * is the handler's responsibility to save registers if required
2057 * (eg hi/lo) and return from the exception using "eret".
2063 #ifdef CONFIG_CPU_MICROMIPS
2064 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2066 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2068 h[0] = (insn >> 16) & 0xffff;
2069 h[1] = insn & 0xffff;
2072 local_flush_icache_range((unsigned long)b,
2073 (unsigned long)(b+8));
2076 return (void *)old_handler;
2079 void *set_vi_handler(int n, vi_handler_t addr)
2081 return set_vi_srs_handler(n, addr, 0);
2084 extern void tlb_init(void);
2089 int cp0_compare_irq;
2090 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2091 int cp0_compare_irq_shift;
2094 * Performance counter IRQ or -1 if shared with timer
2096 int cp0_perfcount_irq;
2097 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2100 * Fast debug channel IRQ or -1 if not present
2103 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2107 static int __init ulri_disable(char *s)
2109 pr_info("Disabling ulri\n");
2114 __setup("noulri", ulri_disable);
2116 /* configure STATUS register */
2117 static void configure_status(void)
2120 * Disable coprocessors and select 32-bit or 64-bit addressing
2121 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2122 * flag that some firmware may have left set and the TS bit (for
2123 * IP27). Set XX for ISA IV code to work.
2125 unsigned int status_set = ST0_CU0;
2127 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2129 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2130 status_set |= ST0_XX;
2132 status_set |= ST0_MX;
2134 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2138 unsigned int hwrena;
2139 EXPORT_SYMBOL_GPL(hwrena);
2141 /* configure HWRENA register */
2142 static void configure_hwrena(void)
2144 hwrena = cpu_hwrena_impl_bits;
2146 if (cpu_has_mips_r2_r6)
2147 hwrena |= MIPS_HWRENA_CPUNUM |
2148 MIPS_HWRENA_SYNCISTEP |
2152 if (!noulri && cpu_has_userlocal)
2153 hwrena |= MIPS_HWRENA_ULR;
2156 write_c0_hwrena(hwrena);
2159 static void configure_exception_vector(void)
2161 if (cpu_has_veic || cpu_has_vint) {
2162 unsigned long sr = set_c0_status(ST0_BEV);
2163 /* If available, use WG to set top bits of EBASE */
2164 if (cpu_has_ebase_wg) {
2166 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2168 write_c0_ebase(ebase | MIPS_EBASE_WG);
2171 write_c0_ebase(ebase);
2172 write_c0_status(sr);
2173 /* Setting vector spacing enables EI/VI mode */
2174 change_c0_intctl(0x3e0, VECTORSPACING);
2176 if (cpu_has_divec) {
2177 if (cpu_has_mipsmt) {
2178 unsigned int vpflags = dvpe();
2179 set_c0_cause(CAUSEF_IV);
2182 set_c0_cause(CAUSEF_IV);
2186 void per_cpu_trap_init(bool is_boot_cpu)
2188 unsigned int cpu = smp_processor_id();
2193 configure_exception_vector();
2196 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2198 * o read IntCtl.IPTI to determine the timer interrupt
2199 * o read IntCtl.IPPCI to determine the performance counter interrupt
2200 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2202 if (cpu_has_mips_r2_r6) {
2204 * We shouldn't trust a secondary core has a sane EBASE register
2205 * so use the one calculated by the boot CPU.
2208 /* If available, use WG to set top bits of EBASE */
2209 if (cpu_has_ebase_wg) {
2211 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2213 write_c0_ebase(ebase | MIPS_EBASE_WG);
2216 write_c0_ebase(ebase);
2219 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2220 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2221 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2222 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2227 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2228 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2229 cp0_perfcount_irq = -1;
2233 if (!cpu_data[cpu].asid_cache)
2234 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2237 current->active_mm = &init_mm;
2238 BUG_ON(current->mm);
2239 enter_lazy_tlb(&init_mm, current);
2241 /* Boot CPU's cache setup in setup_arch(). */
2245 TLBMISS_HANDLER_SETUP();
2248 /* Install CPU exception handler */
2249 void set_handler(unsigned long offset, void *addr, unsigned long size)
2251 #ifdef CONFIG_CPU_MICROMIPS
2252 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2254 memcpy((void *)(ebase + offset), addr, size);
2256 local_flush_icache_range(ebase + offset, ebase + offset + size);
2259 static const char panic_null_cerr[] =
2260 "Trying to set NULL cache error exception handler\n";
2263 * Install uncached CPU exception handler.
2264 * This is suitable only for the cache error exception which is the only
2265 * exception handler that is being run uncached.
2267 void set_uncached_handler(unsigned long offset, void *addr,
2270 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2273 panic(panic_null_cerr);
2275 memcpy((void *)(uncached_ebase + offset), addr, size);
2278 static int __initdata rdhwr_noopt;
2279 static int __init set_rdhwr_noopt(char *str)
2285 __setup("rdhwr_noopt", set_rdhwr_noopt);
2287 void __init trap_init(void)
2289 extern char except_vec3_generic;
2290 extern char except_vec4;
2291 extern char except_vec3_r4000;
2296 if (cpu_has_veic || cpu_has_vint) {
2297 unsigned long size = 0x200 + VECTORSPACING*64;
2298 phys_addr_t ebase_pa;
2300 ebase = (unsigned long)
2301 __alloc_bootmem(size, 1 << fls(size), 0);
2304 * Try to ensure ebase resides in KSeg0 if possible.
2306 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2307 * hitting a poorly defined exception base for Cache Errors.
2308 * The allocation is likely to be in the low 512MB of physical,
2309 * in which case we should be able to convert to KSeg0.
2311 * EVA is special though as it allows segments to be rearranged
2312 * and to become uncached during cache error handling.
2314 ebase_pa = __pa(ebase);
2315 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2316 ebase = CKSEG0ADDR(ebase_pa);
2320 if (cpu_has_mips_r2_r6) {
2321 if (cpu_has_ebase_wg) {
2323 ebase = (read_c0_ebase_64() & ~0xfff);
2325 ebase = (read_c0_ebase() & ~0xfff);
2328 ebase += (read_c0_ebase() & 0x3ffff000);
2333 if (cpu_has_mmips) {
2334 unsigned int config3 = read_c0_config3();
2336 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2337 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2339 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2342 if (board_ebase_setup)
2343 board_ebase_setup();
2344 per_cpu_trap_init(true);
2347 * Copy the generic exception handlers to their final destination.
2348 * This will be overridden later as suitable for a particular
2351 set_handler(0x180, &except_vec3_generic, 0x80);
2354 * Setup default vectors
2356 for (i = 0; i <= 31; i++)
2357 set_except_vector(i, handle_reserved);
2360 * Copy the EJTAG debug exception vector handler code to it's final
2363 if (cpu_has_ejtag && board_ejtag_handler_setup)
2364 board_ejtag_handler_setup();
2367 * Only some CPUs have the watch exceptions.
2370 set_except_vector(EXCCODE_WATCH, handle_watch);
2373 * Initialise interrupt handlers
2375 if (cpu_has_veic || cpu_has_vint) {
2376 int nvec = cpu_has_veic ? 64 : 8;
2377 for (i = 0; i < nvec; i++)
2378 set_vi_handler(i, NULL);
2380 else if (cpu_has_divec)
2381 set_handler(0x200, &except_vec4, 0x8);
2384 * Some CPUs can enable/disable for cache parity detection, but does
2385 * it different ways.
2387 parity_protection_init();
2390 * The Data Bus Errors / Instruction Bus Errors are signaled
2391 * by external hardware. Therefore these two exceptions
2392 * may have board specific handlers.
2397 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2398 rollback_handle_int : handle_int);
2399 set_except_vector(EXCCODE_MOD, handle_tlbm);
2400 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2401 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2403 set_except_vector(EXCCODE_ADEL, handle_adel);
2404 set_except_vector(EXCCODE_ADES, handle_ades);
2406 set_except_vector(EXCCODE_IBE, handle_ibe);
2407 set_except_vector(EXCCODE_DBE, handle_dbe);
2409 set_except_vector(EXCCODE_SYS, handle_sys);
2410 set_except_vector(EXCCODE_BP, handle_bp);
2413 set_except_vector(EXCCODE_RI, handle_ri);
2415 if (cpu_has_vtag_icache)
2416 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2417 else if (current_cpu_type() == CPU_LOONGSON3)
2418 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2420 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2423 set_except_vector(EXCCODE_CPU, handle_cpu);
2424 set_except_vector(EXCCODE_OV, handle_ov);
2425 set_except_vector(EXCCODE_TR, handle_tr);
2426 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2428 if (current_cpu_type() == CPU_R6000 ||
2429 current_cpu_type() == CPU_R6000A) {
2431 * The R6000 is the only R-series CPU that features a machine
2432 * check exception (similar to the R4000 cache error) and
2433 * unaligned ldc1/sdc1 exception. The handlers have not been
2434 * written yet. Well, anyway there is no R6000 machine on the
2435 * current list of targets for Linux/MIPS.
2436 * (Duh, crap, there is someone with a triple R6k machine)
2438 //set_except_vector(14, handle_mc);
2439 //set_except_vector(15, handle_ndc);
2443 if (board_nmi_handler_setup)
2444 board_nmi_handler_setup();
2446 if (cpu_has_fpu && !cpu_has_nofpuex)
2447 set_except_vector(EXCCODE_FPE, handle_fpe);
2449 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2451 if (cpu_has_rixiex) {
2452 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2453 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2456 set_except_vector(EXCCODE_MSADIS, handle_msa);
2457 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2460 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2463 set_except_vector(EXCCODE_THREAD, handle_mt);
2465 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2467 if (board_cache_error_setup)
2468 board_cache_error_setup();
2471 /* Special exception: R4[04]00 uses also the divec space. */
2472 set_handler(0x180, &except_vec3_r4000, 0x100);
2473 else if (cpu_has_4kex)
2474 set_handler(0x180, &except_vec3_generic, 0x80);
2476 set_handler(0x080, &except_vec3_generic, 0x80);
2478 local_flush_icache_range(ebase, ebase + 0x400);
2480 sort_extable(__start___dbe_table, __stop___dbe_table);
2482 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2485 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2489 case CPU_PM_ENTER_FAILED:
2493 configure_exception_vector();
2495 /* Restore register with CPU number for TLB handlers */
2496 TLBMISS_HANDLER_RESTORE();
2504 static struct notifier_block trap_pm_notifier_block = {
2505 .notifier_call = trap_pm_notifier,
2508 static int __init trap_pm_init(void)
2510 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2512 arch_initcall(trap_pm_init);