2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/kprobes.h>
29 #include <linux/notifier.h>
30 #include <linux/kdb.h>
31 #include <linux/irq.h>
32 #include <linux/perf_event.h>
34 #include <asm/bootinfo.h>
35 #include <asm/branch.h>
36 #include <asm/break.h>
41 #include <asm/fpu_emulator.h>
42 #include <asm/mipsregs.h>
43 #include <asm/mipsmtregs.h>
44 #include <asm/module.h>
45 #include <asm/pgtable.h>
46 #include <asm/ptrace.h>
47 #include <asm/sections.h>
48 #include <asm/system.h>
49 #include <asm/tlbdebug.h>
50 #include <asm/traps.h>
51 #include <asm/uaccess.h>
52 #include <asm/watch.h>
53 #include <asm/mmu_context.h>
54 #include <asm/types.h>
55 #include <asm/stacktrace.h>
58 extern void check_wait(void);
59 extern asmlinkage void r4k_wait(void);
60 extern asmlinkage void rollback_handle_int(void);
61 extern asmlinkage void handle_int(void);
62 extern asmlinkage void handle_tlbm(void);
63 extern asmlinkage void handle_tlbl(void);
64 extern asmlinkage void handle_tlbs(void);
65 extern asmlinkage void handle_adel(void);
66 extern asmlinkage void handle_ades(void);
67 extern asmlinkage void handle_ibe(void);
68 extern asmlinkage void handle_dbe(void);
69 extern asmlinkage void handle_sys(void);
70 extern asmlinkage void handle_bp(void);
71 extern asmlinkage void handle_ri(void);
72 extern asmlinkage void handle_ri_rdhwr_vivt(void);
73 extern asmlinkage void handle_ri_rdhwr(void);
74 extern asmlinkage void handle_cpu(void);
75 extern asmlinkage void handle_ov(void);
76 extern asmlinkage void handle_tr(void);
77 extern asmlinkage void handle_fpe(void);
78 extern asmlinkage void handle_mdmx(void);
79 extern asmlinkage void handle_watch(void);
80 extern asmlinkage void handle_mt(void);
81 extern asmlinkage void handle_dsp(void);
82 extern asmlinkage void handle_mcheck(void);
83 extern asmlinkage void handle_reserved(void);
85 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
86 struct mips_fpu_struct *ctx, int has_fpu,
87 void *__user *fault_addr);
89 void (*board_be_init)(void);
90 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
91 void (*board_nmi_handler_setup)(void);
92 void (*board_ejtag_handler_setup)(void);
93 void (*board_bind_eic_interrupt)(int irq, int regset);
96 static void show_raw_backtrace(unsigned long reg29)
98 unsigned long *sp = (unsigned long *)(reg29 & ~3);
101 printk("Call Trace:");
102 #ifdef CONFIG_KALLSYMS
105 while (!kstack_end(sp)) {
106 unsigned long __user *p =
107 (unsigned long __user *)(unsigned long)sp++;
108 if (__get_user(addr, p)) {
109 printk(" (Bad stack address)");
112 if (__kernel_text_address(addr))
118 #ifdef CONFIG_KALLSYMS
120 static int __init set_raw_show_trace(char *str)
125 __setup("raw_show_trace", set_raw_show_trace);
128 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
130 unsigned long sp = regs->regs[29];
131 unsigned long ra = regs->regs[31];
132 unsigned long pc = regs->cp0_epc;
134 if (raw_show_trace || !__kernel_text_address(pc)) {
135 show_raw_backtrace(sp);
138 printk("Call Trace:\n");
141 pc = unwind_stack(task, &sp, pc, &ra);
147 * This routine abuses get_user()/put_user() to reference pointers
148 * with at least a bit of error checking ...
150 static void show_stacktrace(struct task_struct *task,
151 const struct pt_regs *regs)
153 const int field = 2 * sizeof(unsigned long);
156 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
160 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
161 if (i && ((i % (64 / field)) == 0))
168 if (__get_user(stackdata, sp++)) {
169 printk(" (Bad stack address)");
173 printk(" %0*lx", field, stackdata);
177 show_backtrace(task, regs);
180 void show_stack(struct task_struct *task, unsigned long *sp)
184 regs.regs[29] = (unsigned long)sp;
188 if (task && task != current) {
189 regs.regs[29] = task->thread.reg29;
191 regs.cp0_epc = task->thread.reg31;
192 #ifdef CONFIG_KGDB_KDB
193 } else if (atomic_read(&kgdb_active) != -1 &&
195 memcpy(®s, kdb_current_regs, sizeof(regs));
196 #endif /* CONFIG_KGDB_KDB */
198 prepare_frametrace(®s);
201 show_stacktrace(task, ®s);
205 * The architecture-independent dump_stack generator
207 void dump_stack(void)
211 prepare_frametrace(®s);
212 show_backtrace(current, ®s);
215 EXPORT_SYMBOL(dump_stack);
217 static void show_code(unsigned int __user *pc)
220 unsigned short __user *pc16 = NULL;
224 if ((unsigned long)pc & 1)
225 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
226 for(i = -3 ; i < 6 ; i++) {
228 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
229 printk(" (Bad address in epc)\n");
232 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
236 static void __show_regs(const struct pt_regs *regs)
238 const int field = 2 * sizeof(unsigned long);
239 unsigned int cause = regs->cp0_cause;
242 printk("Cpu %d\n", smp_processor_id());
245 * Saved main processor registers
247 for (i = 0; i < 32; ) {
251 printk(" %0*lx", field, 0UL);
252 else if (i == 26 || i == 27)
253 printk(" %*s", field, "");
255 printk(" %0*lx", field, regs->regs[i]);
262 #ifdef CONFIG_CPU_HAS_SMARTMIPS
263 printk("Acx : %0*lx\n", field, regs->acx);
265 printk("Hi : %0*lx\n", field, regs->hi);
266 printk("Lo : %0*lx\n", field, regs->lo);
269 * Saved cp0 registers
271 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
272 (void *) regs->cp0_epc);
273 printk(" %s\n", print_tainted());
274 printk("ra : %0*lx %pS\n", field, regs->regs[31],
275 (void *) regs->regs[31]);
277 printk("Status: %08x ", (uint32_t) regs->cp0_status);
279 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
280 if (regs->cp0_status & ST0_KUO)
282 if (regs->cp0_status & ST0_IEO)
284 if (regs->cp0_status & ST0_KUP)
286 if (regs->cp0_status & ST0_IEP)
288 if (regs->cp0_status & ST0_KUC)
290 if (regs->cp0_status & ST0_IEC)
293 if (regs->cp0_status & ST0_KX)
295 if (regs->cp0_status & ST0_SX)
297 if (regs->cp0_status & ST0_UX)
299 switch (regs->cp0_status & ST0_KSU) {
304 printk("SUPERVISOR ");
313 if (regs->cp0_status & ST0_ERL)
315 if (regs->cp0_status & ST0_EXL)
317 if (regs->cp0_status & ST0_IE)
322 printk("Cause : %08x\n", cause);
324 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
325 if (1 <= cause && cause <= 5)
326 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
328 printk("PrId : %08x (%s)\n", read_c0_prid(),
333 * FIXME: really the generic show_regs should take a const pointer argument.
335 void show_regs(struct pt_regs *regs)
337 __show_regs((struct pt_regs *)regs);
340 void show_registers(struct pt_regs *regs)
342 const int field = 2 * sizeof(unsigned long);
346 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
347 current->comm, current->pid, current_thread_info(), current,
348 field, current_thread_info()->tp_value);
349 if (cpu_has_userlocal) {
352 tls = read_c0_userlocal();
353 if (tls != current_thread_info()->tp_value)
354 printk("*HwTLS: %0*lx\n", field, tls);
357 show_stacktrace(current, regs);
358 show_code((unsigned int __user *) regs->cp0_epc);
362 static int regs_to_trapnr(struct pt_regs *regs)
364 return (regs->cp0_cause >> 2) & 0x1f;
367 static DEFINE_RAW_SPINLOCK(die_lock);
369 void __noreturn die(const char *str, struct pt_regs *regs)
371 static int die_counter;
373 #ifdef CONFIG_MIPS_MT_SMTC
374 unsigned long dvpret;
375 #endif /* CONFIG_MIPS_MT_SMTC */
379 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
383 raw_spin_lock_irq(&die_lock);
384 #ifdef CONFIG_MIPS_MT_SMTC
386 #endif /* CONFIG_MIPS_MT_SMTC */
388 #ifdef CONFIG_MIPS_MT_SMTC
389 mips_mt_regdump(dvpret);
390 #endif /* CONFIG_MIPS_MT_SMTC */
392 printk("%s[#%d]:\n", str, ++die_counter);
393 show_registers(regs);
394 add_taint(TAINT_DIE);
395 raw_spin_unlock_irq(&die_lock);
400 panic("Fatal exception in interrupt");
403 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
405 panic("Fatal exception");
411 extern struct exception_table_entry __start___dbe_table[];
412 extern struct exception_table_entry __stop___dbe_table[];
415 " .section __dbe_table, \"a\"\n"
418 /* Given an address, look for it in the exception tables. */
419 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
421 const struct exception_table_entry *e;
423 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
425 e = search_module_dbetables(addr);
429 asmlinkage void do_be(struct pt_regs *regs)
431 const int field = 2 * sizeof(unsigned long);
432 const struct exception_table_entry *fixup = NULL;
433 int data = regs->cp0_cause & 4;
434 int action = MIPS_BE_FATAL;
436 /* XXX For now. Fixme, this searches the wrong table ... */
437 if (data && !user_mode(regs))
438 fixup = search_dbe_tables(exception_epc(regs));
441 action = MIPS_BE_FIXUP;
443 if (board_be_handler)
444 action = board_be_handler(regs, fixup != NULL);
447 case MIPS_BE_DISCARD:
451 regs->cp0_epc = fixup->nextinsn;
460 * Assume it would be too dangerous to continue ...
462 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
463 data ? "Data" : "Instruction",
464 field, regs->cp0_epc, field, regs->regs[31]);
465 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
469 die_if_kernel("Oops", regs);
470 force_sig(SIGBUS, current);
474 * ll/sc, rdhwr, sync emulation
477 #define OPCODE 0xfc000000
478 #define BASE 0x03e00000
479 #define RT 0x001f0000
480 #define OFFSET 0x0000ffff
481 #define LL 0xc0000000
482 #define SC 0xe0000000
483 #define SPEC0 0x00000000
484 #define SPEC3 0x7c000000
485 #define RD 0x0000f800
486 #define FUNC 0x0000003f
487 #define SYNC 0x0000000f
488 #define RDHWR 0x0000003b
491 * The ll_bit is cleared by r*_switch.S
495 struct task_struct *ll_task;
497 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
499 unsigned long value, __user *vaddr;
503 * analyse the ll instruction that just caused a ri exception
504 * and put the referenced address to addr.
507 /* sign extend offset */
508 offset = opcode & OFFSET;
512 vaddr = (unsigned long __user *)
513 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
515 if ((unsigned long)vaddr & 3)
517 if (get_user(value, vaddr))
522 if (ll_task == NULL || ll_task == current) {
531 regs->regs[(opcode & RT) >> 16] = value;
536 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
538 unsigned long __user *vaddr;
543 * analyse the sc instruction that just caused a ri exception
544 * and put the referenced address to addr.
547 /* sign extend offset */
548 offset = opcode & OFFSET;
552 vaddr = (unsigned long __user *)
553 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
554 reg = (opcode & RT) >> 16;
556 if ((unsigned long)vaddr & 3)
561 if (ll_bit == 0 || ll_task != current) {
569 if (put_user(regs->regs[reg], vaddr))
578 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
579 * opcodes are supposed to result in coprocessor unusable exceptions if
580 * executed on ll/sc-less processors. That's the theory. In practice a
581 * few processors such as NEC's VR4100 throw reserved instruction exceptions
582 * instead, so we're doing the emulation thing in both exception handlers.
584 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
586 if ((opcode & OPCODE) == LL) {
587 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
589 return simulate_ll(regs, opcode);
591 if ((opcode & OPCODE) == SC) {
592 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
594 return simulate_sc(regs, opcode);
597 return -1; /* Must be something else ... */
601 * Simulate trapping 'rdhwr' instructions to provide user accessible
602 * registers not implemented in hardware.
604 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
606 struct thread_info *ti = task_thread_info(current);
608 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
609 int rd = (opcode & RD) >> 11;
610 int rt = (opcode & RT) >> 16;
611 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
614 case 0: /* CPU number */
615 regs->regs[rt] = smp_processor_id();
617 case 1: /* SYNCI length */
618 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
619 current_cpu_data.icache.linesz);
621 case 2: /* Read count register */
622 regs->regs[rt] = read_c0_count();
624 case 3: /* Count register resolution */
625 switch (current_cpu_data.cputype) {
635 regs->regs[rt] = ti->tp_value;
646 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
648 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
649 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
654 return -1; /* Must be something else ... */
657 asmlinkage void do_ov(struct pt_regs *regs)
661 die_if_kernel("Integer overflow", regs);
663 info.si_code = FPE_INTOVF;
664 info.si_signo = SIGFPE;
666 info.si_addr = (void __user *) regs->cp0_epc;
667 force_sig_info(SIGFPE, &info, current);
670 static int process_fpemu_return(int sig, void __user *fault_addr)
672 if (sig == SIGSEGV || sig == SIGBUS) {
673 struct siginfo si = {0};
674 si.si_addr = fault_addr;
676 if (sig == SIGSEGV) {
677 if (find_vma(current->mm, (unsigned long)fault_addr))
678 si.si_code = SEGV_ACCERR;
680 si.si_code = SEGV_MAPERR;
682 si.si_code = BUS_ADRERR;
684 force_sig_info(sig, &si, current);
687 force_sig(sig, current);
695 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
697 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
699 siginfo_t info = {0};
701 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
704 die_if_kernel("FP exception in kernel code", regs);
706 if (fcr31 & FPU_CSR_UNI_X) {
708 void __user *fault_addr = NULL;
711 * Unimplemented operation exception. If we've got the full
712 * software emulator on-board, let's use it...
714 * Force FPU to dump state into task/thread context. We're
715 * moving a lot of data here for what is probably a single
716 * instruction, but the alternative is to pre-decode the FP
717 * register operands before invoking the emulator, which seems
718 * a bit extreme for what should be an infrequent event.
720 /* Ensure 'resume' not overwrite saved fp context again. */
723 /* Run the emulator */
724 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
728 * We can't allow the emulated instruction to leave any of
729 * the cause bit set in $fcr31.
731 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
733 /* Restore the hardware register state */
734 own_fpu(1); /* Using the FPU again. */
736 /* If something went wrong, signal */
737 process_fpemu_return(sig, fault_addr);
740 } else if (fcr31 & FPU_CSR_INV_X)
741 info.si_code = FPE_FLTINV;
742 else if (fcr31 & FPU_CSR_DIV_X)
743 info.si_code = FPE_FLTDIV;
744 else if (fcr31 & FPU_CSR_OVF_X)
745 info.si_code = FPE_FLTOVF;
746 else if (fcr31 & FPU_CSR_UDF_X)
747 info.si_code = FPE_FLTUND;
748 else if (fcr31 & FPU_CSR_INE_X)
749 info.si_code = FPE_FLTRES;
751 info.si_code = __SI_FAULT;
752 info.si_signo = SIGFPE;
754 info.si_addr = (void __user *) regs->cp0_epc;
755 force_sig_info(SIGFPE, &info, current);
758 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
764 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
765 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
767 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
769 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
773 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
774 * insns, even for trap and break codes that indicate arithmetic
775 * failures. Weird ...
776 * But should we continue the brokenness??? --macro
781 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
782 die_if_kernel(b, regs);
783 if (code == BRK_DIVZERO)
784 info.si_code = FPE_INTDIV;
786 info.si_code = FPE_INTOVF;
787 info.si_signo = SIGFPE;
789 info.si_addr = (void __user *) regs->cp0_epc;
790 force_sig_info(SIGFPE, &info, current);
793 die_if_kernel("Kernel bug detected", regs);
794 force_sig(SIGTRAP, current);
798 * Address errors may be deliberately induced by the FPU
799 * emulator to retake control of the CPU after executing the
800 * instruction in the delay slot of an emulated branch.
802 * Terminate if exception was recognized as a delay slot return
803 * otherwise handle as normal.
805 if (do_dsemulret(regs))
808 die_if_kernel("Math emu break/trap", regs);
809 force_sig(SIGTRAP, current);
812 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
813 die_if_kernel(b, regs);
814 force_sig(SIGTRAP, current);
818 asmlinkage void do_bp(struct pt_regs *regs)
820 unsigned int opcode, bcode;
822 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
826 * There is the ancient bug in the MIPS assemblers that the break
827 * code starts left to bit 16 instead to bit 6 in the opcode.
828 * Gas is bug-compatible, but not always, grrr...
829 * We handle both cases with a simple heuristics. --macro
831 bcode = ((opcode >> 6) & ((1 << 20) - 1));
832 if (bcode >= (1 << 10))
836 * notify the kprobe handlers, if instruction is likely to
841 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
845 case BRK_KPROBE_SSTEPBP:
846 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
854 do_trap_or_bp(regs, bcode, "Break");
858 force_sig(SIGSEGV, current);
861 asmlinkage void do_tr(struct pt_regs *regs)
863 unsigned int opcode, tcode = 0;
865 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
868 /* Immediate versions don't provide a code. */
869 if (!(opcode & OPCODE))
870 tcode = ((opcode >> 6) & ((1 << 10) - 1));
872 do_trap_or_bp(regs, tcode, "Trap");
876 force_sig(SIGSEGV, current);
879 asmlinkage void do_ri(struct pt_regs *regs)
881 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
882 unsigned long old_epc = regs->cp0_epc;
883 unsigned int opcode = 0;
886 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
890 die_if_kernel("Reserved instruction in kernel code", regs);
892 if (unlikely(compute_return_epc(regs) < 0))
895 if (unlikely(get_user(opcode, epc) < 0))
898 if (!cpu_has_llsc && status < 0)
899 status = simulate_llsc(regs, opcode);
902 status = simulate_rdhwr(regs, opcode);
905 status = simulate_sync(regs, opcode);
910 if (unlikely(status > 0)) {
911 regs->cp0_epc = old_epc; /* Undo skip-over. */
912 force_sig(status, current);
917 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
918 * emulated more than some threshold number of instructions, force migration to
919 * a "CPU" that has FP support.
921 static void mt_ase_fp_affinity(void)
923 #ifdef CONFIG_MIPS_MT_FPAFF
924 if (mt_fpemul_threshold > 0 &&
925 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
927 * If there's no FPU present, or if the application has already
928 * restricted the allowed set to exclude any CPUs with FPUs,
929 * we'll skip the procedure.
931 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
934 current->thread.user_cpus_allowed
935 = current->cpus_allowed;
936 cpus_and(tmask, current->cpus_allowed,
938 set_cpus_allowed_ptr(current, &tmask);
939 set_thread_flag(TIF_FPUBOUND);
942 #endif /* CONFIG_MIPS_MT_FPAFF */
946 * No lock; only written during early bootup by CPU 0.
948 static RAW_NOTIFIER_HEAD(cu2_chain);
950 int __ref register_cu2_notifier(struct notifier_block *nb)
952 return raw_notifier_chain_register(&cu2_chain, nb);
955 int cu2_notifier_call_chain(unsigned long val, void *v)
957 return raw_notifier_call_chain(&cu2_chain, val, v);
960 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
963 struct pt_regs *regs = data;
967 die_if_kernel("Unhandled kernel unaligned access or invalid "
968 "instruction", regs);
972 force_sig(SIGILL, current);
978 asmlinkage void do_cpu(struct pt_regs *regs)
980 unsigned int __user *epc;
981 unsigned long old_epc;
985 unsigned long __maybe_unused flags;
987 die_if_kernel("do_cpu invoked from kernel context!", regs);
989 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
993 epc = (unsigned int __user *)exception_epc(regs);
994 old_epc = regs->cp0_epc;
998 if (unlikely(compute_return_epc(regs) < 0))
1001 if (unlikely(get_user(opcode, epc) < 0))
1004 if (!cpu_has_llsc && status < 0)
1005 status = simulate_llsc(regs, opcode);
1008 status = simulate_rdhwr(regs, opcode);
1013 if (unlikely(status > 0)) {
1014 regs->cp0_epc = old_epc; /* Undo skip-over. */
1015 force_sig(status, current);
1021 if (used_math()) /* Using the FPU again. */
1023 else { /* First time FPU user. */
1028 if (!raw_cpu_has_fpu) {
1030 void __user *fault_addr = NULL;
1031 sig = fpu_emulator_cop1Handler(regs,
1032 ¤t->thread.fpu,
1034 if (!process_fpemu_return(sig, fault_addr))
1035 mt_ase_fp_affinity();
1041 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1048 force_sig(SIGILL, current);
1051 asmlinkage void do_mdmx(struct pt_regs *regs)
1053 force_sig(SIGILL, current);
1057 * Called with interrupts disabled.
1059 asmlinkage void do_watch(struct pt_regs *regs)
1064 * Clear WP (bit 22) bit of cause register so we don't loop
1067 cause = read_c0_cause();
1068 cause &= ~(1 << 22);
1069 write_c0_cause(cause);
1072 * If the current thread has the watch registers loaded, save
1073 * their values and send SIGTRAP. Otherwise another thread
1074 * left the registers set, clear them and continue.
1076 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1077 mips_read_watch_registers();
1079 force_sig(SIGTRAP, current);
1081 mips_clear_watch_registers();
1086 asmlinkage void do_mcheck(struct pt_regs *regs)
1088 const int field = 2 * sizeof(unsigned long);
1089 int multi_match = regs->cp0_status & ST0_TS;
1094 printk("Index : %0x\n", read_c0_index());
1095 printk("Pagemask: %0x\n", read_c0_pagemask());
1096 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1097 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1098 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1103 show_code((unsigned int __user *) regs->cp0_epc);
1106 * Some chips may have other causes of machine check (e.g. SB1
1109 panic("Caught Machine Check exception - %scaused by multiple "
1110 "matching entries in the TLB.",
1111 (multi_match) ? "" : "not ");
1114 asmlinkage void do_mt(struct pt_regs *regs)
1118 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1119 >> VPECONTROL_EXCPT_SHIFT;
1122 printk(KERN_DEBUG "Thread Underflow\n");
1125 printk(KERN_DEBUG "Thread Overflow\n");
1128 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1131 printk(KERN_DEBUG "Gating Storage Exception\n");
1134 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1137 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1140 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1144 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1146 force_sig(SIGILL, current);
1150 asmlinkage void do_dsp(struct pt_regs *regs)
1153 panic("Unexpected DSP exception\n");
1155 force_sig(SIGILL, current);
1158 asmlinkage void do_reserved(struct pt_regs *regs)
1161 * Game over - no way to handle this if it ever occurs. Most probably
1162 * caused by a new unknown cpu type or after another deadly
1163 * hard/software error.
1166 panic("Caught reserved exception %ld - should not happen.",
1167 (regs->cp0_cause & 0x7f) >> 2);
1170 static int __initdata l1parity = 1;
1171 static int __init nol1parity(char *s)
1176 __setup("nol1par", nol1parity);
1177 static int __initdata l2parity = 1;
1178 static int __init nol2parity(char *s)
1183 __setup("nol2par", nol2parity);
1186 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1187 * it different ways.
1189 static inline void parity_protection_init(void)
1191 switch (current_cpu_type()) {
1197 #define ERRCTL_PE 0x80000000
1198 #define ERRCTL_L2P 0x00800000
1199 unsigned long errctl;
1200 unsigned int l1parity_present, l2parity_present;
1202 errctl = read_c0_ecc();
1203 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1205 /* probe L1 parity support */
1206 write_c0_ecc(errctl | ERRCTL_PE);
1207 back_to_back_c0_hazard();
1208 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1210 /* probe L2 parity support */
1211 write_c0_ecc(errctl|ERRCTL_L2P);
1212 back_to_back_c0_hazard();
1213 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1215 if (l1parity_present && l2parity_present) {
1217 errctl |= ERRCTL_PE;
1218 if (l1parity ^ l2parity)
1219 errctl |= ERRCTL_L2P;
1220 } else if (l1parity_present) {
1222 errctl |= ERRCTL_PE;
1223 } else if (l2parity_present) {
1225 errctl |= ERRCTL_L2P;
1227 /* No parity available */
1230 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1232 write_c0_ecc(errctl);
1233 back_to_back_c0_hazard();
1234 errctl = read_c0_ecc();
1235 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1237 if (l1parity_present)
1238 printk(KERN_INFO "Cache parity protection %sabled\n",
1239 (errctl & ERRCTL_PE) ? "en" : "dis");
1241 if (l2parity_present) {
1242 if (l1parity_present && l1parity)
1243 errctl ^= ERRCTL_L2P;
1244 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1245 (errctl & ERRCTL_L2P) ? "en" : "dis");
1251 write_c0_ecc(0x80000000);
1252 back_to_back_c0_hazard();
1253 /* Set the PE bit (bit 31) in the c0_errctl register. */
1254 printk(KERN_INFO "Cache parity protection %sabled\n",
1255 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1259 /* Clear the DE bit (bit 16) in the c0_status register. */
1260 printk(KERN_INFO "Enable cache parity protection for "
1261 "MIPS 20KC/25KF CPUs.\n");
1262 clear_c0_status(ST0_DE);
1269 asmlinkage void cache_parity_error(void)
1271 const int field = 2 * sizeof(unsigned long);
1272 unsigned int reg_val;
1274 /* For the moment, report the problem and hang. */
1275 printk("Cache error exception:\n");
1276 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1277 reg_val = read_c0_cacheerr();
1278 printk("c0_cacheerr == %08x\n", reg_val);
1280 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1281 reg_val & (1<<30) ? "secondary" : "primary",
1282 reg_val & (1<<31) ? "data" : "insn");
1283 printk("Error bits: %s%s%s%s%s%s%s\n",
1284 reg_val & (1<<29) ? "ED " : "",
1285 reg_val & (1<<28) ? "ET " : "",
1286 reg_val & (1<<26) ? "EE " : "",
1287 reg_val & (1<<25) ? "EB " : "",
1288 reg_val & (1<<24) ? "EI " : "",
1289 reg_val & (1<<23) ? "E1 " : "",
1290 reg_val & (1<<22) ? "E0 " : "");
1291 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1293 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1294 if (reg_val & (1<<22))
1295 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1297 if (reg_val & (1<<23))
1298 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1301 panic("Can't handle the cache error!");
1305 * SDBBP EJTAG debug exception handler.
1306 * We skip the instruction and return to the next instruction.
1308 void ejtag_exception_handler(struct pt_regs *regs)
1310 const int field = 2 * sizeof(unsigned long);
1311 unsigned long depc, old_epc;
1314 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1315 depc = read_c0_depc();
1316 debug = read_c0_debug();
1317 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1318 if (debug & 0x80000000) {
1320 * In branch delay slot.
1321 * We cheat a little bit here and use EPC to calculate the
1322 * debug return address (DEPC). EPC is restored after the
1325 old_epc = regs->cp0_epc;
1326 regs->cp0_epc = depc;
1327 __compute_return_epc(regs);
1328 depc = regs->cp0_epc;
1329 regs->cp0_epc = old_epc;
1332 write_c0_depc(depc);
1335 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1336 write_c0_debug(debug | 0x100);
1341 * NMI exception handler.
1343 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1346 printk("NMI taken!!!!\n");
1350 #define VECTORSPACING 0x100 /* for EI/VI mode */
1352 unsigned long ebase;
1353 unsigned long exception_handlers[32];
1354 unsigned long vi_handlers[64];
1356 void __init *set_except_vector(int n, void *addr)
1358 unsigned long handler = (unsigned long) addr;
1359 unsigned long old_handler = exception_handlers[n];
1361 exception_handlers[n] = handler;
1362 if (n == 0 && cpu_has_divec) {
1363 unsigned long jump_mask = ~((1 << 28) - 1);
1364 u32 *buf = (u32 *)(ebase + 0x200);
1365 unsigned int k0 = 26;
1366 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1367 uasm_i_j(&buf, handler & ~jump_mask);
1370 UASM_i_LA(&buf, k0, handler);
1371 uasm_i_jr(&buf, k0);
1374 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1376 return (void *)old_handler;
1379 static asmlinkage void do_default_vi(void)
1381 show_regs(get_irq_regs());
1382 panic("Caught unexpected vectored interrupt.");
1385 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1387 unsigned long handler;
1388 unsigned long old_handler = vi_handlers[n];
1389 int srssets = current_cpu_data.srsets;
1393 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1396 handler = (unsigned long) do_default_vi;
1399 handler = (unsigned long) addr;
1400 vi_handlers[n] = (unsigned long) addr;
1402 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1405 panic("Shadow register set %d not supported", srs);
1408 if (board_bind_eic_interrupt)
1409 board_bind_eic_interrupt(n, srs);
1410 } else if (cpu_has_vint) {
1411 /* SRSMap is only defined if shadow sets are implemented */
1413 change_c0_srsmap(0xf << n*4, srs << n*4);
1418 * If no shadow set is selected then use the default handler
1419 * that does normal register saving and a standard interrupt exit
1422 extern char except_vec_vi, except_vec_vi_lui;
1423 extern char except_vec_vi_ori, except_vec_vi_end;
1424 extern char rollback_except_vec_vi;
1425 char *vec_start = (cpu_wait == r4k_wait) ?
1426 &rollback_except_vec_vi : &except_vec_vi;
1427 #ifdef CONFIG_MIPS_MT_SMTC
1429 * We need to provide the SMTC vectored interrupt handler
1430 * not only with the address of the handler, but with the
1431 * Status.IM bit to be masked before going there.
1433 extern char except_vec_vi_mori;
1434 const int mori_offset = &except_vec_vi_mori - vec_start;
1435 #endif /* CONFIG_MIPS_MT_SMTC */
1436 const int handler_len = &except_vec_vi_end - vec_start;
1437 const int lui_offset = &except_vec_vi_lui - vec_start;
1438 const int ori_offset = &except_vec_vi_ori - vec_start;
1440 if (handler_len > VECTORSPACING) {
1442 * Sigh... panicing won't help as the console
1443 * is probably not configured :(
1445 panic("VECTORSPACING too small");
1448 memcpy(b, vec_start, handler_len);
1449 #ifdef CONFIG_MIPS_MT_SMTC
1450 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1452 w = (u32 *)(b + mori_offset);
1453 *w = (*w & 0xffff0000) | (0x100 << n);
1454 #endif /* CONFIG_MIPS_MT_SMTC */
1455 w = (u32 *)(b + lui_offset);
1456 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1457 w = (u32 *)(b + ori_offset);
1458 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1459 local_flush_icache_range((unsigned long)b,
1460 (unsigned long)(b+handler_len));
1464 * In other cases jump directly to the interrupt handler
1466 * It is the handlers responsibility to save registers if required
1467 * (eg hi/lo) and return from the exception using "eret"
1470 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1472 local_flush_icache_range((unsigned long)b,
1473 (unsigned long)(b+8));
1476 return (void *)old_handler;
1479 void *set_vi_handler(int n, vi_handler_t addr)
1481 return set_vi_srs_handler(n, addr, 0);
1484 extern void cpu_cache_init(void);
1485 extern void tlb_init(void);
1486 extern void flush_tlb_handlers(void);
1491 int cp0_compare_irq;
1492 int cp0_compare_irq_shift;
1495 * Performance counter IRQ or -1 if shared with timer
1497 int cp0_perfcount_irq;
1498 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1500 static int __cpuinitdata noulri;
1502 static int __init ulri_disable(char *s)
1504 pr_info("Disabling ulri\n");
1509 __setup("noulri", ulri_disable);
1511 void __cpuinit per_cpu_trap_init(void)
1513 unsigned int cpu = smp_processor_id();
1514 unsigned int status_set = ST0_CU0;
1515 unsigned int hwrena = cpu_hwrena_impl_bits;
1516 #ifdef CONFIG_MIPS_MT_SMTC
1517 int secondaryTC = 0;
1518 int bootTC = (cpu == 0);
1521 * Only do per_cpu_trap_init() for first TC of Each VPE.
1522 * Note that this hack assumes that the SMTC init code
1523 * assigns TCs consecutively and in ascending order.
1526 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1527 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1529 #endif /* CONFIG_MIPS_MT_SMTC */
1532 * Disable coprocessors and select 32-bit or 64-bit addressing
1533 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1534 * flag that some firmware may have left set and the TS bit (for
1535 * IP27). Set XX for ISA IV code to work.
1538 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1540 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1541 status_set |= ST0_XX;
1543 status_set |= ST0_MX;
1545 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1548 if (cpu_has_mips_r2)
1549 hwrena |= 0x0000000f;
1551 if (!noulri && cpu_has_userlocal)
1552 hwrena |= (1 << 29);
1555 write_c0_hwrena(hwrena);
1557 #ifdef CONFIG_MIPS_MT_SMTC
1559 #endif /* CONFIG_MIPS_MT_SMTC */
1561 if (cpu_has_veic || cpu_has_vint) {
1562 unsigned long sr = set_c0_status(ST0_BEV);
1563 write_c0_ebase(ebase);
1564 write_c0_status(sr);
1565 /* Setting vector spacing enables EI/VI mode */
1566 change_c0_intctl(0x3e0, VECTORSPACING);
1568 if (cpu_has_divec) {
1569 if (cpu_has_mipsmt) {
1570 unsigned int vpflags = dvpe();
1571 set_c0_cause(CAUSEF_IV);
1574 set_c0_cause(CAUSEF_IV);
1578 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1580 * o read IntCtl.IPTI to determine the timer interrupt
1581 * o read IntCtl.IPPCI to determine the performance counter interrupt
1583 if (cpu_has_mips_r2) {
1584 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1585 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1586 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1587 if (cp0_perfcount_irq == cp0_compare_irq)
1588 cp0_perfcount_irq = -1;
1590 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1591 cp0_compare_irq_shift = cp0_compare_irq;
1592 cp0_perfcount_irq = -1;
1595 #ifdef CONFIG_MIPS_MT_SMTC
1597 #endif /* CONFIG_MIPS_MT_SMTC */
1599 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1601 atomic_inc(&init_mm.mm_count);
1602 current->active_mm = &init_mm;
1603 BUG_ON(current->mm);
1604 enter_lazy_tlb(&init_mm, current);
1606 #ifdef CONFIG_MIPS_MT_SMTC
1608 #endif /* CONFIG_MIPS_MT_SMTC */
1611 #ifdef CONFIG_MIPS_MT_SMTC
1612 } else if (!secondaryTC) {
1614 * First TC in non-boot VPE must do subset of tlb_init()
1615 * for MMU countrol registers.
1617 write_c0_pagemask(PM_DEFAULT_MASK);
1620 #endif /* CONFIG_MIPS_MT_SMTC */
1621 TLBMISS_HANDLER_SETUP();
1624 /* Install CPU exception handler */
1625 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1627 memcpy((void *)(ebase + offset), addr, size);
1628 local_flush_icache_range(ebase + offset, ebase + offset + size);
1631 static char panic_null_cerr[] __cpuinitdata =
1632 "Trying to set NULL cache error exception handler";
1635 * Install uncached CPU exception handler.
1636 * This is suitable only for the cache error exception which is the only
1637 * exception handler that is being run uncached.
1639 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1642 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1645 panic(panic_null_cerr);
1647 memcpy((void *)(uncached_ebase + offset), addr, size);
1650 static int __initdata rdhwr_noopt;
1651 static int __init set_rdhwr_noopt(char *str)
1657 __setup("rdhwr_noopt", set_rdhwr_noopt);
1659 void __init trap_init(void)
1661 extern char except_vec3_generic, except_vec3_r4000;
1662 extern char except_vec4;
1667 rollback = (cpu_wait == r4k_wait);
1669 #if defined(CONFIG_KGDB)
1670 if (kgdb_early_setup)
1671 return; /* Already done */
1674 if (cpu_has_veic || cpu_has_vint) {
1675 unsigned long size = 0x200 + VECTORSPACING*64;
1676 ebase = (unsigned long)
1677 __alloc_bootmem(size, 1 << fls(size), 0);
1680 if (cpu_has_mips_r2)
1681 ebase += (read_c0_ebase() & 0x3ffff000);
1684 per_cpu_trap_init();
1687 * Copy the generic exception handlers to their final destination.
1688 * This will be overriden later as suitable for a particular
1691 set_handler(0x180, &except_vec3_generic, 0x80);
1694 * Setup default vectors
1696 for (i = 0; i <= 31; i++)
1697 set_except_vector(i, handle_reserved);
1700 * Copy the EJTAG debug exception vector handler code to it's final
1703 if (cpu_has_ejtag && board_ejtag_handler_setup)
1704 board_ejtag_handler_setup();
1707 * Only some CPUs have the watch exceptions.
1710 set_except_vector(23, handle_watch);
1713 * Initialise interrupt handlers
1715 if (cpu_has_veic || cpu_has_vint) {
1716 int nvec = cpu_has_veic ? 64 : 8;
1717 for (i = 0; i < nvec; i++)
1718 set_vi_handler(i, NULL);
1720 else if (cpu_has_divec)
1721 set_handler(0x200, &except_vec4, 0x8);
1724 * Some CPUs can enable/disable for cache parity detection, but does
1725 * it different ways.
1727 parity_protection_init();
1730 * The Data Bus Errors / Instruction Bus Errors are signaled
1731 * by external hardware. Therefore these two exceptions
1732 * may have board specific handlers.
1737 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1738 set_except_vector(1, handle_tlbm);
1739 set_except_vector(2, handle_tlbl);
1740 set_except_vector(3, handle_tlbs);
1742 set_except_vector(4, handle_adel);
1743 set_except_vector(5, handle_ades);
1745 set_except_vector(6, handle_ibe);
1746 set_except_vector(7, handle_dbe);
1748 set_except_vector(8, handle_sys);
1749 set_except_vector(9, handle_bp);
1750 set_except_vector(10, rdhwr_noopt ? handle_ri :
1751 (cpu_has_vtag_icache ?
1752 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1753 set_except_vector(11, handle_cpu);
1754 set_except_vector(12, handle_ov);
1755 set_except_vector(13, handle_tr);
1757 if (current_cpu_type() == CPU_R6000 ||
1758 current_cpu_type() == CPU_R6000A) {
1760 * The R6000 is the only R-series CPU that features a machine
1761 * check exception (similar to the R4000 cache error) and
1762 * unaligned ldc1/sdc1 exception. The handlers have not been
1763 * written yet. Well, anyway there is no R6000 machine on the
1764 * current list of targets for Linux/MIPS.
1765 * (Duh, crap, there is someone with a triple R6k machine)
1767 //set_except_vector(14, handle_mc);
1768 //set_except_vector(15, handle_ndc);
1772 if (board_nmi_handler_setup)
1773 board_nmi_handler_setup();
1775 if (cpu_has_fpu && !cpu_has_nofpuex)
1776 set_except_vector(15, handle_fpe);
1778 set_except_vector(22, handle_mdmx);
1781 set_except_vector(24, handle_mcheck);
1784 set_except_vector(25, handle_mt);
1786 set_except_vector(26, handle_dsp);
1789 /* Special exception: R4[04]00 uses also the divec space. */
1790 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1791 else if (cpu_has_4kex)
1792 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1794 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1796 local_flush_icache_range(ebase, ebase + 0x400);
1797 flush_tlb_handlers();
1799 sort_extable(__start___dbe_table, __stop___dbe_table);
1801 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */