2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/context_tracking.h>
17 #include <linux/kexec.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/spinlock.h>
25 #include <linux/kallsyms.h>
26 #include <linux/bootmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/ptrace.h>
29 #include <linux/kgdb.h>
30 #include <linux/kdebug.h>
31 #include <linux/kprobes.h>
32 #include <linux/notifier.h>
33 #include <linux/kdb.h>
34 #include <linux/irq.h>
35 #include <linux/perf_event.h>
37 #include <asm/bootinfo.h>
38 #include <asm/branch.h>
39 #include <asm/break.h>
42 #include <asm/cpu-type.h>
45 #include <asm/fpu_emulator.h>
47 #include <asm/mipsregs.h>
48 #include <asm/mipsmtregs.h>
49 #include <asm/module.h>
50 #include <asm/pgtable.h>
51 #include <asm/ptrace.h>
52 #include <asm/sections.h>
53 #include <asm/tlbdebug.h>
54 #include <asm/traps.h>
55 #include <asm/uaccess.h>
56 #include <asm/watch.h>
57 #include <asm/mmu_context.h>
58 #include <asm/types.h>
59 #include <asm/stacktrace.h>
62 extern void check_wait(void);
63 extern asmlinkage void rollback_handle_int(void);
64 extern asmlinkage void handle_int(void);
65 extern u32 handle_tlbl[];
66 extern u32 handle_tlbs[];
67 extern u32 handle_tlbm[];
68 extern asmlinkage void handle_adel(void);
69 extern asmlinkage void handle_ades(void);
70 extern asmlinkage void handle_ibe(void);
71 extern asmlinkage void handle_dbe(void);
72 extern asmlinkage void handle_sys(void);
73 extern asmlinkage void handle_bp(void);
74 extern asmlinkage void handle_ri(void);
75 extern asmlinkage void handle_ri_rdhwr_vivt(void);
76 extern asmlinkage void handle_ri_rdhwr(void);
77 extern asmlinkage void handle_cpu(void);
78 extern asmlinkage void handle_ov(void);
79 extern asmlinkage void handle_tr(void);
80 extern asmlinkage void handle_fpe(void);
81 extern asmlinkage void handle_mdmx(void);
82 extern asmlinkage void handle_watch(void);
83 extern asmlinkage void handle_mt(void);
84 extern asmlinkage void handle_dsp(void);
85 extern asmlinkage void handle_mcheck(void);
86 extern asmlinkage void handle_reserved(void);
88 void (*board_be_init)(void);
89 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
90 void (*board_nmi_handler_setup)(void);
91 void (*board_ejtag_handler_setup)(void);
92 void (*board_bind_eic_interrupt)(int irq, int regset);
93 void (*board_ebase_setup)(void);
94 void(*board_cache_error_setup)(void);
96 static void show_raw_backtrace(unsigned long reg29)
98 unsigned long *sp = (unsigned long *)(reg29 & ~3);
101 printk("Call Trace:");
102 #ifdef CONFIG_KALLSYMS
105 while (!kstack_end(sp)) {
106 unsigned long __user *p =
107 (unsigned long __user *)(unsigned long)sp++;
108 if (__get_user(addr, p)) {
109 printk(" (Bad stack address)");
112 if (__kernel_text_address(addr))
118 #ifdef CONFIG_KALLSYMS
120 static int __init set_raw_show_trace(char *str)
125 __setup("raw_show_trace", set_raw_show_trace);
128 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
130 unsigned long sp = regs->regs[29];
131 unsigned long ra = regs->regs[31];
132 unsigned long pc = regs->cp0_epc;
137 if (raw_show_trace || !__kernel_text_address(pc)) {
138 show_raw_backtrace(sp);
141 printk("Call Trace:\n");
144 pc = unwind_stack(task, &sp, pc, &ra);
150 * This routine abuses get_user()/put_user() to reference pointers
151 * with at least a bit of error checking ...
153 static void show_stacktrace(struct task_struct *task,
154 const struct pt_regs *regs)
156 const int field = 2 * sizeof(unsigned long);
159 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
163 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
164 if (i && ((i % (64 / field)) == 0))
171 if (__get_user(stackdata, sp++)) {
172 printk(" (Bad stack address)");
176 printk(" %0*lx", field, stackdata);
180 show_backtrace(task, regs);
183 void show_stack(struct task_struct *task, unsigned long *sp)
187 regs.regs[29] = (unsigned long)sp;
191 if (task && task != current) {
192 regs.regs[29] = task->thread.reg29;
194 regs.cp0_epc = task->thread.reg31;
195 #ifdef CONFIG_KGDB_KDB
196 } else if (atomic_read(&kgdb_active) != -1 &&
198 memcpy(®s, kdb_current_regs, sizeof(regs));
199 #endif /* CONFIG_KGDB_KDB */
201 prepare_frametrace(®s);
204 show_stacktrace(task, ®s);
207 static void show_code(unsigned int __user *pc)
210 unsigned short __user *pc16 = NULL;
214 if ((unsigned long)pc & 1)
215 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
216 for(i = -3 ; i < 6 ; i++) {
218 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
219 printk(" (Bad address in epc)\n");
222 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
226 static void __show_regs(const struct pt_regs *regs)
228 const int field = 2 * sizeof(unsigned long);
229 unsigned int cause = regs->cp0_cause;
232 show_regs_print_info(KERN_DEFAULT);
235 * Saved main processor registers
237 for (i = 0; i < 32; ) {
241 printk(" %0*lx", field, 0UL);
242 else if (i == 26 || i == 27)
243 printk(" %*s", field, "");
245 printk(" %0*lx", field, regs->regs[i]);
252 #ifdef CONFIG_CPU_HAS_SMARTMIPS
253 printk("Acx : %0*lx\n", field, regs->acx);
255 printk("Hi : %0*lx\n", field, regs->hi);
256 printk("Lo : %0*lx\n", field, regs->lo);
259 * Saved cp0 registers
261 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
262 (void *) regs->cp0_epc);
263 printk(" %s\n", print_tainted());
264 printk("ra : %0*lx %pS\n", field, regs->regs[31],
265 (void *) regs->regs[31]);
267 printk("Status: %08x ", (uint32_t) regs->cp0_status);
270 if (regs->cp0_status & ST0_KUO)
272 if (regs->cp0_status & ST0_IEO)
274 if (regs->cp0_status & ST0_KUP)
276 if (regs->cp0_status & ST0_IEP)
278 if (regs->cp0_status & ST0_KUC)
280 if (regs->cp0_status & ST0_IEC)
282 } else if (cpu_has_4kex) {
283 if (regs->cp0_status & ST0_KX)
285 if (regs->cp0_status & ST0_SX)
287 if (regs->cp0_status & ST0_UX)
289 switch (regs->cp0_status & ST0_KSU) {
294 printk("SUPERVISOR ");
303 if (regs->cp0_status & ST0_ERL)
305 if (regs->cp0_status & ST0_EXL)
307 if (regs->cp0_status & ST0_IE)
312 printk("Cause : %08x\n", cause);
314 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
315 if (1 <= cause && cause <= 5)
316 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
318 printk("PrId : %08x (%s)\n", read_c0_prid(),
323 * FIXME: really the generic show_regs should take a const pointer argument.
325 void show_regs(struct pt_regs *regs)
327 __show_regs((struct pt_regs *)regs);
330 void show_registers(struct pt_regs *regs)
332 const int field = 2 * sizeof(unsigned long);
333 mm_segment_t old_fs = get_fs();
337 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
338 current->comm, current->pid, current_thread_info(), current,
339 field, current_thread_info()->tp_value);
340 if (cpu_has_userlocal) {
343 tls = read_c0_userlocal();
344 if (tls != current_thread_info()->tp_value)
345 printk("*HwTLS: %0*lx\n", field, tls);
348 if (!user_mode(regs))
349 /* Necessary for getting the correct stack content */
351 show_stacktrace(current, regs);
352 show_code((unsigned int __user *) regs->cp0_epc);
357 static int regs_to_trapnr(struct pt_regs *regs)
359 return (regs->cp0_cause >> 2) & 0x1f;
362 static DEFINE_RAW_SPINLOCK(die_lock);
364 void __noreturn die(const char *str, struct pt_regs *regs)
366 static int die_counter;
368 #ifdef CONFIG_MIPS_MT_SMTC
369 unsigned long dvpret;
370 #endif /* CONFIG_MIPS_MT_SMTC */
374 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
375 SIGSEGV) == NOTIFY_STOP)
379 raw_spin_lock_irq(&die_lock);
380 #ifdef CONFIG_MIPS_MT_SMTC
382 #endif /* CONFIG_MIPS_MT_SMTC */
384 #ifdef CONFIG_MIPS_MT_SMTC
385 mips_mt_regdump(dvpret);
386 #endif /* CONFIG_MIPS_MT_SMTC */
388 printk("%s[#%d]:\n", str, ++die_counter);
389 show_registers(regs);
390 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
391 raw_spin_unlock_irq(&die_lock);
396 panic("Fatal exception in interrupt");
399 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
401 panic("Fatal exception");
404 if (regs && kexec_should_crash(current))
410 extern struct exception_table_entry __start___dbe_table[];
411 extern struct exception_table_entry __stop___dbe_table[];
414 " .section __dbe_table, \"a\"\n"
417 /* Given an address, look for it in the exception tables. */
418 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
420 const struct exception_table_entry *e;
422 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
424 e = search_module_dbetables(addr);
428 asmlinkage void do_be(struct pt_regs *regs)
430 const int field = 2 * sizeof(unsigned long);
431 const struct exception_table_entry *fixup = NULL;
432 int data = regs->cp0_cause & 4;
433 int action = MIPS_BE_FATAL;
434 enum ctx_state prev_state;
436 prev_state = exception_enter();
437 /* XXX For now. Fixme, this searches the wrong table ... */
438 if (data && !user_mode(regs))
439 fixup = search_dbe_tables(exception_epc(regs));
442 action = MIPS_BE_FIXUP;
444 if (board_be_handler)
445 action = board_be_handler(regs, fixup != NULL);
448 case MIPS_BE_DISCARD:
452 regs->cp0_epc = fixup->nextinsn;
461 * Assume it would be too dangerous to continue ...
463 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
464 data ? "Data" : "Instruction",
465 field, regs->cp0_epc, field, regs->regs[31]);
466 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
467 SIGBUS) == NOTIFY_STOP)
470 die_if_kernel("Oops", regs);
471 force_sig(SIGBUS, current);
474 exception_exit(prev_state);
478 * ll/sc, rdhwr, sync emulation
481 #define OPCODE 0xfc000000
482 #define BASE 0x03e00000
483 #define RT 0x001f0000
484 #define OFFSET 0x0000ffff
485 #define LL 0xc0000000
486 #define SC 0xe0000000
487 #define SPEC0 0x00000000
488 #define SPEC3 0x7c000000
489 #define RD 0x0000f800
490 #define FUNC 0x0000003f
491 #define SYNC 0x0000000f
492 #define RDHWR 0x0000003b
494 /* microMIPS definitions */
495 #define MM_POOL32A_FUNC 0xfc00ffff
496 #define MM_RDHWR 0x00006b3c
497 #define MM_RS 0x001f0000
498 #define MM_RT 0x03e00000
501 * The ll_bit is cleared by r*_switch.S
505 struct task_struct *ll_task;
507 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
509 unsigned long value, __user *vaddr;
513 * analyse the ll instruction that just caused a ri exception
514 * and put the referenced address to addr.
517 /* sign extend offset */
518 offset = opcode & OFFSET;
522 vaddr = (unsigned long __user *)
523 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
525 if ((unsigned long)vaddr & 3)
527 if (get_user(value, vaddr))
532 if (ll_task == NULL || ll_task == current) {
541 regs->regs[(opcode & RT) >> 16] = value;
546 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
548 unsigned long __user *vaddr;
553 * analyse the sc instruction that just caused a ri exception
554 * and put the referenced address to addr.
557 /* sign extend offset */
558 offset = opcode & OFFSET;
562 vaddr = (unsigned long __user *)
563 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
564 reg = (opcode & RT) >> 16;
566 if ((unsigned long)vaddr & 3)
571 if (ll_bit == 0 || ll_task != current) {
579 if (put_user(regs->regs[reg], vaddr))
588 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
589 * opcodes are supposed to result in coprocessor unusable exceptions if
590 * executed on ll/sc-less processors. That's the theory. In practice a
591 * few processors such as NEC's VR4100 throw reserved instruction exceptions
592 * instead, so we're doing the emulation thing in both exception handlers.
594 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
596 if ((opcode & OPCODE) == LL) {
597 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
599 return simulate_ll(regs, opcode);
601 if ((opcode & OPCODE) == SC) {
602 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
604 return simulate_sc(regs, opcode);
607 return -1; /* Must be something else ... */
611 * Simulate trapping 'rdhwr' instructions to provide user accessible
612 * registers not implemented in hardware.
614 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
616 struct thread_info *ti = task_thread_info(current);
618 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
621 case 0: /* CPU number */
622 regs->regs[rt] = smp_processor_id();
624 case 1: /* SYNCI length */
625 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
626 current_cpu_data.icache.linesz);
628 case 2: /* Read count register */
629 regs->regs[rt] = read_c0_count();
631 case 3: /* Count register resolution */
632 switch (current_cpu_type()) {
642 regs->regs[rt] = ti->tp_value;
649 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
651 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
652 int rd = (opcode & RD) >> 11;
653 int rt = (opcode & RT) >> 16;
655 simulate_rdhwr(regs, rd, rt);
663 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
665 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
666 int rd = (opcode & MM_RS) >> 16;
667 int rt = (opcode & MM_RT) >> 21;
668 simulate_rdhwr(regs, rd, rt);
676 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
678 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
679 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
684 return -1; /* Must be something else ... */
687 asmlinkage void do_ov(struct pt_regs *regs)
689 enum ctx_state prev_state;
692 prev_state = exception_enter();
693 die_if_kernel("Integer overflow", regs);
695 info.si_code = FPE_INTOVF;
696 info.si_signo = SIGFPE;
698 info.si_addr = (void __user *) regs->cp0_epc;
699 force_sig_info(SIGFPE, &info, current);
700 exception_exit(prev_state);
703 int process_fpemu_return(int sig, void __user *fault_addr)
705 if (sig == SIGSEGV || sig == SIGBUS) {
706 struct siginfo si = {0};
707 si.si_addr = fault_addr;
709 if (sig == SIGSEGV) {
710 if (find_vma(current->mm, (unsigned long)fault_addr))
711 si.si_code = SEGV_ACCERR;
713 si.si_code = SEGV_MAPERR;
715 si.si_code = BUS_ADRERR;
717 force_sig_info(sig, &si, current);
720 force_sig(sig, current);
728 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
730 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
732 enum ctx_state prev_state;
733 siginfo_t info = {0};
735 prev_state = exception_enter();
736 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
737 SIGFPE) == NOTIFY_STOP)
739 die_if_kernel("FP exception in kernel code", regs);
741 if (fcr31 & FPU_CSR_UNI_X) {
743 void __user *fault_addr = NULL;
746 * Unimplemented operation exception. If we've got the full
747 * software emulator on-board, let's use it...
749 * Force FPU to dump state into task/thread context. We're
750 * moving a lot of data here for what is probably a single
751 * instruction, but the alternative is to pre-decode the FP
752 * register operands before invoking the emulator, which seems
753 * a bit extreme for what should be an infrequent event.
755 /* Ensure 'resume' not overwrite saved fp context again. */
758 /* Run the emulator */
759 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
763 * We can't allow the emulated instruction to leave any of
764 * the cause bit set in $fcr31.
766 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
768 /* Restore the hardware register state */
769 own_fpu(1); /* Using the FPU again. */
771 /* If something went wrong, signal */
772 process_fpemu_return(sig, fault_addr);
775 } else if (fcr31 & FPU_CSR_INV_X)
776 info.si_code = FPE_FLTINV;
777 else if (fcr31 & FPU_CSR_DIV_X)
778 info.si_code = FPE_FLTDIV;
779 else if (fcr31 & FPU_CSR_OVF_X)
780 info.si_code = FPE_FLTOVF;
781 else if (fcr31 & FPU_CSR_UDF_X)
782 info.si_code = FPE_FLTUND;
783 else if (fcr31 & FPU_CSR_INE_X)
784 info.si_code = FPE_FLTRES;
786 info.si_code = __SI_FAULT;
787 info.si_signo = SIGFPE;
789 info.si_addr = (void __user *) regs->cp0_epc;
790 force_sig_info(SIGFPE, &info, current);
793 exception_exit(prev_state);
796 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
802 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
803 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
805 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
807 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
808 SIGTRAP) == NOTIFY_STOP)
812 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
813 * insns, even for trap and break codes that indicate arithmetic
814 * failures. Weird ...
815 * But should we continue the brokenness??? --macro
820 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
821 die_if_kernel(b, regs);
822 if (code == BRK_DIVZERO)
823 info.si_code = FPE_INTDIV;
825 info.si_code = FPE_INTOVF;
826 info.si_signo = SIGFPE;
828 info.si_addr = (void __user *) regs->cp0_epc;
829 force_sig_info(SIGFPE, &info, current);
832 die_if_kernel("Kernel bug detected", regs);
833 force_sig(SIGTRAP, current);
837 * Address errors may be deliberately induced by the FPU
838 * emulator to retake control of the CPU after executing the
839 * instruction in the delay slot of an emulated branch.
841 * Terminate if exception was recognized as a delay slot return
842 * otherwise handle as normal.
844 if (do_dsemulret(regs))
847 die_if_kernel("Math emu break/trap", regs);
848 force_sig(SIGTRAP, current);
851 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
852 die_if_kernel(b, regs);
853 force_sig(SIGTRAP, current);
857 asmlinkage void do_bp(struct pt_regs *regs)
859 unsigned int opcode, bcode;
860 enum ctx_state prev_state;
864 prev_state = exception_enter();
865 if (get_isa16_mode(regs->cp0_epc)) {
867 epc = exception_epc(regs);
869 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
870 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
872 opcode = (instr[0] << 16) | instr[1];
875 if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
877 bcode = (instr[0] >> 6) & 0x3f;
878 do_trap_or_bp(regs, bcode, "Break");
882 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
887 * There is the ancient bug in the MIPS assemblers that the break
888 * code starts left to bit 16 instead to bit 6 in the opcode.
889 * Gas is bug-compatible, but not always, grrr...
890 * We handle both cases with a simple heuristics. --macro
892 bcode = ((opcode >> 6) & ((1 << 20) - 1));
893 if (bcode >= (1 << 10))
897 * notify the kprobe handlers, if instruction is likely to
902 if (notify_die(DIE_BREAK, "debug", regs, bcode,
903 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
907 case BRK_KPROBE_SSTEPBP:
908 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
909 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
917 do_trap_or_bp(regs, bcode, "Break");
920 exception_exit(prev_state);
924 force_sig(SIGSEGV, current);
928 asmlinkage void do_tr(struct pt_regs *regs)
930 u32 opcode, tcode = 0;
931 enum ctx_state prev_state;
933 unsigned long epc = msk_isa16_mode(exception_epc(regs));
935 prev_state = exception_enter();
936 if (get_isa16_mode(regs->cp0_epc)) {
937 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
938 __get_user(instr[1], (u16 __user *)(epc + 2)))
940 opcode = (instr[0] << 16) | instr[1];
941 /* Immediate versions don't provide a code. */
942 if (!(opcode & OPCODE))
943 tcode = (opcode >> 12) & ((1 << 4) - 1);
945 if (__get_user(opcode, (u32 __user *)epc))
947 /* Immediate versions don't provide a code. */
948 if (!(opcode & OPCODE))
949 tcode = (opcode >> 6) & ((1 << 10) - 1);
952 do_trap_or_bp(regs, tcode, "Trap");
955 exception_exit(prev_state);
959 force_sig(SIGSEGV, current);
963 asmlinkage void do_ri(struct pt_regs *regs)
965 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
966 unsigned long old_epc = regs->cp0_epc;
967 unsigned long old31 = regs->regs[31];
968 enum ctx_state prev_state;
969 unsigned int opcode = 0;
972 prev_state = exception_enter();
973 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
974 SIGILL) == NOTIFY_STOP)
977 die_if_kernel("Reserved instruction in kernel code", regs);
979 if (unlikely(compute_return_epc(regs) < 0))
982 if (get_isa16_mode(regs->cp0_epc)) {
983 unsigned short mmop[2] = { 0 };
985 if (unlikely(get_user(mmop[0], epc) < 0))
987 if (unlikely(get_user(mmop[1], epc) < 0))
989 opcode = (mmop[0] << 16) | mmop[1];
992 status = simulate_rdhwr_mm(regs, opcode);
994 if (unlikely(get_user(opcode, epc) < 0))
997 if (!cpu_has_llsc && status < 0)
998 status = simulate_llsc(regs, opcode);
1001 status = simulate_rdhwr_normal(regs, opcode);
1004 status = simulate_sync(regs, opcode);
1010 if (unlikely(status > 0)) {
1011 regs->cp0_epc = old_epc; /* Undo skip-over. */
1012 regs->regs[31] = old31;
1013 force_sig(status, current);
1017 exception_exit(prev_state);
1021 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1022 * emulated more than some threshold number of instructions, force migration to
1023 * a "CPU" that has FP support.
1025 static void mt_ase_fp_affinity(void)
1027 #ifdef CONFIG_MIPS_MT_FPAFF
1028 if (mt_fpemul_threshold > 0 &&
1029 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1031 * If there's no FPU present, or if the application has already
1032 * restricted the allowed set to exclude any CPUs with FPUs,
1033 * we'll skip the procedure.
1035 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1038 current->thread.user_cpus_allowed
1039 = current->cpus_allowed;
1040 cpus_and(tmask, current->cpus_allowed,
1042 set_cpus_allowed_ptr(current, &tmask);
1043 set_thread_flag(TIF_FPUBOUND);
1046 #endif /* CONFIG_MIPS_MT_FPAFF */
1050 * No lock; only written during early bootup by CPU 0.
1052 static RAW_NOTIFIER_HEAD(cu2_chain);
1054 int __ref register_cu2_notifier(struct notifier_block *nb)
1056 return raw_notifier_chain_register(&cu2_chain, nb);
1059 int cu2_notifier_call_chain(unsigned long val, void *v)
1061 return raw_notifier_call_chain(&cu2_chain, val, v);
1064 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1067 struct pt_regs *regs = data;
1069 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1070 "instruction", regs);
1071 force_sig(SIGILL, current);
1076 asmlinkage void do_cpu(struct pt_regs *regs)
1078 enum ctx_state prev_state;
1079 unsigned int __user *epc;
1080 unsigned long old_epc, old31;
1081 unsigned int opcode;
1084 unsigned long __maybe_unused flags;
1086 prev_state = exception_enter();
1087 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1090 die_if_kernel("do_cpu invoked from kernel context!", regs);
1094 epc = (unsigned int __user *)exception_epc(regs);
1095 old_epc = regs->cp0_epc;
1096 old31 = regs->regs[31];
1100 if (unlikely(compute_return_epc(regs) < 0))
1103 if (get_isa16_mode(regs->cp0_epc)) {
1104 unsigned short mmop[2] = { 0 };
1106 if (unlikely(get_user(mmop[0], epc) < 0))
1108 if (unlikely(get_user(mmop[1], epc) < 0))
1110 opcode = (mmop[0] << 16) | mmop[1];
1113 status = simulate_rdhwr_mm(regs, opcode);
1115 if (unlikely(get_user(opcode, epc) < 0))
1118 if (!cpu_has_llsc && status < 0)
1119 status = simulate_llsc(regs, opcode);
1122 status = simulate_rdhwr_normal(regs, opcode);
1128 if (unlikely(status > 0)) {
1129 regs->cp0_epc = old_epc; /* Undo skip-over. */
1130 regs->regs[31] = old31;
1131 force_sig(status, current);
1138 * Old (MIPS I and MIPS II) processors will set this code
1139 * for COP1X opcode instructions that replaced the original
1140 * COP3 space. We don't limit COP1 space instructions in
1141 * the emulator according to the CPU ISA, so we want to
1142 * treat COP1X instructions consistently regardless of which
1143 * code the CPU chose. Therefore we redirect this trap to
1144 * the FP emulator too.
1146 * Then some newer FPU-less processors use this code
1147 * erroneously too, so they are covered by this choice
1150 if (raw_cpu_has_fpu)
1155 if (used_math()) /* Using the FPU again. */
1157 else { /* First time FPU user. */
1162 if (!raw_cpu_has_fpu) {
1164 void __user *fault_addr = NULL;
1165 sig = fpu_emulator_cop1Handler(regs,
1166 ¤t->thread.fpu,
1168 if (!process_fpemu_return(sig, fault_addr))
1169 mt_ase_fp_affinity();
1175 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1179 force_sig(SIGILL, current);
1182 exception_exit(prev_state);
1185 asmlinkage void do_mdmx(struct pt_regs *regs)
1187 enum ctx_state prev_state;
1189 prev_state = exception_enter();
1190 force_sig(SIGILL, current);
1191 exception_exit(prev_state);
1195 * Called with interrupts disabled.
1197 asmlinkage void do_watch(struct pt_regs *regs)
1199 enum ctx_state prev_state;
1202 prev_state = exception_enter();
1204 * Clear WP (bit 22) bit of cause register so we don't loop
1207 cause = read_c0_cause();
1208 cause &= ~(1 << 22);
1209 write_c0_cause(cause);
1212 * If the current thread has the watch registers loaded, save
1213 * their values and send SIGTRAP. Otherwise another thread
1214 * left the registers set, clear them and continue.
1216 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1217 mips_read_watch_registers();
1219 force_sig(SIGTRAP, current);
1221 mips_clear_watch_registers();
1224 exception_exit(prev_state);
1227 asmlinkage void do_mcheck(struct pt_regs *regs)
1229 const int field = 2 * sizeof(unsigned long);
1230 int multi_match = regs->cp0_status & ST0_TS;
1231 enum ctx_state prev_state;
1233 prev_state = exception_enter();
1237 printk("Index : %0x\n", read_c0_index());
1238 printk("Pagemask: %0x\n", read_c0_pagemask());
1239 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1240 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1241 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1246 show_code((unsigned int __user *) regs->cp0_epc);
1249 * Some chips may have other causes of machine check (e.g. SB1
1252 panic("Caught Machine Check exception - %scaused by multiple "
1253 "matching entries in the TLB.",
1254 (multi_match) ? "" : "not ");
1257 asmlinkage void do_mt(struct pt_regs *regs)
1261 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1262 >> VPECONTROL_EXCPT_SHIFT;
1265 printk(KERN_DEBUG "Thread Underflow\n");
1268 printk(KERN_DEBUG "Thread Overflow\n");
1271 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1274 printk(KERN_DEBUG "Gating Storage Exception\n");
1277 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1280 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1283 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1287 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1289 force_sig(SIGILL, current);
1293 asmlinkage void do_dsp(struct pt_regs *regs)
1296 panic("Unexpected DSP exception");
1298 force_sig(SIGILL, current);
1301 asmlinkage void do_reserved(struct pt_regs *regs)
1304 * Game over - no way to handle this if it ever occurs. Most probably
1305 * caused by a new unknown cpu type or after another deadly
1306 * hard/software error.
1309 panic("Caught reserved exception %ld - should not happen.",
1310 (regs->cp0_cause & 0x7f) >> 2);
1313 static int __initdata l1parity = 1;
1314 static int __init nol1parity(char *s)
1319 __setup("nol1par", nol1parity);
1320 static int __initdata l2parity = 1;
1321 static int __init nol2parity(char *s)
1326 __setup("nol2par", nol2parity);
1329 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1330 * it different ways.
1332 static inline void parity_protection_init(void)
1334 switch (current_cpu_type()) {
1340 #define ERRCTL_PE 0x80000000
1341 #define ERRCTL_L2P 0x00800000
1342 unsigned long errctl;
1343 unsigned int l1parity_present, l2parity_present;
1345 errctl = read_c0_ecc();
1346 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1348 /* probe L1 parity support */
1349 write_c0_ecc(errctl | ERRCTL_PE);
1350 back_to_back_c0_hazard();
1351 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1353 /* probe L2 parity support */
1354 write_c0_ecc(errctl|ERRCTL_L2P);
1355 back_to_back_c0_hazard();
1356 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1358 if (l1parity_present && l2parity_present) {
1360 errctl |= ERRCTL_PE;
1361 if (l1parity ^ l2parity)
1362 errctl |= ERRCTL_L2P;
1363 } else if (l1parity_present) {
1365 errctl |= ERRCTL_PE;
1366 } else if (l2parity_present) {
1368 errctl |= ERRCTL_L2P;
1370 /* No parity available */
1373 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1375 write_c0_ecc(errctl);
1376 back_to_back_c0_hazard();
1377 errctl = read_c0_ecc();
1378 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1380 if (l1parity_present)
1381 printk(KERN_INFO "Cache parity protection %sabled\n",
1382 (errctl & ERRCTL_PE) ? "en" : "dis");
1384 if (l2parity_present) {
1385 if (l1parity_present && l1parity)
1386 errctl ^= ERRCTL_L2P;
1387 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1388 (errctl & ERRCTL_L2P) ? "en" : "dis");
1396 write_c0_ecc(0x80000000);
1397 back_to_back_c0_hazard();
1398 /* Set the PE bit (bit 31) in the c0_errctl register. */
1399 printk(KERN_INFO "Cache parity protection %sabled\n",
1400 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1404 /* Clear the DE bit (bit 16) in the c0_status register. */
1405 printk(KERN_INFO "Enable cache parity protection for "
1406 "MIPS 20KC/25KF CPUs.\n");
1407 clear_c0_status(ST0_DE);
1414 asmlinkage void cache_parity_error(void)
1416 const int field = 2 * sizeof(unsigned long);
1417 unsigned int reg_val;
1419 /* For the moment, report the problem and hang. */
1420 printk("Cache error exception:\n");
1421 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1422 reg_val = read_c0_cacheerr();
1423 printk("c0_cacheerr == %08x\n", reg_val);
1425 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1426 reg_val & (1<<30) ? "secondary" : "primary",
1427 reg_val & (1<<31) ? "data" : "insn");
1428 printk("Error bits: %s%s%s%s%s%s%s\n",
1429 reg_val & (1<<29) ? "ED " : "",
1430 reg_val & (1<<28) ? "ET " : "",
1431 reg_val & (1<<26) ? "EE " : "",
1432 reg_val & (1<<25) ? "EB " : "",
1433 reg_val & (1<<24) ? "EI " : "",
1434 reg_val & (1<<23) ? "E1 " : "",
1435 reg_val & (1<<22) ? "E0 " : "");
1436 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1438 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1439 if (reg_val & (1<<22))
1440 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1442 if (reg_val & (1<<23))
1443 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1446 panic("Can't handle the cache error!");
1450 * SDBBP EJTAG debug exception handler.
1451 * We skip the instruction and return to the next instruction.
1453 void ejtag_exception_handler(struct pt_regs *regs)
1455 const int field = 2 * sizeof(unsigned long);
1456 unsigned long depc, old_epc, old_ra;
1459 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1460 depc = read_c0_depc();
1461 debug = read_c0_debug();
1462 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1463 if (debug & 0x80000000) {
1465 * In branch delay slot.
1466 * We cheat a little bit here and use EPC to calculate the
1467 * debug return address (DEPC). EPC is restored after the
1470 old_epc = regs->cp0_epc;
1471 old_ra = regs->regs[31];
1472 regs->cp0_epc = depc;
1473 compute_return_epc(regs);
1474 depc = regs->cp0_epc;
1475 regs->cp0_epc = old_epc;
1476 regs->regs[31] = old_ra;
1479 write_c0_depc(depc);
1482 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1483 write_c0_debug(debug | 0x100);
1488 * NMI exception handler.
1489 * No lock; only written during early bootup by CPU 0.
1491 static RAW_NOTIFIER_HEAD(nmi_chain);
1493 int register_nmi_notifier(struct notifier_block *nb)
1495 return raw_notifier_chain_register(&nmi_chain, nb);
1498 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1502 raw_notifier_call_chain(&nmi_chain, 0, regs);
1504 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1505 smp_processor_id(), regs->cp0_epc);
1506 regs->cp0_epc = read_c0_errorepc();
1510 #define VECTORSPACING 0x100 /* for EI/VI mode */
1512 unsigned long ebase;
1513 unsigned long exception_handlers[32];
1514 unsigned long vi_handlers[64];
1516 void __init *set_except_vector(int n, void *addr)
1518 unsigned long handler = (unsigned long) addr;
1519 unsigned long old_handler;
1521 #ifdef CONFIG_CPU_MICROMIPS
1523 * Only the TLB handlers are cache aligned with an even
1524 * address. All other handlers are on an odd address and
1525 * require no modification. Otherwise, MIPS32 mode will
1526 * be entered when handling any TLB exceptions. That
1527 * would be bad...since we must stay in microMIPS mode.
1529 if (!(handler & 0x1))
1532 old_handler = xchg(&exception_handlers[n], handler);
1534 if (n == 0 && cpu_has_divec) {
1535 #ifdef CONFIG_CPU_MICROMIPS
1536 unsigned long jump_mask = ~((1 << 27) - 1);
1538 unsigned long jump_mask = ~((1 << 28) - 1);
1540 u32 *buf = (u32 *)(ebase + 0x200);
1541 unsigned int k0 = 26;
1542 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1543 uasm_i_j(&buf, handler & ~jump_mask);
1546 UASM_i_LA(&buf, k0, handler);
1547 uasm_i_jr(&buf, k0);
1550 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1552 return (void *)old_handler;
1555 static void do_default_vi(void)
1557 show_regs(get_irq_regs());
1558 panic("Caught unexpected vectored interrupt.");
1561 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1563 unsigned long handler;
1564 unsigned long old_handler = vi_handlers[n];
1565 int srssets = current_cpu_data.srsets;
1569 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1572 handler = (unsigned long) do_default_vi;
1575 handler = (unsigned long) addr;
1576 vi_handlers[n] = handler;
1578 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1581 panic("Shadow register set %d not supported", srs);
1584 if (board_bind_eic_interrupt)
1585 board_bind_eic_interrupt(n, srs);
1586 } else if (cpu_has_vint) {
1587 /* SRSMap is only defined if shadow sets are implemented */
1589 change_c0_srsmap(0xf << n*4, srs << n*4);
1594 * If no shadow set is selected then use the default handler
1595 * that does normal register saving and standard interrupt exit
1597 extern char except_vec_vi, except_vec_vi_lui;
1598 extern char except_vec_vi_ori, except_vec_vi_end;
1599 extern char rollback_except_vec_vi;
1600 char *vec_start = using_rollback_handler() ?
1601 &rollback_except_vec_vi : &except_vec_vi;
1602 #ifdef CONFIG_MIPS_MT_SMTC
1604 * We need to provide the SMTC vectored interrupt handler
1605 * not only with the address of the handler, but with the
1606 * Status.IM bit to be masked before going there.
1608 extern char except_vec_vi_mori;
1609 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1610 const int mori_offset = &except_vec_vi_mori - vec_start + 2;
1612 const int mori_offset = &except_vec_vi_mori - vec_start;
1614 #endif /* CONFIG_MIPS_MT_SMTC */
1615 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1616 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1617 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1619 const int lui_offset = &except_vec_vi_lui - vec_start;
1620 const int ori_offset = &except_vec_vi_ori - vec_start;
1622 const int handler_len = &except_vec_vi_end - vec_start;
1624 if (handler_len > VECTORSPACING) {
1626 * Sigh... panicing won't help as the console
1627 * is probably not configured :(
1629 panic("VECTORSPACING too small");
1632 set_handler(((unsigned long)b - ebase), vec_start,
1633 #ifdef CONFIG_CPU_MICROMIPS
1638 #ifdef CONFIG_MIPS_MT_SMTC
1639 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1641 h = (u16 *)(b + mori_offset);
1643 #endif /* CONFIG_MIPS_MT_SMTC */
1644 h = (u16 *)(b + lui_offset);
1645 *h = (handler >> 16) & 0xffff;
1646 h = (u16 *)(b + ori_offset);
1647 *h = (handler & 0xffff);
1648 local_flush_icache_range((unsigned long)b,
1649 (unsigned long)(b+handler_len));
1653 * In other cases jump directly to the interrupt handler. It
1654 * is the handler's responsibility to save registers if required
1655 * (eg hi/lo) and return from the exception using "eret".
1661 #ifdef CONFIG_CPU_MICROMIPS
1662 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1664 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1666 h[0] = (insn >> 16) & 0xffff;
1667 h[1] = insn & 0xffff;
1670 local_flush_icache_range((unsigned long)b,
1671 (unsigned long)(b+8));
1674 return (void *)old_handler;
1677 void *set_vi_handler(int n, vi_handler_t addr)
1679 return set_vi_srs_handler(n, addr, 0);
1682 extern void tlb_init(void);
1687 int cp0_compare_irq;
1688 EXPORT_SYMBOL_GPL(cp0_compare_irq);
1689 int cp0_compare_irq_shift;
1692 * Performance counter IRQ or -1 if shared with timer
1694 int cp0_perfcount_irq;
1695 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1699 static int __init ulri_disable(char *s)
1701 pr_info("Disabling ulri\n");
1706 __setup("noulri", ulri_disable);
1708 void per_cpu_trap_init(bool is_boot_cpu)
1710 unsigned int cpu = smp_processor_id();
1711 unsigned int status_set = ST0_CU0;
1712 unsigned int hwrena = cpu_hwrena_impl_bits;
1713 #ifdef CONFIG_MIPS_MT_SMTC
1714 int secondaryTC = 0;
1715 int bootTC = (cpu == 0);
1718 * Only do per_cpu_trap_init() for first TC of Each VPE.
1719 * Note that this hack assumes that the SMTC init code
1720 * assigns TCs consecutively and in ascending order.
1723 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1724 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1726 #endif /* CONFIG_MIPS_MT_SMTC */
1729 * Disable coprocessors and select 32-bit or 64-bit addressing
1730 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1731 * flag that some firmware may have left set and the TS bit (for
1732 * IP27). Set XX for ISA IV code to work.
1735 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1737 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1738 status_set |= ST0_XX;
1740 status_set |= ST0_MX;
1742 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1745 if (cpu_has_mips_r2)
1746 hwrena |= 0x0000000f;
1748 if (!noulri && cpu_has_userlocal)
1749 hwrena |= (1 << 29);
1752 write_c0_hwrena(hwrena);
1754 #ifdef CONFIG_MIPS_MT_SMTC
1756 #endif /* CONFIG_MIPS_MT_SMTC */
1758 if (cpu_has_veic || cpu_has_vint) {
1759 unsigned long sr = set_c0_status(ST0_BEV);
1760 write_c0_ebase(ebase);
1761 write_c0_status(sr);
1762 /* Setting vector spacing enables EI/VI mode */
1763 change_c0_intctl(0x3e0, VECTORSPACING);
1765 if (cpu_has_divec) {
1766 if (cpu_has_mipsmt) {
1767 unsigned int vpflags = dvpe();
1768 set_c0_cause(CAUSEF_IV);
1771 set_c0_cause(CAUSEF_IV);
1775 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1777 * o read IntCtl.IPTI to determine the timer interrupt
1778 * o read IntCtl.IPPCI to determine the performance counter interrupt
1780 if (cpu_has_mips_r2) {
1781 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1782 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1783 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1784 if (cp0_perfcount_irq == cp0_compare_irq)
1785 cp0_perfcount_irq = -1;
1787 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1788 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
1789 cp0_perfcount_irq = -1;
1792 #ifdef CONFIG_MIPS_MT_SMTC
1794 #endif /* CONFIG_MIPS_MT_SMTC */
1796 if (!cpu_data[cpu].asid_cache)
1797 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1799 atomic_inc(&init_mm.mm_count);
1800 current->active_mm = &init_mm;
1801 BUG_ON(current->mm);
1802 enter_lazy_tlb(&init_mm, current);
1804 #ifdef CONFIG_MIPS_MT_SMTC
1806 #endif /* CONFIG_MIPS_MT_SMTC */
1807 /* Boot CPU's cache setup in setup_arch(). */
1811 #ifdef CONFIG_MIPS_MT_SMTC
1812 } else if (!secondaryTC) {
1814 * First TC in non-boot VPE must do subset of tlb_init()
1815 * for MMU countrol registers.
1817 write_c0_pagemask(PM_DEFAULT_MASK);
1820 #endif /* CONFIG_MIPS_MT_SMTC */
1821 TLBMISS_HANDLER_SETUP();
1824 /* Install CPU exception handler */
1825 void set_handler(unsigned long offset, void *addr, unsigned long size)
1827 #ifdef CONFIG_CPU_MICROMIPS
1828 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
1830 memcpy((void *)(ebase + offset), addr, size);
1832 local_flush_icache_range(ebase + offset, ebase + offset + size);
1835 static char panic_null_cerr[] =
1836 "Trying to set NULL cache error exception handler";
1839 * Install uncached CPU exception handler.
1840 * This is suitable only for the cache error exception which is the only
1841 * exception handler that is being run uncached.
1843 void set_uncached_handler(unsigned long offset, void *addr,
1846 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1849 panic(panic_null_cerr);
1851 memcpy((void *)(uncached_ebase + offset), addr, size);
1854 static int __initdata rdhwr_noopt;
1855 static int __init set_rdhwr_noopt(char *str)
1861 __setup("rdhwr_noopt", set_rdhwr_noopt);
1863 void __init trap_init(void)
1865 extern char except_vec3_generic;
1866 extern char except_vec4;
1867 extern char except_vec3_r4000;
1872 #if defined(CONFIG_KGDB)
1873 if (kgdb_early_setup)
1874 return; /* Already done */
1877 if (cpu_has_veic || cpu_has_vint) {
1878 unsigned long size = 0x200 + VECTORSPACING*64;
1879 ebase = (unsigned long)
1880 __alloc_bootmem(size, 1 << fls(size), 0);
1882 #ifdef CONFIG_KVM_GUEST
1883 #define KVM_GUEST_KSEG0 0x40000000
1884 ebase = KVM_GUEST_KSEG0;
1888 if (cpu_has_mips_r2)
1889 ebase += (read_c0_ebase() & 0x3ffff000);
1892 if (cpu_has_mmips) {
1893 unsigned int config3 = read_c0_config3();
1895 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
1896 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
1898 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
1901 if (board_ebase_setup)
1902 board_ebase_setup();
1903 per_cpu_trap_init(true);
1906 * Copy the generic exception handlers to their final destination.
1907 * This will be overriden later as suitable for a particular
1910 set_handler(0x180, &except_vec3_generic, 0x80);
1913 * Setup default vectors
1915 for (i = 0; i <= 31; i++)
1916 set_except_vector(i, handle_reserved);
1919 * Copy the EJTAG debug exception vector handler code to it's final
1922 if (cpu_has_ejtag && board_ejtag_handler_setup)
1923 board_ejtag_handler_setup();
1926 * Only some CPUs have the watch exceptions.
1929 set_except_vector(23, handle_watch);
1932 * Initialise interrupt handlers
1934 if (cpu_has_veic || cpu_has_vint) {
1935 int nvec = cpu_has_veic ? 64 : 8;
1936 for (i = 0; i < nvec; i++)
1937 set_vi_handler(i, NULL);
1939 else if (cpu_has_divec)
1940 set_handler(0x200, &except_vec4, 0x8);
1943 * Some CPUs can enable/disable for cache parity detection, but does
1944 * it different ways.
1946 parity_protection_init();
1949 * The Data Bus Errors / Instruction Bus Errors are signaled
1950 * by external hardware. Therefore these two exceptions
1951 * may have board specific handlers.
1956 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
1958 set_except_vector(1, handle_tlbm);
1959 set_except_vector(2, handle_tlbl);
1960 set_except_vector(3, handle_tlbs);
1962 set_except_vector(4, handle_adel);
1963 set_except_vector(5, handle_ades);
1965 set_except_vector(6, handle_ibe);
1966 set_except_vector(7, handle_dbe);
1968 set_except_vector(8, handle_sys);
1969 set_except_vector(9, handle_bp);
1970 set_except_vector(10, rdhwr_noopt ? handle_ri :
1971 (cpu_has_vtag_icache ?
1972 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1973 set_except_vector(11, handle_cpu);
1974 set_except_vector(12, handle_ov);
1975 set_except_vector(13, handle_tr);
1977 if (current_cpu_type() == CPU_R6000 ||
1978 current_cpu_type() == CPU_R6000A) {
1980 * The R6000 is the only R-series CPU that features a machine
1981 * check exception (similar to the R4000 cache error) and
1982 * unaligned ldc1/sdc1 exception. The handlers have not been
1983 * written yet. Well, anyway there is no R6000 machine on the
1984 * current list of targets for Linux/MIPS.
1985 * (Duh, crap, there is someone with a triple R6k machine)
1987 //set_except_vector(14, handle_mc);
1988 //set_except_vector(15, handle_ndc);
1992 if (board_nmi_handler_setup)
1993 board_nmi_handler_setup();
1995 if (cpu_has_fpu && !cpu_has_nofpuex)
1996 set_except_vector(15, handle_fpe);
1998 set_except_vector(22, handle_mdmx);
2001 set_except_vector(24, handle_mcheck);
2004 set_except_vector(25, handle_mt);
2006 set_except_vector(26, handle_dsp);
2008 if (board_cache_error_setup)
2009 board_cache_error_setup();
2012 /* Special exception: R4[04]00 uses also the divec space. */
2013 set_handler(0x180, &except_vec3_r4000, 0x100);
2014 else if (cpu_has_4kex)
2015 set_handler(0x180, &except_vec3_generic, 0x80);
2017 set_handler(0x080, &except_vec3_generic, 0x80);
2019 local_flush_icache_range(ebase, ebase + 0x400);
2021 sort_extable(__start___dbe_table, __stop___dbe_table);
2023 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */