2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2014 Imagination Technologies Ltd.
12 * This file contains exception handler for address error exception with the
13 * special capability to execute faulting instructions in software. The
14 * handler does not try to handle the case when the program counter points
15 * to an address not aligned to a word boundary.
17 * Putting data to unaligned addresses is a bad practice even on Intel where
18 * only the performance is affected. Much worse is that such code is non-
19 * portable. Due to several programs that die on MIPS due to alignment
20 * problems I decided to implement this handler anyway though I originally
21 * didn't intend to do this at all for user code.
23 * For now I enable fixing of address errors by default to make life easier.
24 * I however intend to disable this somewhen in the future when the alignment
25 * problems with user programs have been fixed. For programmers this is the
28 * Fixing address errors is a per process option. The option is inherited
29 * across fork(2) and execve(2) calls. If you really want to use the
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
33 * #include <sys/sysmips.h>
36 * sysmips(MIPS_FIXADE, x);
39 * The argument x is 0 for disabling software emulation, enabled otherwise.
41 * Below a little program to play around with this feature.
44 * #include <sys/sysmips.h>
47 * unsigned char bar[8];
50 * main(int argc, char *argv[])
52 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
53 * unsigned int *p = (unsigned int *) (x.bar + 3);
57 * sysmips(MIPS_FIXADE, atoi(argv[1]));
59 * printf("*p = %08lx\n", *p);
63 * for(i = 0; i <= 7; i++)
64 * printf("%02x ", x.bar[i]);
68 * Coprocessor loads are not supported; I think this case is unimportant
71 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
72 * exception for the R6000.
73 * A store crossing a page boundary might be executed only partially.
74 * Undo the partial store in this case.
76 #include <linux/context_tracking.h>
78 #include <linux/signal.h>
79 #include <linux/smp.h>
80 #include <linux/sched.h>
81 #include <linux/debugfs.h>
82 #include <linux/perf_event.h>
85 #include <asm/branch.h>
86 #include <asm/byteorder.h>
89 #include <asm/fpu_emulator.h>
91 #include <asm/uaccess.h>
93 #define STR(x) __STR(x)
97 UNALIGNED_ACTION_QUIET,
98 UNALIGNED_ACTION_SIGNAL,
99 UNALIGNED_ACTION_SHOW,
101 #ifdef CONFIG_DEBUG_FS
102 static u32 unaligned_instructions;
103 static u32 unaligned_action;
105 #define unaligned_action UNALIGNED_ACTION_QUIET
107 extern void show_registers(struct pt_regs *regs);
110 #define _LoadHW(addr, value, res, type) \
112 __asm__ __volatile__ (".set\tnoat\n" \
113 "1:\t"type##_lb("%0", "0(%2)")"\n" \
114 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
120 ".section\t.fixup,\"ax\"\n\t" \
121 "4:\tli\t%1, %3\n\t" \
124 ".section\t__ex_table,\"a\"\n\t" \
125 STR(PTR)"\t1b, 4b\n\t" \
126 STR(PTR)"\t2b, 4b\n\t" \
128 : "=&r" (value), "=r" (res) \
129 : "r" (addr), "i" (-EFAULT)); \
132 #ifndef CONFIG_CPU_MIPSR6
133 #define _LoadW(addr, value, res, type) \
135 __asm__ __volatile__ ( \
136 "1:\t"type##_lwl("%0", "(%2)")"\n" \
137 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
141 ".section\t.fixup,\"ax\"\n\t" \
142 "4:\tli\t%1, %3\n\t" \
145 ".section\t__ex_table,\"a\"\n\t" \
146 STR(PTR)"\t1b, 4b\n\t" \
147 STR(PTR)"\t2b, 4b\n\t" \
149 : "=&r" (value), "=r" (res) \
150 : "r" (addr), "i" (-EFAULT)); \
154 /* MIPSR6 has no lwl instruction */
155 #define _LoadW(addr, value, res, type) \
157 __asm__ __volatile__ ( \
160 "1:"type##_lb("%0", "0(%2)")"\n\t" \
161 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
164 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
167 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
174 ".section\t.fixup,\"ax\"\n\t" \
175 "11:\tli\t%1, %3\n\t" \
178 ".section\t__ex_table,\"a\"\n\t" \
179 STR(PTR)"\t1b, 11b\n\t" \
180 STR(PTR)"\t2b, 11b\n\t" \
181 STR(PTR)"\t3b, 11b\n\t" \
182 STR(PTR)"\t4b, 11b\n\t" \
184 : "=&r" (value), "=r" (res) \
185 : "r" (addr), "i" (-EFAULT)); \
188 #endif /* CONFIG_CPU_MIPSR6 */
190 #define _LoadHWU(addr, value, res, type) \
192 __asm__ __volatile__ ( \
194 "1:\t"type##_lbu("%0", "0(%2)")"\n" \
195 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
202 ".section\t.fixup,\"ax\"\n\t" \
203 "4:\tli\t%1, %3\n\t" \
206 ".section\t__ex_table,\"a\"\n\t" \
207 STR(PTR)"\t1b, 4b\n\t" \
208 STR(PTR)"\t2b, 4b\n\t" \
210 : "=&r" (value), "=r" (res) \
211 : "r" (addr), "i" (-EFAULT)); \
214 #ifndef CONFIG_CPU_MIPSR6
215 #define _LoadWU(addr, value, res, type) \
217 __asm__ __volatile__ ( \
218 "1:\t"type##_lwl("%0", "(%2)")"\n" \
219 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
220 "dsll\t%0, %0, 32\n\t" \
221 "dsrl\t%0, %0, 32\n\t" \
225 "\t.section\t.fixup,\"ax\"\n\t" \
226 "4:\tli\t%1, %3\n\t" \
229 ".section\t__ex_table,\"a\"\n\t" \
230 STR(PTR)"\t1b, 4b\n\t" \
231 STR(PTR)"\t2b, 4b\n\t" \
233 : "=&r" (value), "=r" (res) \
234 : "r" (addr), "i" (-EFAULT)); \
237 #define _LoadDW(addr, value, res) \
239 __asm__ __volatile__ ( \
240 "1:\tldl\t%0, (%2)\n" \
241 "2:\tldr\t%0, 7(%2)\n\t" \
245 "\t.section\t.fixup,\"ax\"\n\t" \
246 "4:\tli\t%1, %3\n\t" \
249 ".section\t__ex_table,\"a\"\n\t" \
250 STR(PTR)"\t1b, 4b\n\t" \
251 STR(PTR)"\t2b, 4b\n\t" \
253 : "=&r" (value), "=r" (res) \
254 : "r" (addr), "i" (-EFAULT)); \
258 /* MIPSR6 has not lwl and ldl instructions */
259 #define _LoadWU(addr, value, res, type) \
261 __asm__ __volatile__ ( \
264 "1:"type##_lbu("%0", "0(%2)")"\n\t" \
265 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
268 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
271 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
278 ".section\t.fixup,\"ax\"\n\t" \
279 "11:\tli\t%1, %3\n\t" \
282 ".section\t__ex_table,\"a\"\n\t" \
283 STR(PTR)"\t1b, 11b\n\t" \
284 STR(PTR)"\t2b, 11b\n\t" \
285 STR(PTR)"\t3b, 11b\n\t" \
286 STR(PTR)"\t4b, 11b\n\t" \
288 : "=&r" (value), "=r" (res) \
289 : "r" (addr), "i" (-EFAULT)); \
292 #define _LoadDW(addr, value, res) \
294 __asm__ __volatile__ ( \
297 "1:lb\t%0, 0(%2)\n\t" \
298 "2:lbu\t $1, 1(%2)\n\t" \
299 "dsll\t%0, 0x8\n\t" \
301 "3:lbu\t$1, 2(%2)\n\t" \
302 "dsll\t%0, 0x8\n\t" \
304 "4:lbu\t$1, 3(%2)\n\t" \
305 "dsll\t%0, 0x8\n\t" \
307 "5:lbu\t$1, 4(%2)\n\t" \
308 "dsll\t%0, 0x8\n\t" \
310 "6:lbu\t$1, 5(%2)\n\t" \
311 "dsll\t%0, 0x8\n\t" \
313 "7:lbu\t$1, 6(%2)\n\t" \
314 "dsll\t%0, 0x8\n\t" \
316 "8:lbu\t$1, 7(%2)\n\t" \
317 "dsll\t%0, 0x8\n\t" \
323 ".section\t.fixup,\"ax\"\n\t" \
324 "11:\tli\t%1, %3\n\t" \
327 ".section\t__ex_table,\"a\"\n\t" \
328 STR(PTR)"\t1b, 11b\n\t" \
329 STR(PTR)"\t2b, 11b\n\t" \
330 STR(PTR)"\t3b, 11b\n\t" \
331 STR(PTR)"\t4b, 11b\n\t" \
332 STR(PTR)"\t5b, 11b\n\t" \
333 STR(PTR)"\t6b, 11b\n\t" \
334 STR(PTR)"\t7b, 11b\n\t" \
335 STR(PTR)"\t8b, 11b\n\t" \
337 : "=&r" (value), "=r" (res) \
338 : "r" (addr), "i" (-EFAULT)); \
341 #endif /* CONFIG_CPU_MIPSR6 */
344 #define _StoreHW(addr, value, res, type) \
346 __asm__ __volatile__ ( \
348 "1:\t"type##_sb("%1", "1(%2)")"\n" \
349 "srl\t$1, %1, 0x8\n" \
350 "2:\t"type##_sb("$1", "0(%2)")"\n" \
355 ".section\t.fixup,\"ax\"\n\t" \
356 "4:\tli\t%0, %3\n\t" \
359 ".section\t__ex_table,\"a\"\n\t" \
360 STR(PTR)"\t1b, 4b\n\t" \
361 STR(PTR)"\t2b, 4b\n\t" \
364 : "r" (value), "r" (addr), "i" (-EFAULT));\
367 #ifndef CONFIG_CPU_MIPSR6
368 #define _StoreW(addr, value, res, type) \
370 __asm__ __volatile__ ( \
371 "1:\t"type##_swl("%1", "(%2)")"\n" \
372 "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
376 ".section\t.fixup,\"ax\"\n\t" \
377 "4:\tli\t%0, %3\n\t" \
380 ".section\t__ex_table,\"a\"\n\t" \
381 STR(PTR)"\t1b, 4b\n\t" \
382 STR(PTR)"\t2b, 4b\n\t" \
385 : "r" (value), "r" (addr), "i" (-EFAULT)); \
388 #define _StoreDW(addr, value, res) \
390 __asm__ __volatile__ ( \
391 "1:\tsdl\t%1,(%2)\n" \
392 "2:\tsdr\t%1, 7(%2)\n\t" \
396 ".section\t.fixup,\"ax\"\n\t" \
397 "4:\tli\t%0, %3\n\t" \
400 ".section\t__ex_table,\"a\"\n\t" \
401 STR(PTR)"\t1b, 4b\n\t" \
402 STR(PTR)"\t2b, 4b\n\t" \
405 : "r" (value), "r" (addr), "i" (-EFAULT)); \
409 /* MIPSR6 has no swl and sdl instructions */
410 #define _StoreW(addr, value, res, type) \
412 __asm__ __volatile__ ( \
415 "1:"type##_sb("%1", "3(%2)")"\n\t" \
416 "srl\t$1, %1, 0x8\n\t" \
417 "2:"type##_sb("$1", "2(%2)")"\n\t" \
418 "srl\t$1, $1, 0x8\n\t" \
419 "3:"type##_sb("$1", "1(%2)")"\n\t" \
420 "srl\t$1, $1, 0x8\n\t" \
421 "4:"type##_sb("$1", "0(%2)")"\n\t" \
426 ".section\t.fixup,\"ax\"\n\t" \
427 "11:\tli\t%0, %3\n\t" \
430 ".section\t__ex_table,\"a\"\n\t" \
431 STR(PTR)"\t1b, 11b\n\t" \
432 STR(PTR)"\t2b, 11b\n\t" \
433 STR(PTR)"\t3b, 11b\n\t" \
434 STR(PTR)"\t4b, 11b\n\t" \
437 : "r" (value), "r" (addr), "i" (-EFAULT) \
441 #define _StoreDW(addr, value, res) \
443 __asm__ __volatile__ ( \
446 "1:sb\t%1, 7(%2)\n\t" \
447 "dsrl\t$1, %1, 0x8\n\t" \
448 "2:sb\t$1, 6(%2)\n\t" \
449 "dsrl\t$1, $1, 0x8\n\t" \
450 "3:sb\t$1, 5(%2)\n\t" \
451 "dsrl\t$1, $1, 0x8\n\t" \
452 "4:sb\t$1, 4(%2)\n\t" \
453 "dsrl\t$1, $1, 0x8\n\t" \
454 "5:sb\t$1, 3(%2)\n\t" \
455 "dsrl\t$1, $1, 0x8\n\t" \
456 "6:sb\t$1, 2(%2)\n\t" \
457 "dsrl\t$1, $1, 0x8\n\t" \
458 "7:sb\t$1, 1(%2)\n\t" \
459 "dsrl\t$1, $1, 0x8\n\t" \
460 "8:sb\t$1, 0(%2)\n\t" \
461 "dsrl\t$1, $1, 0x8\n\t" \
466 ".section\t.fixup,\"ax\"\n\t" \
467 "11:\tli\t%0, %3\n\t" \
470 ".section\t__ex_table,\"a\"\n\t" \
471 STR(PTR)"\t1b, 11b\n\t" \
472 STR(PTR)"\t2b, 11b\n\t" \
473 STR(PTR)"\t3b, 11b\n\t" \
474 STR(PTR)"\t4b, 11b\n\t" \
475 STR(PTR)"\t5b, 11b\n\t" \
476 STR(PTR)"\t6b, 11b\n\t" \
477 STR(PTR)"\t7b, 11b\n\t" \
478 STR(PTR)"\t8b, 11b\n\t" \
481 : "r" (value), "r" (addr), "i" (-EFAULT) \
485 #endif /* CONFIG_CPU_MIPSR6 */
487 #else /* __BIG_ENDIAN */
489 #define _LoadHW(addr, value, res, type) \
491 __asm__ __volatile__ (".set\tnoat\n" \
492 "1:\t"type##_lb("%0", "1(%2)")"\n" \
493 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
499 ".section\t.fixup,\"ax\"\n\t" \
500 "4:\tli\t%1, %3\n\t" \
503 ".section\t__ex_table,\"a\"\n\t" \
504 STR(PTR)"\t1b, 4b\n\t" \
505 STR(PTR)"\t2b, 4b\n\t" \
507 : "=&r" (value), "=r" (res) \
508 : "r" (addr), "i" (-EFAULT)); \
511 #ifndef CONFIG_CPU_MIPSR6
512 #define _LoadW(addr, value, res, type) \
514 __asm__ __volatile__ ( \
515 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
516 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
520 ".section\t.fixup,\"ax\"\n\t" \
521 "4:\tli\t%1, %3\n\t" \
524 ".section\t__ex_table,\"a\"\n\t" \
525 STR(PTR)"\t1b, 4b\n\t" \
526 STR(PTR)"\t2b, 4b\n\t" \
528 : "=&r" (value), "=r" (res) \
529 : "r" (addr), "i" (-EFAULT)); \
533 /* MIPSR6 has no lwl instruction */
534 #define _LoadW(addr, value, res, type) \
536 __asm__ __volatile__ ( \
539 "1:"type##_lb("%0", "3(%2)")"\n\t" \
540 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
543 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
546 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
553 ".section\t.fixup,\"ax\"\n\t" \
554 "11:\tli\t%1, %3\n\t" \
557 ".section\t__ex_table,\"a\"\n\t" \
558 STR(PTR)"\t1b, 11b\n\t" \
559 STR(PTR)"\t2b, 11b\n\t" \
560 STR(PTR)"\t3b, 11b\n\t" \
561 STR(PTR)"\t4b, 11b\n\t" \
563 : "=&r" (value), "=r" (res) \
564 : "r" (addr), "i" (-EFAULT)); \
567 #endif /* CONFIG_CPU_MIPSR6 */
570 #define _LoadHWU(addr, value, res, type) \
572 __asm__ __volatile__ ( \
574 "1:\t"type##_lbu("%0", "1(%2)")"\n" \
575 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
582 ".section\t.fixup,\"ax\"\n\t" \
583 "4:\tli\t%1, %3\n\t" \
586 ".section\t__ex_table,\"a\"\n\t" \
587 STR(PTR)"\t1b, 4b\n\t" \
588 STR(PTR)"\t2b, 4b\n\t" \
590 : "=&r" (value), "=r" (res) \
591 : "r" (addr), "i" (-EFAULT)); \
594 #ifndef CONFIG_CPU_MIPSR6
595 #define _LoadWU(addr, value, res, type) \
597 __asm__ __volatile__ ( \
598 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
599 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
600 "dsll\t%0, %0, 32\n\t" \
601 "dsrl\t%0, %0, 32\n\t" \
605 "\t.section\t.fixup,\"ax\"\n\t" \
606 "4:\tli\t%1, %3\n\t" \
609 ".section\t__ex_table,\"a\"\n\t" \
610 STR(PTR)"\t1b, 4b\n\t" \
611 STR(PTR)"\t2b, 4b\n\t" \
613 : "=&r" (value), "=r" (res) \
614 : "r" (addr), "i" (-EFAULT)); \
617 #define _LoadDW(addr, value, res) \
619 __asm__ __volatile__ ( \
620 "1:\tldl\t%0, 7(%2)\n" \
621 "2:\tldr\t%0, (%2)\n\t" \
625 "\t.section\t.fixup,\"ax\"\n\t" \
626 "4:\tli\t%1, %3\n\t" \
629 ".section\t__ex_table,\"a\"\n\t" \
630 STR(PTR)"\t1b, 4b\n\t" \
631 STR(PTR)"\t2b, 4b\n\t" \
633 : "=&r" (value), "=r" (res) \
634 : "r" (addr), "i" (-EFAULT)); \
638 /* MIPSR6 has not lwl and ldl instructions */
639 #define _LoadWU(addr, value, res, type) \
641 __asm__ __volatile__ ( \
644 "1:"type##_lbu("%0", "3(%2)")"\n\t" \
645 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
648 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
651 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
658 ".section\t.fixup,\"ax\"\n\t" \
659 "11:\tli\t%1, %3\n\t" \
662 ".section\t__ex_table,\"a\"\n\t" \
663 STR(PTR)"\t1b, 11b\n\t" \
664 STR(PTR)"\t2b, 11b\n\t" \
665 STR(PTR)"\t3b, 11b\n\t" \
666 STR(PTR)"\t4b, 11b\n\t" \
668 : "=&r" (value), "=r" (res) \
669 : "r" (addr), "i" (-EFAULT)); \
672 #define _LoadDW(addr, value, res) \
674 __asm__ __volatile__ ( \
677 "1:lb\t%0, 7(%2)\n\t" \
678 "2:lbu\t$1, 6(%2)\n\t" \
679 "dsll\t%0, 0x8\n\t" \
681 "3:lbu\t$1, 5(%2)\n\t" \
682 "dsll\t%0, 0x8\n\t" \
684 "4:lbu\t$1, 4(%2)\n\t" \
685 "dsll\t%0, 0x8\n\t" \
687 "5:lbu\t$1, 3(%2)\n\t" \
688 "dsll\t%0, 0x8\n\t" \
690 "6:lbu\t$1, 2(%2)\n\t" \
691 "dsll\t%0, 0x8\n\t" \
693 "7:lbu\t$1, 1(%2)\n\t" \
694 "dsll\t%0, 0x8\n\t" \
696 "8:lbu\t$1, 0(%2)\n\t" \
697 "dsll\t%0, 0x8\n\t" \
703 ".section\t.fixup,\"ax\"\n\t" \
704 "11:\tli\t%1, %3\n\t" \
707 ".section\t__ex_table,\"a\"\n\t" \
708 STR(PTR)"\t1b, 11b\n\t" \
709 STR(PTR)"\t2b, 11b\n\t" \
710 STR(PTR)"\t3b, 11b\n\t" \
711 STR(PTR)"\t4b, 11b\n\t" \
712 STR(PTR)"\t5b, 11b\n\t" \
713 STR(PTR)"\t6b, 11b\n\t" \
714 STR(PTR)"\t7b, 11b\n\t" \
715 STR(PTR)"\t8b, 11b\n\t" \
717 : "=&r" (value), "=r" (res) \
718 : "r" (addr), "i" (-EFAULT)); \
720 #endif /* CONFIG_CPU_MIPSR6 */
722 #define _StoreHW(addr, value, res, type) \
724 __asm__ __volatile__ ( \
726 "1:\t"type##_sb("%1", "0(%2)")"\n" \
727 "srl\t$1,%1, 0x8\n" \
728 "2:\t"type##_sb("$1", "1(%2)")"\n" \
733 ".section\t.fixup,\"ax\"\n\t" \
734 "4:\tli\t%0, %3\n\t" \
737 ".section\t__ex_table,\"a\"\n\t" \
738 STR(PTR)"\t1b, 4b\n\t" \
739 STR(PTR)"\t2b, 4b\n\t" \
742 : "r" (value), "r" (addr), "i" (-EFAULT));\
745 #ifndef CONFIG_CPU_MIPSR6
746 #define _StoreW(addr, value, res, type) \
748 __asm__ __volatile__ ( \
749 "1:\t"type##_swl("%1", "3(%2)")"\n" \
750 "2:\t"type##_swr("%1", "(%2)")"\n\t"\
754 ".section\t.fixup,\"ax\"\n\t" \
755 "4:\tli\t%0, %3\n\t" \
758 ".section\t__ex_table,\"a\"\n\t" \
759 STR(PTR)"\t1b, 4b\n\t" \
760 STR(PTR)"\t2b, 4b\n\t" \
763 : "r" (value), "r" (addr), "i" (-EFAULT)); \
766 #define _StoreDW(addr, value, res) \
768 __asm__ __volatile__ ( \
769 "1:\tsdl\t%1, 7(%2)\n" \
770 "2:\tsdr\t%1, (%2)\n\t" \
774 ".section\t.fixup,\"ax\"\n\t" \
775 "4:\tli\t%0, %3\n\t" \
778 ".section\t__ex_table,\"a\"\n\t" \
779 STR(PTR)"\t1b, 4b\n\t" \
780 STR(PTR)"\t2b, 4b\n\t" \
783 : "r" (value), "r" (addr), "i" (-EFAULT)); \
787 /* MIPSR6 has no swl and sdl instructions */
788 #define _StoreW(addr, value, res, type) \
790 __asm__ __volatile__ ( \
793 "1:"type##_sb("%1", "0(%2)")"\n\t" \
794 "srl\t$1, %1, 0x8\n\t" \
795 "2:"type##_sb("$1", "1(%2)")"\n\t" \
796 "srl\t$1, $1, 0x8\n\t" \
797 "3:"type##_sb("$1", "2(%2)")"\n\t" \
798 "srl\t$1, $1, 0x8\n\t" \
799 "4:"type##_sb("$1", "3(%2)")"\n\t" \
804 ".section\t.fixup,\"ax\"\n\t" \
805 "11:\tli\t%0, %3\n\t" \
808 ".section\t__ex_table,\"a\"\n\t" \
809 STR(PTR)"\t1b, 11b\n\t" \
810 STR(PTR)"\t2b, 11b\n\t" \
811 STR(PTR)"\t3b, 11b\n\t" \
812 STR(PTR)"\t4b, 11b\n\t" \
815 : "r" (value), "r" (addr), "i" (-EFAULT) \
819 #define _StoreDW(addr, value, res) \
821 __asm__ __volatile__ ( \
824 "1:sb\t%1, 0(%2)\n\t" \
825 "dsrl\t$1, %1, 0x8\n\t" \
826 "2:sb\t$1, 1(%2)\n\t" \
827 "dsrl\t$1, $1, 0x8\n\t" \
828 "3:sb\t$1, 2(%2)\n\t" \
829 "dsrl\t$1, $1, 0x8\n\t" \
830 "4:sb\t$1, 3(%2)\n\t" \
831 "dsrl\t$1, $1, 0x8\n\t" \
832 "5:sb\t$1, 4(%2)\n\t" \
833 "dsrl\t$1, $1, 0x8\n\t" \
834 "6:sb\t$1, 5(%2)\n\t" \
835 "dsrl\t$1, $1, 0x8\n\t" \
836 "7:sb\t$1, 6(%2)\n\t" \
837 "dsrl\t$1, $1, 0x8\n\t" \
838 "8:sb\t$1, 7(%2)\n\t" \
839 "dsrl\t$1, $1, 0x8\n\t" \
844 ".section\t.fixup,\"ax\"\n\t" \
845 "11:\tli\t%0, %3\n\t" \
848 ".section\t__ex_table,\"a\"\n\t" \
849 STR(PTR)"\t1b, 11b\n\t" \
850 STR(PTR)"\t2b, 11b\n\t" \
851 STR(PTR)"\t3b, 11b\n\t" \
852 STR(PTR)"\t4b, 11b\n\t" \
853 STR(PTR)"\t5b, 11b\n\t" \
854 STR(PTR)"\t6b, 11b\n\t" \
855 STR(PTR)"\t7b, 11b\n\t" \
856 STR(PTR)"\t8b, 11b\n\t" \
859 : "r" (value), "r" (addr), "i" (-EFAULT) \
863 #endif /* CONFIG_CPU_MIPSR6 */
866 #define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
867 #define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
868 #define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
869 #define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
870 #define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
871 #define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
872 #define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
873 #define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
874 #define LoadDW(addr, value, res) _LoadDW(addr, value, res)
876 #define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
877 #define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
878 #define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
879 #define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
880 #define StoreDW(addr, value, res) _StoreDW(addr, value, res)
882 static void emulate_load_store_insn(struct pt_regs *regs,
883 void __user *addr, unsigned int __user *pc)
885 union mips_instruction insn;
888 unsigned long origpc;
889 unsigned long orig31;
890 void __user *fault_addr = NULL;
897 origpc = (unsigned long)pc;
898 orig31 = regs->regs[31];
900 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
903 * This load never faults.
905 __get_user(insn.word, pc);
907 switch (insn.i_format.opcode) {
909 * These are instructions that a compiler doesn't generate. We
910 * can assume therefore that the code is MIPS-aware and
911 * really buggy. Emulating these instructions would break the
920 * For these instructions the only way to create an address
921 * error is an attempted access to kernel/supervisor address
938 * The remaining opcodes are the ones that are really of
944 * we can land here only from kernel accessing user memory,
945 * so we need to "switch" the address limit to user space, so
946 * address check can work properly.
950 switch (insn.spec3_format.func) {
952 if (!access_ok(VERIFY_READ, addr, 2)) {
956 LoadHWE(addr, value, res);
961 compute_return_epc(regs);
962 regs->regs[insn.spec3_format.rt] = value;
965 if (!access_ok(VERIFY_READ, addr, 4)) {
969 LoadWE(addr, value, res);
974 compute_return_epc(regs);
975 regs->regs[insn.spec3_format.rt] = value;
978 if (!access_ok(VERIFY_READ, addr, 2)) {
982 LoadHWUE(addr, value, res);
987 compute_return_epc(regs);
988 regs->regs[insn.spec3_format.rt] = value;
991 if (!access_ok(VERIFY_WRITE, addr, 2)) {
995 compute_return_epc(regs);
996 value = regs->regs[insn.spec3_format.rt];
997 StoreHWE(addr, value, res);
1004 if (!access_ok(VERIFY_WRITE, addr, 4)) {
1008 compute_return_epc(regs);
1009 value = regs->regs[insn.spec3_format.rt];
1010 StoreWE(addr, value, res);
1024 if (!access_ok(VERIFY_READ, addr, 2))
1027 if (config_enabled(CONFIG_EVA)) {
1028 if (segment_eq(get_fs(), get_ds()))
1029 LoadHW(addr, value, res);
1031 LoadHWE(addr, value, res);
1033 LoadHW(addr, value, res);
1038 compute_return_epc(regs);
1039 regs->regs[insn.i_format.rt] = value;
1043 if (!access_ok(VERIFY_READ, addr, 4))
1046 if (config_enabled(CONFIG_EVA)) {
1047 if (segment_eq(get_fs(), get_ds()))
1048 LoadW(addr, value, res);
1050 LoadWE(addr, value, res);
1052 LoadW(addr, value, res);
1057 compute_return_epc(regs);
1058 regs->regs[insn.i_format.rt] = value;
1062 if (!access_ok(VERIFY_READ, addr, 2))
1065 if (config_enabled(CONFIG_EVA)) {
1066 if (segment_eq(get_fs(), get_ds()))
1067 LoadHWU(addr, value, res);
1069 LoadHWUE(addr, value, res);
1071 LoadHWU(addr, value, res);
1076 compute_return_epc(regs);
1077 regs->regs[insn.i_format.rt] = value;
1083 * A 32-bit kernel might be running on a 64-bit processor. But
1084 * if we're on a 32-bit processor and an i-cache incoherency
1085 * or race makes us see a 64-bit instruction here the sdl/sdr
1086 * would blow up, so for now we don't handle unaligned 64-bit
1087 * instructions on 32-bit kernels.
1089 if (!access_ok(VERIFY_READ, addr, 4))
1092 LoadWU(addr, value, res);
1095 compute_return_epc(regs);
1096 regs->regs[insn.i_format.rt] = value;
1098 #endif /* CONFIG_64BIT */
1100 /* Cannot handle 64-bit instructions in 32-bit kernel */
1106 * A 32-bit kernel might be running on a 64-bit processor. But
1107 * if we're on a 32-bit processor and an i-cache incoherency
1108 * or race makes us see a 64-bit instruction here the sdl/sdr
1109 * would blow up, so for now we don't handle unaligned 64-bit
1110 * instructions on 32-bit kernels.
1112 if (!access_ok(VERIFY_READ, addr, 8))
1115 LoadDW(addr, value, res);
1118 compute_return_epc(regs);
1119 regs->regs[insn.i_format.rt] = value;
1121 #endif /* CONFIG_64BIT */
1123 /* Cannot handle 64-bit instructions in 32-bit kernel */
1127 if (!access_ok(VERIFY_WRITE, addr, 2))
1130 compute_return_epc(regs);
1131 value = regs->regs[insn.i_format.rt];
1133 if (config_enabled(CONFIG_EVA)) {
1134 if (segment_eq(get_fs(), get_ds()))
1135 StoreHW(addr, value, res);
1137 StoreHWE(addr, value, res);
1139 StoreHW(addr, value, res);
1147 if (!access_ok(VERIFY_WRITE, addr, 4))
1150 compute_return_epc(regs);
1151 value = regs->regs[insn.i_format.rt];
1153 if (config_enabled(CONFIG_EVA)) {
1154 if (segment_eq(get_fs(), get_ds()))
1155 StoreW(addr, value, res);
1157 StoreWE(addr, value, res);
1159 StoreW(addr, value, res);
1169 * A 32-bit kernel might be running on a 64-bit processor. But
1170 * if we're on a 32-bit processor and an i-cache incoherency
1171 * or race makes us see a 64-bit instruction here the sdl/sdr
1172 * would blow up, so for now we don't handle unaligned 64-bit
1173 * instructions on 32-bit kernels.
1175 if (!access_ok(VERIFY_WRITE, addr, 8))
1178 compute_return_epc(regs);
1179 value = regs->regs[insn.i_format.rt];
1180 StoreDW(addr, value, res);
1184 #endif /* CONFIG_64BIT */
1186 /* Cannot handle 64-bit instructions in 32-bit kernel */
1193 die_if_kernel("Unaligned FP access in kernel code", regs);
1194 BUG_ON(!used_math());
1196 lose_fpu(1); /* Save FPU state for the emulator. */
1197 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1199 own_fpu(1); /* Restore FPU state. */
1201 /* Signal if something went wrong. */
1202 process_fpemu_return(res, fault_addr, 0);
1213 * If we've reached this point then userland should have taken
1214 * the MSA disabled exception & initialised vector context at
1215 * some point in the past.
1217 BUG_ON(!thread_msa_context_live());
1219 df = insn.msa_mi10_format.df;
1220 wd = insn.msa_mi10_format.wd;
1221 fpr = ¤t->thread.fpu.fpr[wd];
1223 switch (insn.msa_mi10_format.func) {
1225 if (!access_ok(VERIFY_READ, addr, sizeof(*fpr)))
1229 * Disable preemption to avoid a race between copying
1230 * state from userland, migrating to another CPU and
1231 * updating the hardware vector register below.
1235 res = __copy_from_user_inatomic(fpr, addr,
1241 * Update the hardware register if it is in use by the
1242 * task in this quantum, in order to avoid having to
1243 * save & restore the whole vector context.
1245 if (test_thread_flag(TIF_USEDMSA))
1246 write_msa_wr(wd, fpr, df);
1252 if (!access_ok(VERIFY_WRITE, addr, sizeof(*fpr)))
1256 * Update from the hardware register if it is in use by
1257 * the task in this quantum, in order to avoid having to
1258 * save & restore the whole vector context.
1261 if (test_thread_flag(TIF_USEDMSA))
1262 read_msa_wr(wd, fpr, df);
1265 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr));
1274 compute_return_epc(regs);
1277 #ifndef CONFIG_CPU_MIPSR6
1279 * COP2 is available to implementor for application specific use.
1280 * It's up to applications to register a notifier chain and do
1281 * whatever they have to do, including possible sending of signals.
1283 * This instruction has been reallocated in Release 6
1286 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
1290 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
1294 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
1298 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
1303 * Pheeee... We encountered an yet unknown instruction or
1304 * cache coherence problem. Die sucker, die ...
1309 #ifdef CONFIG_DEBUG_FS
1310 unaligned_instructions++;
1316 /* roll back jump/branch */
1317 regs->cp0_epc = origpc;
1318 regs->regs[31] = orig31;
1319 /* Did we have an exception handler installed? */
1320 if (fixup_exception(regs))
1323 die_if_kernel("Unhandled kernel unaligned access", regs);
1324 force_sig(SIGSEGV, current);
1329 die_if_kernel("Unhandled kernel unaligned access", regs);
1330 force_sig(SIGBUS, current);
1336 ("Unhandled kernel unaligned access or invalid instruction", regs);
1337 force_sig(SIGILL, current);
1340 /* Recode table from 16-bit register notation to 32-bit GPR. */
1341 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
1343 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1344 const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
1346 static void emulate_load_store_microMIPS(struct pt_regs *regs,
1349 unsigned long value;
1352 unsigned int reg = 0, rvar;
1353 unsigned long orig31;
1357 unsigned long origpc, contpc;
1358 union mips_instruction insn;
1359 struct mm_decoded_insn mminsn;
1360 void __user *fault_addr = NULL;
1362 origpc = regs->cp0_epc;
1363 orig31 = regs->regs[31];
1365 mminsn.micro_mips_mode = 1;
1368 * This load never faults.
1370 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
1371 __get_user(halfword, pc16);
1373 contpc = regs->cp0_epc + 2;
1374 word = ((unsigned int)halfword << 16);
1377 if (!mm_insn_16bit(halfword)) {
1378 __get_user(halfword, pc16);
1380 contpc = regs->cp0_epc + 4;
1386 if (get_user(halfword, pc16))
1388 mminsn.next_pc_inc = 2;
1389 word = ((unsigned int)halfword << 16);
1391 if (!mm_insn_16bit(halfword)) {
1393 if (get_user(halfword, pc16))
1395 mminsn.next_pc_inc = 4;
1398 mminsn.next_insn = word;
1400 insn = (union mips_instruction)(mminsn.insn);
1401 if (mm_isBranchInstr(regs, mminsn, &contpc))
1402 insn = (union mips_instruction)(mminsn.next_insn);
1404 /* Parse instruction to find what to do */
1406 switch (insn.mm_i_format.opcode) {
1409 switch (insn.mm_x_format.func) {
1411 reg = insn.mm_x_format.rd;
1418 switch (insn.mm_m_format.func) {
1420 reg = insn.mm_m_format.rd;
1424 if (!access_ok(VERIFY_READ, addr, 8))
1427 LoadW(addr, value, res);
1430 regs->regs[reg] = value;
1432 LoadW(addr, value, res);
1435 regs->regs[reg + 1] = value;
1439 reg = insn.mm_m_format.rd;
1443 if (!access_ok(VERIFY_WRITE, addr, 8))
1446 value = regs->regs[reg];
1447 StoreW(addr, value, res);
1451 value = regs->regs[reg + 1];
1452 StoreW(addr, value, res);
1459 reg = insn.mm_m_format.rd;
1463 if (!access_ok(VERIFY_READ, addr, 16))
1466 LoadDW(addr, value, res);
1469 regs->regs[reg] = value;
1471 LoadDW(addr, value, res);
1474 regs->regs[reg + 1] = value;
1476 #endif /* CONFIG_64BIT */
1482 reg = insn.mm_m_format.rd;
1486 if (!access_ok(VERIFY_WRITE, addr, 16))
1489 value = regs->regs[reg];
1490 StoreDW(addr, value, res);
1494 value = regs->regs[reg + 1];
1495 StoreDW(addr, value, res);
1499 #endif /* CONFIG_64BIT */
1504 reg = insn.mm_m_format.rd;
1506 if ((rvar > 9) || !reg)
1510 (VERIFY_READ, addr, 4 * (rvar + 1)))
1513 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1518 for (i = 16; rvar; rvar--, i++) {
1519 LoadW(addr, value, res);
1523 regs->regs[i] = value;
1525 if ((reg & 0xf) == 9) {
1526 LoadW(addr, value, res);
1530 regs->regs[30] = value;
1533 LoadW(addr, value, res);
1536 regs->regs[31] = value;
1541 reg = insn.mm_m_format.rd;
1543 if ((rvar > 9) || !reg)
1547 (VERIFY_WRITE, addr, 4 * (rvar + 1)))
1550 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1555 for (i = 16; rvar; rvar--, i++) {
1556 value = regs->regs[i];
1557 StoreW(addr, value, res);
1562 if ((reg & 0xf) == 9) {
1563 value = regs->regs[30];
1564 StoreW(addr, value, res);
1570 value = regs->regs[31];
1571 StoreW(addr, value, res);
1579 reg = insn.mm_m_format.rd;
1581 if ((rvar > 9) || !reg)
1585 (VERIFY_READ, addr, 8 * (rvar + 1)))
1588 if (!access_ok(VERIFY_READ, addr, 8 * rvar))
1594 for (i = 16; rvar; rvar--, i++) {
1595 LoadDW(addr, value, res);
1599 regs->regs[i] = value;
1601 if ((reg & 0xf) == 9) {
1602 LoadDW(addr, value, res);
1606 regs->regs[30] = value;
1609 LoadDW(addr, value, res);
1612 regs->regs[31] = value;
1615 #endif /* CONFIG_64BIT */
1621 reg = insn.mm_m_format.rd;
1623 if ((rvar > 9) || !reg)
1627 (VERIFY_WRITE, addr, 8 * (rvar + 1)))
1630 if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
1636 for (i = 16; rvar; rvar--, i++) {
1637 value = regs->regs[i];
1638 StoreDW(addr, value, res);
1643 if ((reg & 0xf) == 9) {
1644 value = regs->regs[30];
1645 StoreDW(addr, value, res);
1651 value = regs->regs[31];
1652 StoreDW(addr, value, res);
1657 #endif /* CONFIG_64BIT */
1661 /* LWC2, SWC2, LDC2, SDC2 are not serviced */
1667 switch (insn.mm_m_format.func) {
1669 reg = insn.mm_m_format.rd;
1673 /* LL,SC,LLD,SCD are not serviced */
1677 switch (insn.mm_x_format.func) {
1692 /* roll back jump/branch */
1693 regs->cp0_epc = origpc;
1694 regs->regs[31] = orig31;
1696 die_if_kernel("Unaligned FP access in kernel code", regs);
1697 BUG_ON(!used_math());
1698 BUG_ON(!is_fpu_owner());
1700 lose_fpu(1); /* save the FPU state for the emulator */
1701 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1703 own_fpu(1); /* restore FPU state */
1705 /* If something went wrong, signal */
1706 process_fpemu_return(res, fault_addr, 0);
1713 reg = insn.mm_i_format.rt;
1717 reg = insn.mm_i_format.rt;
1721 reg = insn.mm_i_format.rt;
1725 reg = insn.mm_i_format.rt;
1729 reg = insn.mm_i_format.rt;
1733 reg = insn.mm_i_format.rt;
1737 reg = insn.mm_i_format.rt;
1741 switch (insn.mm16_m_format.func) {
1743 reg = insn.mm16_m_format.rlist;
1745 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1748 for (i = 16; rvar; rvar--, i++) {
1749 LoadW(addr, value, res);
1753 regs->regs[i] = value;
1755 LoadW(addr, value, res);
1758 regs->regs[31] = value;
1763 reg = insn.mm16_m_format.rlist;
1765 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1768 for (i = 16; rvar; rvar--, i++) {
1769 value = regs->regs[i];
1770 StoreW(addr, value, res);
1775 value = regs->regs[31];
1776 StoreW(addr, value, res);
1787 reg = reg16to32[insn.mm16_rb_format.rt];
1791 reg = reg16to32[insn.mm16_rb_format.rt];
1795 reg = reg16to32st[insn.mm16_rb_format.rt];
1799 reg = reg16to32st[insn.mm16_rb_format.rt];
1803 reg = insn.mm16_r5_format.rt;
1807 reg = insn.mm16_r5_format.rt;
1811 reg = reg16to32[insn.mm16_r3_format.rt];
1819 if (!access_ok(VERIFY_READ, addr, 2))
1822 LoadHW(addr, value, res);
1825 regs->regs[reg] = value;
1829 if (!access_ok(VERIFY_READ, addr, 2))
1832 LoadHWU(addr, value, res);
1835 regs->regs[reg] = value;
1839 if (!access_ok(VERIFY_READ, addr, 4))
1842 LoadW(addr, value, res);
1845 regs->regs[reg] = value;
1851 * A 32-bit kernel might be running on a 64-bit processor. But
1852 * if we're on a 32-bit processor and an i-cache incoherency
1853 * or race makes us see a 64-bit instruction here the sdl/sdr
1854 * would blow up, so for now we don't handle unaligned 64-bit
1855 * instructions on 32-bit kernels.
1857 if (!access_ok(VERIFY_READ, addr, 4))
1860 LoadWU(addr, value, res);
1863 regs->regs[reg] = value;
1865 #endif /* CONFIG_64BIT */
1867 /* Cannot handle 64-bit instructions in 32-bit kernel */
1873 * A 32-bit kernel might be running on a 64-bit processor. But
1874 * if we're on a 32-bit processor and an i-cache incoherency
1875 * or race makes us see a 64-bit instruction here the sdl/sdr
1876 * would blow up, so for now we don't handle unaligned 64-bit
1877 * instructions on 32-bit kernels.
1879 if (!access_ok(VERIFY_READ, addr, 8))
1882 LoadDW(addr, value, res);
1885 regs->regs[reg] = value;
1887 #endif /* CONFIG_64BIT */
1889 /* Cannot handle 64-bit instructions in 32-bit kernel */
1893 if (!access_ok(VERIFY_WRITE, addr, 2))
1896 value = regs->regs[reg];
1897 StoreHW(addr, value, res);
1903 if (!access_ok(VERIFY_WRITE, addr, 4))
1906 value = regs->regs[reg];
1907 StoreW(addr, value, res);
1915 * A 32-bit kernel might be running on a 64-bit processor. But
1916 * if we're on a 32-bit processor and an i-cache incoherency
1917 * or race makes us see a 64-bit instruction here the sdl/sdr
1918 * would blow up, so for now we don't handle unaligned 64-bit
1919 * instructions on 32-bit kernels.
1921 if (!access_ok(VERIFY_WRITE, addr, 8))
1924 value = regs->regs[reg];
1925 StoreDW(addr, value, res);
1929 #endif /* CONFIG_64BIT */
1931 /* Cannot handle 64-bit instructions in 32-bit kernel */
1935 regs->cp0_epc = contpc; /* advance or branch */
1937 #ifdef CONFIG_DEBUG_FS
1938 unaligned_instructions++;
1943 /* roll back jump/branch */
1944 regs->cp0_epc = origpc;
1945 regs->regs[31] = orig31;
1946 /* Did we have an exception handler installed? */
1947 if (fixup_exception(regs))
1950 die_if_kernel("Unhandled kernel unaligned access", regs);
1951 force_sig(SIGSEGV, current);
1956 die_if_kernel("Unhandled kernel unaligned access", regs);
1957 force_sig(SIGBUS, current);
1963 ("Unhandled kernel unaligned access or invalid instruction", regs);
1964 force_sig(SIGILL, current);
1967 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1969 unsigned long value;
1972 unsigned long orig31;
1974 unsigned long origpc;
1975 union mips16e_instruction mips16inst, oldinst;
1977 origpc = regs->cp0_epc;
1978 orig31 = regs->regs[31];
1979 pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1981 * This load never faults.
1983 __get_user(mips16inst.full, pc16);
1984 oldinst = mips16inst;
1986 /* skip EXTEND instruction */
1987 if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1989 __get_user(mips16inst.full, pc16);
1990 } else if (delay_slot(regs)) {
1991 /* skip jump instructions */
1992 /* JAL/JALX are 32 bits but have OPCODE in first short int */
1993 if (mips16inst.ri.opcode == MIPS16e_jal_op)
1996 if (get_user(mips16inst.full, pc16))
2000 switch (mips16inst.ri.opcode) {
2001 case MIPS16e_i64_op: /* I64 or RI64 instruction */
2002 switch (mips16inst.i64.func) { /* I64/RI64 func field check */
2003 case MIPS16e_ldpc_func:
2004 case MIPS16e_ldsp_func:
2005 reg = reg16to32[mips16inst.ri64.ry];
2008 case MIPS16e_sdsp_func:
2009 reg = reg16to32[mips16inst.ri64.ry];
2012 case MIPS16e_sdrasp_func:
2013 reg = 29; /* GPRSP */
2019 case MIPS16e_swsp_op:
2020 case MIPS16e_lwpc_op:
2021 case MIPS16e_lwsp_op:
2022 reg = reg16to32[mips16inst.ri.rx];
2026 if (mips16inst.i8.func != MIPS16e_swrasp_func)
2028 reg = 29; /* GPRSP */
2032 reg = reg16to32[mips16inst.rri.ry];
2036 switch (mips16inst.ri.opcode) {
2039 case MIPS16e_lbu_op:
2044 if (!access_ok(VERIFY_READ, addr, 2))
2047 LoadHW(addr, value, res);
2050 MIPS16e_compute_return_epc(regs, &oldinst);
2051 regs->regs[reg] = value;
2054 case MIPS16e_lhu_op:
2055 if (!access_ok(VERIFY_READ, addr, 2))
2058 LoadHWU(addr, value, res);
2061 MIPS16e_compute_return_epc(regs, &oldinst);
2062 regs->regs[reg] = value;
2066 case MIPS16e_lwpc_op:
2067 case MIPS16e_lwsp_op:
2068 if (!access_ok(VERIFY_READ, addr, 4))
2071 LoadW(addr, value, res);
2074 MIPS16e_compute_return_epc(regs, &oldinst);
2075 regs->regs[reg] = value;
2078 case MIPS16e_lwu_op:
2081 * A 32-bit kernel might be running on a 64-bit processor. But
2082 * if we're on a 32-bit processor and an i-cache incoherency
2083 * or race makes us see a 64-bit instruction here the sdl/sdr
2084 * would blow up, so for now we don't handle unaligned 64-bit
2085 * instructions on 32-bit kernels.
2087 if (!access_ok(VERIFY_READ, addr, 4))
2090 LoadWU(addr, value, res);
2093 MIPS16e_compute_return_epc(regs, &oldinst);
2094 regs->regs[reg] = value;
2096 #endif /* CONFIG_64BIT */
2098 /* Cannot handle 64-bit instructions in 32-bit kernel */
2105 * A 32-bit kernel might be running on a 64-bit processor. But
2106 * if we're on a 32-bit processor and an i-cache incoherency
2107 * or race makes us see a 64-bit instruction here the sdl/sdr
2108 * would blow up, so for now we don't handle unaligned 64-bit
2109 * instructions on 32-bit kernels.
2111 if (!access_ok(VERIFY_READ, addr, 8))
2114 LoadDW(addr, value, res);
2117 MIPS16e_compute_return_epc(regs, &oldinst);
2118 regs->regs[reg] = value;
2120 #endif /* CONFIG_64BIT */
2122 /* Cannot handle 64-bit instructions in 32-bit kernel */
2126 if (!access_ok(VERIFY_WRITE, addr, 2))
2129 MIPS16e_compute_return_epc(regs, &oldinst);
2130 value = regs->regs[reg];
2131 StoreHW(addr, value, res);
2137 case MIPS16e_swsp_op:
2138 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
2139 if (!access_ok(VERIFY_WRITE, addr, 4))
2142 MIPS16e_compute_return_epc(regs, &oldinst);
2143 value = regs->regs[reg];
2144 StoreW(addr, value, res);
2153 * A 32-bit kernel might be running on a 64-bit processor. But
2154 * if we're on a 32-bit processor and an i-cache incoherency
2155 * or race makes us see a 64-bit instruction here the sdl/sdr
2156 * would blow up, so for now we don't handle unaligned 64-bit
2157 * instructions on 32-bit kernels.
2159 if (!access_ok(VERIFY_WRITE, addr, 8))
2162 MIPS16e_compute_return_epc(regs, &oldinst);
2163 value = regs->regs[reg];
2164 StoreDW(addr, value, res);
2168 #endif /* CONFIG_64BIT */
2170 /* Cannot handle 64-bit instructions in 32-bit kernel */
2175 * Pheeee... We encountered an yet unknown instruction or
2176 * cache coherence problem. Die sucker, die ...
2181 #ifdef CONFIG_DEBUG_FS
2182 unaligned_instructions++;
2188 /* roll back jump/branch */
2189 regs->cp0_epc = origpc;
2190 regs->regs[31] = orig31;
2191 /* Did we have an exception handler installed? */
2192 if (fixup_exception(regs))
2195 die_if_kernel("Unhandled kernel unaligned access", regs);
2196 force_sig(SIGSEGV, current);
2201 die_if_kernel("Unhandled kernel unaligned access", regs);
2202 force_sig(SIGBUS, current);
2208 ("Unhandled kernel unaligned access or invalid instruction", regs);
2209 force_sig(SIGILL, current);
2212 asmlinkage void do_ade(struct pt_regs *regs)
2214 enum ctx_state prev_state;
2215 unsigned int __user *pc;
2218 prev_state = exception_enter();
2219 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
2220 1, regs, regs->cp0_badvaddr);
2222 * Did we catch a fault trying to load an instruction?
2224 if (regs->cp0_badvaddr == regs->cp0_epc)
2227 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
2229 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
2233 * Do branch emulation only if we didn't forward the exception.
2234 * This is all so but ugly ...
2238 * Are we running in microMIPS mode?
2240 if (get_isa16_mode(regs->cp0_epc)) {
2242 * Did we catch a fault trying to load an instruction in
2245 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
2247 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2248 show_registers(regs);
2250 if (cpu_has_mmips) {
2252 if (!user_mode(regs))
2254 emulate_load_store_microMIPS(regs,
2255 (void __user *)regs->cp0_badvaddr);
2261 if (cpu_has_mips16) {
2263 if (!user_mode(regs))
2265 emulate_load_store_MIPS16e(regs,
2266 (void __user *)regs->cp0_badvaddr);
2275 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2276 show_registers(regs);
2277 pc = (unsigned int __user *)exception_epc(regs);
2280 if (!user_mode(regs))
2282 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
2288 die_if_kernel("Kernel unaligned instruction access", regs);
2289 force_sig(SIGBUS, current);
2292 * XXX On return from the signal handler we should advance the epc
2294 exception_exit(prev_state);
2297 #ifdef CONFIG_DEBUG_FS
2298 extern struct dentry *mips_debugfs_dir;
2299 static int __init debugfs_unaligned(void)
2303 if (!mips_debugfs_dir)
2305 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
2306 mips_debugfs_dir, &unaligned_instructions);
2309 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
2310 mips_debugfs_dir, &unaligned_action);
2315 arch_initcall(debugfs_unaligned);