2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2014 Imagination Technologies Ltd.
12 * This file contains exception handler for address error exception with the
13 * special capability to execute faulting instructions in software. The
14 * handler does not try to handle the case when the program counter points
15 * to an address not aligned to a word boundary.
17 * Putting data to unaligned addresses is a bad practice even on Intel where
18 * only the performance is affected. Much worse is that such code is non-
19 * portable. Due to several programs that die on MIPS due to alignment
20 * problems I decided to implement this handler anyway though I originally
21 * didn't intend to do this at all for user code.
23 * For now I enable fixing of address errors by default to make life easier.
24 * I however intend to disable this somewhen in the future when the alignment
25 * problems with user programs have been fixed. For programmers this is the
28 * Fixing address errors is a per process option. The option is inherited
29 * across fork(2) and execve(2) calls. If you really want to use the
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
33 * #include <sys/sysmips.h>
36 * sysmips(MIPS_FIXADE, x);
39 * The argument x is 0 for disabling software emulation, enabled otherwise.
41 * Below a little program to play around with this feature.
44 * #include <sys/sysmips.h>
47 * unsigned char bar[8];
50 * main(int argc, char *argv[])
52 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
53 * unsigned int *p = (unsigned int *) (x.bar + 3);
57 * sysmips(MIPS_FIXADE, atoi(argv[1]));
59 * printf("*p = %08lx\n", *p);
63 * for(i = 0; i <= 7; i++)
64 * printf("%02x ", x.bar[i]);
68 * Coprocessor loads are not supported; I think this case is unimportant
71 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
72 * exception for the R6000.
73 * A store crossing a page boundary might be executed only partially.
74 * Undo the partial store in this case.
76 #include <linux/context_tracking.h>
78 #include <linux/signal.h>
79 #include <linux/smp.h>
80 #include <linux/sched.h>
81 #include <linux/debugfs.h>
82 #include <linux/perf_event.h>
85 #include <asm/branch.h>
86 #include <asm/byteorder.h>
88 #include <asm/debug.h>
90 #include <asm/fpu_emulator.h>
92 #include <asm/uaccess.h>
94 #define STR(x) __STR(x)
98 UNALIGNED_ACTION_QUIET,
99 UNALIGNED_ACTION_SIGNAL,
100 UNALIGNED_ACTION_SHOW,
102 #ifdef CONFIG_DEBUG_FS
103 static u32 unaligned_instructions;
104 static u32 unaligned_action;
106 #define unaligned_action UNALIGNED_ACTION_QUIET
108 extern void show_registers(struct pt_regs *regs);
111 #define _LoadHW(addr, value, res, type) \
113 __asm__ __volatile__ (".set\tnoat\n" \
114 "1:\t"type##_lb("%0", "0(%2)")"\n" \
115 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
121 ".section\t.fixup,\"ax\"\n\t" \
122 "4:\tli\t%1, %3\n\t" \
125 ".section\t__ex_table,\"a\"\n\t" \
126 STR(PTR)"\t1b, 4b\n\t" \
127 STR(PTR)"\t2b, 4b\n\t" \
129 : "=&r" (value), "=r" (res) \
130 : "r" (addr), "i" (-EFAULT)); \
133 #ifndef CONFIG_CPU_MIPSR6
134 #define _LoadW(addr, value, res, type) \
136 __asm__ __volatile__ ( \
137 "1:\t"type##_lwl("%0", "(%2)")"\n" \
138 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
142 ".section\t.fixup,\"ax\"\n\t" \
143 "4:\tli\t%1, %3\n\t" \
146 ".section\t__ex_table,\"a\"\n\t" \
147 STR(PTR)"\t1b, 4b\n\t" \
148 STR(PTR)"\t2b, 4b\n\t" \
150 : "=&r" (value), "=r" (res) \
151 : "r" (addr), "i" (-EFAULT)); \
155 /* MIPSR6 has no lwl instruction */
156 #define _LoadW(addr, value, res, type) \
158 __asm__ __volatile__ ( \
161 "1:"type##_lb("%0", "0(%2)")"\n\t" \
162 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
165 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
168 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
175 ".section\t.fixup,\"ax\"\n\t" \
176 "11:\tli\t%1, %3\n\t" \
179 ".section\t__ex_table,\"a\"\n\t" \
180 STR(PTR)"\t1b, 11b\n\t" \
181 STR(PTR)"\t2b, 11b\n\t" \
182 STR(PTR)"\t3b, 11b\n\t" \
183 STR(PTR)"\t4b, 11b\n\t" \
185 : "=&r" (value), "=r" (res) \
186 : "r" (addr), "i" (-EFAULT)); \
189 #endif /* CONFIG_CPU_MIPSR6 */
191 #define _LoadHWU(addr, value, res, type) \
193 __asm__ __volatile__ ( \
195 "1:\t"type##_lbu("%0", "0(%2)")"\n" \
196 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
203 ".section\t.fixup,\"ax\"\n\t" \
204 "4:\tli\t%1, %3\n\t" \
207 ".section\t__ex_table,\"a\"\n\t" \
208 STR(PTR)"\t1b, 4b\n\t" \
209 STR(PTR)"\t2b, 4b\n\t" \
211 : "=&r" (value), "=r" (res) \
212 : "r" (addr), "i" (-EFAULT)); \
215 #ifndef CONFIG_CPU_MIPSR6
216 #define _LoadWU(addr, value, res, type) \
218 __asm__ __volatile__ ( \
219 "1:\t"type##_lwl("%0", "(%2)")"\n" \
220 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
221 "dsll\t%0, %0, 32\n\t" \
222 "dsrl\t%0, %0, 32\n\t" \
226 "\t.section\t.fixup,\"ax\"\n\t" \
227 "4:\tli\t%1, %3\n\t" \
230 ".section\t__ex_table,\"a\"\n\t" \
231 STR(PTR)"\t1b, 4b\n\t" \
232 STR(PTR)"\t2b, 4b\n\t" \
234 : "=&r" (value), "=r" (res) \
235 : "r" (addr), "i" (-EFAULT)); \
238 #define _LoadDW(addr, value, res) \
240 __asm__ __volatile__ ( \
241 "1:\tldl\t%0, (%2)\n" \
242 "2:\tldr\t%0, 7(%2)\n\t" \
246 "\t.section\t.fixup,\"ax\"\n\t" \
247 "4:\tli\t%1, %3\n\t" \
250 ".section\t__ex_table,\"a\"\n\t" \
251 STR(PTR)"\t1b, 4b\n\t" \
252 STR(PTR)"\t2b, 4b\n\t" \
254 : "=&r" (value), "=r" (res) \
255 : "r" (addr), "i" (-EFAULT)); \
259 /* MIPSR6 has not lwl and ldl instructions */
260 #define _LoadWU(addr, value, res, type) \
262 __asm__ __volatile__ ( \
265 "1:"type##_lbu("%0", "0(%2)")"\n\t" \
266 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
269 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
272 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
279 ".section\t.fixup,\"ax\"\n\t" \
280 "11:\tli\t%1, %3\n\t" \
283 ".section\t__ex_table,\"a\"\n\t" \
284 STR(PTR)"\t1b, 11b\n\t" \
285 STR(PTR)"\t2b, 11b\n\t" \
286 STR(PTR)"\t3b, 11b\n\t" \
287 STR(PTR)"\t4b, 11b\n\t" \
289 : "=&r" (value), "=r" (res) \
290 : "r" (addr), "i" (-EFAULT)); \
293 #define _LoadDW(addr, value, res) \
295 __asm__ __volatile__ ( \
298 "1:lb\t%0, 0(%2)\n\t" \
299 "2:lbu\t $1, 1(%2)\n\t" \
300 "dsll\t%0, 0x8\n\t" \
302 "3:lbu\t$1, 2(%2)\n\t" \
303 "dsll\t%0, 0x8\n\t" \
305 "4:lbu\t$1, 3(%2)\n\t" \
306 "dsll\t%0, 0x8\n\t" \
308 "5:lbu\t$1, 4(%2)\n\t" \
309 "dsll\t%0, 0x8\n\t" \
311 "6:lbu\t$1, 5(%2)\n\t" \
312 "dsll\t%0, 0x8\n\t" \
314 "7:lbu\t$1, 6(%2)\n\t" \
315 "dsll\t%0, 0x8\n\t" \
317 "8:lbu\t$1, 7(%2)\n\t" \
318 "dsll\t%0, 0x8\n\t" \
324 ".section\t.fixup,\"ax\"\n\t" \
325 "11:\tli\t%1, %3\n\t" \
328 ".section\t__ex_table,\"a\"\n\t" \
329 STR(PTR)"\t1b, 11b\n\t" \
330 STR(PTR)"\t2b, 11b\n\t" \
331 STR(PTR)"\t3b, 11b\n\t" \
332 STR(PTR)"\t4b, 11b\n\t" \
333 STR(PTR)"\t5b, 11b\n\t" \
334 STR(PTR)"\t6b, 11b\n\t" \
335 STR(PTR)"\t7b, 11b\n\t" \
336 STR(PTR)"\t8b, 11b\n\t" \
338 : "=&r" (value), "=r" (res) \
339 : "r" (addr), "i" (-EFAULT)); \
342 #endif /* CONFIG_CPU_MIPSR6 */
345 #define _StoreHW(addr, value, res, type) \
347 __asm__ __volatile__ ( \
349 "1:\t"type##_sb("%1", "1(%2)")"\n" \
350 "srl\t$1, %1, 0x8\n" \
351 "2:\t"type##_sb("$1", "0(%2)")"\n" \
356 ".section\t.fixup,\"ax\"\n\t" \
357 "4:\tli\t%0, %3\n\t" \
360 ".section\t__ex_table,\"a\"\n\t" \
361 STR(PTR)"\t1b, 4b\n\t" \
362 STR(PTR)"\t2b, 4b\n\t" \
365 : "r" (value), "r" (addr), "i" (-EFAULT));\
368 #ifndef CONFIG_CPU_MIPSR6
369 #define _StoreW(addr, value, res, type) \
371 __asm__ __volatile__ ( \
372 "1:\t"type##_swl("%1", "(%2)")"\n" \
373 "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
377 ".section\t.fixup,\"ax\"\n\t" \
378 "4:\tli\t%0, %3\n\t" \
381 ".section\t__ex_table,\"a\"\n\t" \
382 STR(PTR)"\t1b, 4b\n\t" \
383 STR(PTR)"\t2b, 4b\n\t" \
386 : "r" (value), "r" (addr), "i" (-EFAULT)); \
389 #define _StoreDW(addr, value, res) \
391 __asm__ __volatile__ ( \
392 "1:\tsdl\t%1,(%2)\n" \
393 "2:\tsdr\t%1, 7(%2)\n\t" \
397 ".section\t.fixup,\"ax\"\n\t" \
398 "4:\tli\t%0, %3\n\t" \
401 ".section\t__ex_table,\"a\"\n\t" \
402 STR(PTR)"\t1b, 4b\n\t" \
403 STR(PTR)"\t2b, 4b\n\t" \
406 : "r" (value), "r" (addr), "i" (-EFAULT)); \
410 /* MIPSR6 has no swl and sdl instructions */
411 #define _StoreW(addr, value, res, type) \
413 __asm__ __volatile__ ( \
416 "1:"type##_sb("%1", "3(%2)")"\n\t" \
417 "srl\t$1, %1, 0x8\n\t" \
418 "2:"type##_sb("$1", "2(%2)")"\n\t" \
419 "srl\t$1, $1, 0x8\n\t" \
420 "3:"type##_sb("$1", "1(%2)")"\n\t" \
421 "srl\t$1, $1, 0x8\n\t" \
422 "4:"type##_sb("$1", "0(%2)")"\n\t" \
427 ".section\t.fixup,\"ax\"\n\t" \
428 "11:\tli\t%0, %3\n\t" \
431 ".section\t__ex_table,\"a\"\n\t" \
432 STR(PTR)"\t1b, 11b\n\t" \
433 STR(PTR)"\t2b, 11b\n\t" \
434 STR(PTR)"\t3b, 11b\n\t" \
435 STR(PTR)"\t4b, 11b\n\t" \
438 : "r" (value), "r" (addr), "i" (-EFAULT) \
442 #define _StoreDW(addr, value, res) \
444 __asm__ __volatile__ ( \
447 "1:sb\t%1, 7(%2)\n\t" \
448 "dsrl\t$1, %1, 0x8\n\t" \
449 "2:sb\t$1, 6(%2)\n\t" \
450 "dsrl\t$1, $1, 0x8\n\t" \
451 "3:sb\t$1, 5(%2)\n\t" \
452 "dsrl\t$1, $1, 0x8\n\t" \
453 "4:sb\t$1, 4(%2)\n\t" \
454 "dsrl\t$1, $1, 0x8\n\t" \
455 "5:sb\t$1, 3(%2)\n\t" \
456 "dsrl\t$1, $1, 0x8\n\t" \
457 "6:sb\t$1, 2(%2)\n\t" \
458 "dsrl\t$1, $1, 0x8\n\t" \
459 "7:sb\t$1, 1(%2)\n\t" \
460 "dsrl\t$1, $1, 0x8\n\t" \
461 "8:sb\t$1, 0(%2)\n\t" \
462 "dsrl\t$1, $1, 0x8\n\t" \
467 ".section\t.fixup,\"ax\"\n\t" \
468 "11:\tli\t%0, %3\n\t" \
471 ".section\t__ex_table,\"a\"\n\t" \
472 STR(PTR)"\t1b, 11b\n\t" \
473 STR(PTR)"\t2b, 11b\n\t" \
474 STR(PTR)"\t3b, 11b\n\t" \
475 STR(PTR)"\t4b, 11b\n\t" \
476 STR(PTR)"\t5b, 11b\n\t" \
477 STR(PTR)"\t6b, 11b\n\t" \
478 STR(PTR)"\t7b, 11b\n\t" \
479 STR(PTR)"\t8b, 11b\n\t" \
482 : "r" (value), "r" (addr), "i" (-EFAULT) \
486 #endif /* CONFIG_CPU_MIPSR6 */
488 #else /* __BIG_ENDIAN */
490 #define _LoadHW(addr, value, res, type) \
492 __asm__ __volatile__ (".set\tnoat\n" \
493 "1:\t"type##_lb("%0", "1(%2)")"\n" \
494 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
500 ".section\t.fixup,\"ax\"\n\t" \
501 "4:\tli\t%1, %3\n\t" \
504 ".section\t__ex_table,\"a\"\n\t" \
505 STR(PTR)"\t1b, 4b\n\t" \
506 STR(PTR)"\t2b, 4b\n\t" \
508 : "=&r" (value), "=r" (res) \
509 : "r" (addr), "i" (-EFAULT)); \
512 #ifndef CONFIG_CPU_MIPSR6
513 #define _LoadW(addr, value, res, type) \
515 __asm__ __volatile__ ( \
516 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
517 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
521 ".section\t.fixup,\"ax\"\n\t" \
522 "4:\tli\t%1, %3\n\t" \
525 ".section\t__ex_table,\"a\"\n\t" \
526 STR(PTR)"\t1b, 4b\n\t" \
527 STR(PTR)"\t2b, 4b\n\t" \
529 : "=&r" (value), "=r" (res) \
530 : "r" (addr), "i" (-EFAULT)); \
534 /* MIPSR6 has no lwl instruction */
535 #define _LoadW(addr, value, res, type) \
537 __asm__ __volatile__ ( \
540 "1:"type##_lb("%0", "3(%2)")"\n\t" \
541 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
544 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
547 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
554 ".section\t.fixup,\"ax\"\n\t" \
555 "11:\tli\t%1, %3\n\t" \
558 ".section\t__ex_table,\"a\"\n\t" \
559 STR(PTR)"\t1b, 11b\n\t" \
560 STR(PTR)"\t2b, 11b\n\t" \
561 STR(PTR)"\t3b, 11b\n\t" \
562 STR(PTR)"\t4b, 11b\n\t" \
564 : "=&r" (value), "=r" (res) \
565 : "r" (addr), "i" (-EFAULT)); \
568 #endif /* CONFIG_CPU_MIPSR6 */
571 #define _LoadHWU(addr, value, res, type) \
573 __asm__ __volatile__ ( \
575 "1:\t"type##_lbu("%0", "1(%2)")"\n" \
576 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
583 ".section\t.fixup,\"ax\"\n\t" \
584 "4:\tli\t%1, %3\n\t" \
587 ".section\t__ex_table,\"a\"\n\t" \
588 STR(PTR)"\t1b, 4b\n\t" \
589 STR(PTR)"\t2b, 4b\n\t" \
591 : "=&r" (value), "=r" (res) \
592 : "r" (addr), "i" (-EFAULT)); \
595 #ifndef CONFIG_CPU_MIPSR6
596 #define _LoadWU(addr, value, res, type) \
598 __asm__ __volatile__ ( \
599 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
600 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
601 "dsll\t%0, %0, 32\n\t" \
602 "dsrl\t%0, %0, 32\n\t" \
606 "\t.section\t.fixup,\"ax\"\n\t" \
607 "4:\tli\t%1, %3\n\t" \
610 ".section\t__ex_table,\"a\"\n\t" \
611 STR(PTR)"\t1b, 4b\n\t" \
612 STR(PTR)"\t2b, 4b\n\t" \
614 : "=&r" (value), "=r" (res) \
615 : "r" (addr), "i" (-EFAULT)); \
618 #define _LoadDW(addr, value, res) \
620 __asm__ __volatile__ ( \
621 "1:\tldl\t%0, 7(%2)\n" \
622 "2:\tldr\t%0, (%2)\n\t" \
626 "\t.section\t.fixup,\"ax\"\n\t" \
627 "4:\tli\t%1, %3\n\t" \
630 ".section\t__ex_table,\"a\"\n\t" \
631 STR(PTR)"\t1b, 4b\n\t" \
632 STR(PTR)"\t2b, 4b\n\t" \
634 : "=&r" (value), "=r" (res) \
635 : "r" (addr), "i" (-EFAULT)); \
639 /* MIPSR6 has not lwl and ldl instructions */
640 #define _LoadWU(addr, value, res, type) \
642 __asm__ __volatile__ ( \
645 "1:"type##_lbu("%0", "3(%2)")"\n\t" \
646 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
649 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
652 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
659 ".section\t.fixup,\"ax\"\n\t" \
660 "11:\tli\t%1, %3\n\t" \
663 ".section\t__ex_table,\"a\"\n\t" \
664 STR(PTR)"\t1b, 11b\n\t" \
665 STR(PTR)"\t2b, 11b\n\t" \
666 STR(PTR)"\t3b, 11b\n\t" \
667 STR(PTR)"\t4b, 11b\n\t" \
669 : "=&r" (value), "=r" (res) \
670 : "r" (addr), "i" (-EFAULT)); \
673 #define _LoadDW(addr, value, res) \
675 __asm__ __volatile__ ( \
678 "1:lb\t%0, 7(%2)\n\t" \
679 "2:lbu\t$1, 6(%2)\n\t" \
680 "dsll\t%0, 0x8\n\t" \
682 "3:lbu\t$1, 5(%2)\n\t" \
683 "dsll\t%0, 0x8\n\t" \
685 "4:lbu\t$1, 4(%2)\n\t" \
686 "dsll\t%0, 0x8\n\t" \
688 "5:lbu\t$1, 3(%2)\n\t" \
689 "dsll\t%0, 0x8\n\t" \
691 "6:lbu\t$1, 2(%2)\n\t" \
692 "dsll\t%0, 0x8\n\t" \
694 "7:lbu\t$1, 1(%2)\n\t" \
695 "dsll\t%0, 0x8\n\t" \
697 "8:lbu\t$1, 0(%2)\n\t" \
698 "dsll\t%0, 0x8\n\t" \
704 ".section\t.fixup,\"ax\"\n\t" \
705 "11:\tli\t%1, %3\n\t" \
708 ".section\t__ex_table,\"a\"\n\t" \
709 STR(PTR)"\t1b, 11b\n\t" \
710 STR(PTR)"\t2b, 11b\n\t" \
711 STR(PTR)"\t3b, 11b\n\t" \
712 STR(PTR)"\t4b, 11b\n\t" \
713 STR(PTR)"\t5b, 11b\n\t" \
714 STR(PTR)"\t6b, 11b\n\t" \
715 STR(PTR)"\t7b, 11b\n\t" \
716 STR(PTR)"\t8b, 11b\n\t" \
718 : "=&r" (value), "=r" (res) \
719 : "r" (addr), "i" (-EFAULT)); \
721 #endif /* CONFIG_CPU_MIPSR6 */
723 #define _StoreHW(addr, value, res, type) \
725 __asm__ __volatile__ ( \
727 "1:\t"type##_sb("%1", "0(%2)")"\n" \
728 "srl\t$1,%1, 0x8\n" \
729 "2:\t"type##_sb("$1", "1(%2)")"\n" \
734 ".section\t.fixup,\"ax\"\n\t" \
735 "4:\tli\t%0, %3\n\t" \
738 ".section\t__ex_table,\"a\"\n\t" \
739 STR(PTR)"\t1b, 4b\n\t" \
740 STR(PTR)"\t2b, 4b\n\t" \
743 : "r" (value), "r" (addr), "i" (-EFAULT));\
746 #ifndef CONFIG_CPU_MIPSR6
747 #define _StoreW(addr, value, res, type) \
749 __asm__ __volatile__ ( \
750 "1:\t"type##_swl("%1", "3(%2)")"\n" \
751 "2:\t"type##_swr("%1", "(%2)")"\n\t"\
755 ".section\t.fixup,\"ax\"\n\t" \
756 "4:\tli\t%0, %3\n\t" \
759 ".section\t__ex_table,\"a\"\n\t" \
760 STR(PTR)"\t1b, 4b\n\t" \
761 STR(PTR)"\t2b, 4b\n\t" \
764 : "r" (value), "r" (addr), "i" (-EFAULT)); \
767 #define _StoreDW(addr, value, res) \
769 __asm__ __volatile__ ( \
770 "1:\tsdl\t%1, 7(%2)\n" \
771 "2:\tsdr\t%1, (%2)\n\t" \
775 ".section\t.fixup,\"ax\"\n\t" \
776 "4:\tli\t%0, %3\n\t" \
779 ".section\t__ex_table,\"a\"\n\t" \
780 STR(PTR)"\t1b, 4b\n\t" \
781 STR(PTR)"\t2b, 4b\n\t" \
784 : "r" (value), "r" (addr), "i" (-EFAULT)); \
788 /* MIPSR6 has no swl and sdl instructions */
789 #define _StoreW(addr, value, res, type) \
791 __asm__ __volatile__ ( \
794 "1:"type##_sb("%1", "0(%2)")"\n\t" \
795 "srl\t$1, %1, 0x8\n\t" \
796 "2:"type##_sb("$1", "1(%2)")"\n\t" \
797 "srl\t$1, $1, 0x8\n\t" \
798 "3:"type##_sb("$1", "2(%2)")"\n\t" \
799 "srl\t$1, $1, 0x8\n\t" \
800 "4:"type##_sb("$1", "3(%2)")"\n\t" \
805 ".section\t.fixup,\"ax\"\n\t" \
806 "11:\tli\t%0, %3\n\t" \
809 ".section\t__ex_table,\"a\"\n\t" \
810 STR(PTR)"\t1b, 11b\n\t" \
811 STR(PTR)"\t2b, 11b\n\t" \
812 STR(PTR)"\t3b, 11b\n\t" \
813 STR(PTR)"\t4b, 11b\n\t" \
816 : "r" (value), "r" (addr), "i" (-EFAULT) \
820 #define _StoreDW(addr, value, res) \
822 __asm__ __volatile__ ( \
825 "1:sb\t%1, 0(%2)\n\t" \
826 "dsrl\t$1, %1, 0x8\n\t" \
827 "2:sb\t$1, 1(%2)\n\t" \
828 "dsrl\t$1, $1, 0x8\n\t" \
829 "3:sb\t$1, 2(%2)\n\t" \
830 "dsrl\t$1, $1, 0x8\n\t" \
831 "4:sb\t$1, 3(%2)\n\t" \
832 "dsrl\t$1, $1, 0x8\n\t" \
833 "5:sb\t$1, 4(%2)\n\t" \
834 "dsrl\t$1, $1, 0x8\n\t" \
835 "6:sb\t$1, 5(%2)\n\t" \
836 "dsrl\t$1, $1, 0x8\n\t" \
837 "7:sb\t$1, 6(%2)\n\t" \
838 "dsrl\t$1, $1, 0x8\n\t" \
839 "8:sb\t$1, 7(%2)\n\t" \
840 "dsrl\t$1, $1, 0x8\n\t" \
845 ".section\t.fixup,\"ax\"\n\t" \
846 "11:\tli\t%0, %3\n\t" \
849 ".section\t__ex_table,\"a\"\n\t" \
850 STR(PTR)"\t1b, 11b\n\t" \
851 STR(PTR)"\t2b, 11b\n\t" \
852 STR(PTR)"\t3b, 11b\n\t" \
853 STR(PTR)"\t4b, 11b\n\t" \
854 STR(PTR)"\t5b, 11b\n\t" \
855 STR(PTR)"\t6b, 11b\n\t" \
856 STR(PTR)"\t7b, 11b\n\t" \
857 STR(PTR)"\t8b, 11b\n\t" \
860 : "r" (value), "r" (addr), "i" (-EFAULT) \
864 #endif /* CONFIG_CPU_MIPSR6 */
867 #define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
868 #define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
869 #define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
870 #define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
871 #define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
872 #define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
873 #define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
874 #define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
875 #define LoadDW(addr, value, res) _LoadDW(addr, value, res)
877 #define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
878 #define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
879 #define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
880 #define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
881 #define StoreDW(addr, value, res) _StoreDW(addr, value, res)
883 static void emulate_load_store_insn(struct pt_regs *regs,
884 void __user *addr, unsigned int __user *pc)
886 union mips_instruction insn;
888 unsigned int res, preempted;
889 unsigned long origpc;
890 unsigned long orig31;
891 void __user *fault_addr = NULL;
898 origpc = (unsigned long)pc;
899 orig31 = regs->regs[31];
901 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
904 * This load never faults.
906 __get_user(insn.word, pc);
908 switch (insn.i_format.opcode) {
910 * These are instructions that a compiler doesn't generate. We
911 * can assume therefore that the code is MIPS-aware and
912 * really buggy. Emulating these instructions would break the
921 * For these instructions the only way to create an address
922 * error is an attempted access to kernel/supervisor address
939 * The remaining opcodes are the ones that are really of
945 * we can land here only from kernel accessing user memory,
946 * so we need to "switch" the address limit to user space, so
947 * address check can work properly.
951 switch (insn.spec3_format.func) {
953 if (!access_ok(VERIFY_READ, addr, 2)) {
957 LoadHWE(addr, value, res);
962 compute_return_epc(regs);
963 regs->regs[insn.spec3_format.rt] = value;
966 if (!access_ok(VERIFY_READ, addr, 4)) {
970 LoadWE(addr, value, res);
975 compute_return_epc(regs);
976 regs->regs[insn.spec3_format.rt] = value;
979 if (!access_ok(VERIFY_READ, addr, 2)) {
983 LoadHWUE(addr, value, res);
988 compute_return_epc(regs);
989 regs->regs[insn.spec3_format.rt] = value;
992 if (!access_ok(VERIFY_WRITE, addr, 2)) {
996 compute_return_epc(regs);
997 value = regs->regs[insn.spec3_format.rt];
998 StoreHWE(addr, value, res);
1005 if (!access_ok(VERIFY_WRITE, addr, 4)) {
1009 compute_return_epc(regs);
1010 value = regs->regs[insn.spec3_format.rt];
1011 StoreWE(addr, value, res);
1025 if (!access_ok(VERIFY_READ, addr, 2))
1028 if (IS_ENABLED(CONFIG_EVA)) {
1029 if (segment_eq(get_fs(), get_ds()))
1030 LoadHW(addr, value, res);
1032 LoadHWE(addr, value, res);
1034 LoadHW(addr, value, res);
1039 compute_return_epc(regs);
1040 regs->regs[insn.i_format.rt] = value;
1044 if (!access_ok(VERIFY_READ, addr, 4))
1047 if (IS_ENABLED(CONFIG_EVA)) {
1048 if (segment_eq(get_fs(), get_ds()))
1049 LoadW(addr, value, res);
1051 LoadWE(addr, value, res);
1053 LoadW(addr, value, res);
1058 compute_return_epc(regs);
1059 regs->regs[insn.i_format.rt] = value;
1063 if (!access_ok(VERIFY_READ, addr, 2))
1066 if (IS_ENABLED(CONFIG_EVA)) {
1067 if (segment_eq(get_fs(), get_ds()))
1068 LoadHWU(addr, value, res);
1070 LoadHWUE(addr, value, res);
1072 LoadHWU(addr, value, res);
1077 compute_return_epc(regs);
1078 regs->regs[insn.i_format.rt] = value;
1084 * A 32-bit kernel might be running on a 64-bit processor. But
1085 * if we're on a 32-bit processor and an i-cache incoherency
1086 * or race makes us see a 64-bit instruction here the sdl/sdr
1087 * would blow up, so for now we don't handle unaligned 64-bit
1088 * instructions on 32-bit kernels.
1090 if (!access_ok(VERIFY_READ, addr, 4))
1093 LoadWU(addr, value, res);
1096 compute_return_epc(regs);
1097 regs->regs[insn.i_format.rt] = value;
1099 #endif /* CONFIG_64BIT */
1101 /* Cannot handle 64-bit instructions in 32-bit kernel */
1107 * A 32-bit kernel might be running on a 64-bit processor. But
1108 * if we're on a 32-bit processor and an i-cache incoherency
1109 * or race makes us see a 64-bit instruction here the sdl/sdr
1110 * would blow up, so for now we don't handle unaligned 64-bit
1111 * instructions on 32-bit kernels.
1113 if (!access_ok(VERIFY_READ, addr, 8))
1116 LoadDW(addr, value, res);
1119 compute_return_epc(regs);
1120 regs->regs[insn.i_format.rt] = value;
1122 #endif /* CONFIG_64BIT */
1124 /* Cannot handle 64-bit instructions in 32-bit kernel */
1128 if (!access_ok(VERIFY_WRITE, addr, 2))
1131 compute_return_epc(regs);
1132 value = regs->regs[insn.i_format.rt];
1134 if (IS_ENABLED(CONFIG_EVA)) {
1135 if (segment_eq(get_fs(), get_ds()))
1136 StoreHW(addr, value, res);
1138 StoreHWE(addr, value, res);
1140 StoreHW(addr, value, res);
1148 if (!access_ok(VERIFY_WRITE, addr, 4))
1151 compute_return_epc(regs);
1152 value = regs->regs[insn.i_format.rt];
1154 if (IS_ENABLED(CONFIG_EVA)) {
1155 if (segment_eq(get_fs(), get_ds()))
1156 StoreW(addr, value, res);
1158 StoreWE(addr, value, res);
1160 StoreW(addr, value, res);
1170 * A 32-bit kernel might be running on a 64-bit processor. But
1171 * if we're on a 32-bit processor and an i-cache incoherency
1172 * or race makes us see a 64-bit instruction here the sdl/sdr
1173 * would blow up, so for now we don't handle unaligned 64-bit
1174 * instructions on 32-bit kernels.
1176 if (!access_ok(VERIFY_WRITE, addr, 8))
1179 compute_return_epc(regs);
1180 value = regs->regs[insn.i_format.rt];
1181 StoreDW(addr, value, res);
1185 #endif /* CONFIG_64BIT */
1187 /* Cannot handle 64-bit instructions in 32-bit kernel */
1195 die_if_kernel("Unaligned FP access in kernel code", regs);
1196 BUG_ON(!used_math());
1198 lose_fpu(1); /* Save FPU state for the emulator. */
1199 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1201 own_fpu(1); /* Restore FPU state. */
1203 /* Signal if something went wrong. */
1204 process_fpemu_return(res, fault_addr, 0);
1215 * If we've reached this point then userland should have taken
1216 * the MSA disabled exception & initialised vector context at
1217 * some point in the past.
1219 BUG_ON(!thread_msa_context_live());
1221 df = insn.msa_mi10_format.df;
1222 wd = insn.msa_mi10_format.wd;
1223 fpr = ¤t->thread.fpu.fpr[wd];
1225 switch (insn.msa_mi10_format.func) {
1227 if (!access_ok(VERIFY_READ, addr, sizeof(*fpr)))
1232 * If we have live MSA context keep track of
1233 * whether we get preempted in order to avoid
1234 * the register context we load being clobbered
1235 * by the live context as it's saved during
1236 * preemption. If we don't have live context
1237 * then it can't be saved to clobber the value
1240 preempted = test_thread_flag(TIF_USEDMSA);
1242 res = __copy_from_user_inatomic(fpr, addr,
1248 * Update the hardware register if it is in use
1249 * by the task in this quantum, in order to
1250 * avoid having to save & restore the whole
1254 if (test_thread_flag(TIF_USEDMSA)) {
1255 write_msa_wr(wd, fpr, df);
1259 } while (preempted);
1263 if (!access_ok(VERIFY_WRITE, addr, sizeof(*fpr)))
1267 * Update from the hardware register if it is in use by
1268 * the task in this quantum, in order to avoid having to
1269 * save & restore the whole vector context.
1272 if (test_thread_flag(TIF_USEDMSA))
1273 read_msa_wr(wd, fpr, df);
1276 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr));
1285 compute_return_epc(regs);
1288 #ifndef CONFIG_CPU_MIPSR6
1290 * COP2 is available to implementor for application specific use.
1291 * It's up to applications to register a notifier chain and do
1292 * whatever they have to do, including possible sending of signals.
1294 * This instruction has been reallocated in Release 6
1297 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
1301 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
1305 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
1309 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
1314 * Pheeee... We encountered an yet unknown instruction or
1315 * cache coherence problem. Die sucker, die ...
1320 #ifdef CONFIG_DEBUG_FS
1321 unaligned_instructions++;
1327 /* roll back jump/branch */
1328 regs->cp0_epc = origpc;
1329 regs->regs[31] = orig31;
1330 /* Did we have an exception handler installed? */
1331 if (fixup_exception(regs))
1334 die_if_kernel("Unhandled kernel unaligned access", regs);
1335 force_sig(SIGSEGV, current);
1340 die_if_kernel("Unhandled kernel unaligned access", regs);
1341 force_sig(SIGBUS, current);
1347 ("Unhandled kernel unaligned access or invalid instruction", regs);
1348 force_sig(SIGILL, current);
1351 /* Recode table from 16-bit register notation to 32-bit GPR. */
1352 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
1354 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1355 const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
1357 static void emulate_load_store_microMIPS(struct pt_regs *regs,
1360 unsigned long value;
1363 unsigned int reg = 0, rvar;
1364 unsigned long orig31;
1368 unsigned long origpc, contpc;
1369 union mips_instruction insn;
1370 struct mm_decoded_insn mminsn;
1371 void __user *fault_addr = NULL;
1373 origpc = regs->cp0_epc;
1374 orig31 = regs->regs[31];
1376 mminsn.micro_mips_mode = 1;
1379 * This load never faults.
1381 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
1382 __get_user(halfword, pc16);
1384 contpc = regs->cp0_epc + 2;
1385 word = ((unsigned int)halfword << 16);
1388 if (!mm_insn_16bit(halfword)) {
1389 __get_user(halfword, pc16);
1391 contpc = regs->cp0_epc + 4;
1397 if (get_user(halfword, pc16))
1399 mminsn.next_pc_inc = 2;
1400 word = ((unsigned int)halfword << 16);
1402 if (!mm_insn_16bit(halfword)) {
1404 if (get_user(halfword, pc16))
1406 mminsn.next_pc_inc = 4;
1409 mminsn.next_insn = word;
1411 insn = (union mips_instruction)(mminsn.insn);
1412 if (mm_isBranchInstr(regs, mminsn, &contpc))
1413 insn = (union mips_instruction)(mminsn.next_insn);
1415 /* Parse instruction to find what to do */
1417 switch (insn.mm_i_format.opcode) {
1420 switch (insn.mm_x_format.func) {
1422 reg = insn.mm_x_format.rd;
1429 switch (insn.mm_m_format.func) {
1431 reg = insn.mm_m_format.rd;
1435 if (!access_ok(VERIFY_READ, addr, 8))
1438 LoadW(addr, value, res);
1441 regs->regs[reg] = value;
1443 LoadW(addr, value, res);
1446 regs->regs[reg + 1] = value;
1450 reg = insn.mm_m_format.rd;
1454 if (!access_ok(VERIFY_WRITE, addr, 8))
1457 value = regs->regs[reg];
1458 StoreW(addr, value, res);
1462 value = regs->regs[reg + 1];
1463 StoreW(addr, value, res);
1470 reg = insn.mm_m_format.rd;
1474 if (!access_ok(VERIFY_READ, addr, 16))
1477 LoadDW(addr, value, res);
1480 regs->regs[reg] = value;
1482 LoadDW(addr, value, res);
1485 regs->regs[reg + 1] = value;
1487 #endif /* CONFIG_64BIT */
1493 reg = insn.mm_m_format.rd;
1497 if (!access_ok(VERIFY_WRITE, addr, 16))
1500 value = regs->regs[reg];
1501 StoreDW(addr, value, res);
1505 value = regs->regs[reg + 1];
1506 StoreDW(addr, value, res);
1510 #endif /* CONFIG_64BIT */
1515 reg = insn.mm_m_format.rd;
1517 if ((rvar > 9) || !reg)
1521 (VERIFY_READ, addr, 4 * (rvar + 1)))
1524 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1529 for (i = 16; rvar; rvar--, i++) {
1530 LoadW(addr, value, res);
1534 regs->regs[i] = value;
1536 if ((reg & 0xf) == 9) {
1537 LoadW(addr, value, res);
1541 regs->regs[30] = value;
1544 LoadW(addr, value, res);
1547 regs->regs[31] = value;
1552 reg = insn.mm_m_format.rd;
1554 if ((rvar > 9) || !reg)
1558 (VERIFY_WRITE, addr, 4 * (rvar + 1)))
1561 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1566 for (i = 16; rvar; rvar--, i++) {
1567 value = regs->regs[i];
1568 StoreW(addr, value, res);
1573 if ((reg & 0xf) == 9) {
1574 value = regs->regs[30];
1575 StoreW(addr, value, res);
1581 value = regs->regs[31];
1582 StoreW(addr, value, res);
1590 reg = insn.mm_m_format.rd;
1592 if ((rvar > 9) || !reg)
1596 (VERIFY_READ, addr, 8 * (rvar + 1)))
1599 if (!access_ok(VERIFY_READ, addr, 8 * rvar))
1605 for (i = 16; rvar; rvar--, i++) {
1606 LoadDW(addr, value, res);
1610 regs->regs[i] = value;
1612 if ((reg & 0xf) == 9) {
1613 LoadDW(addr, value, res);
1617 regs->regs[30] = value;
1620 LoadDW(addr, value, res);
1623 regs->regs[31] = value;
1626 #endif /* CONFIG_64BIT */
1632 reg = insn.mm_m_format.rd;
1634 if ((rvar > 9) || !reg)
1638 (VERIFY_WRITE, addr, 8 * (rvar + 1)))
1641 if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
1647 for (i = 16; rvar; rvar--, i++) {
1648 value = regs->regs[i];
1649 StoreDW(addr, value, res);
1654 if ((reg & 0xf) == 9) {
1655 value = regs->regs[30];
1656 StoreDW(addr, value, res);
1662 value = regs->regs[31];
1663 StoreDW(addr, value, res);
1668 #endif /* CONFIG_64BIT */
1672 /* LWC2, SWC2, LDC2, SDC2 are not serviced */
1678 switch (insn.mm_m_format.func) {
1680 reg = insn.mm_m_format.rd;
1684 /* LL,SC,LLD,SCD are not serviced */
1688 switch (insn.mm_x_format.func) {
1703 /* roll back jump/branch */
1704 regs->cp0_epc = origpc;
1705 regs->regs[31] = orig31;
1707 die_if_kernel("Unaligned FP access in kernel code", regs);
1708 BUG_ON(!used_math());
1709 BUG_ON(!is_fpu_owner());
1711 lose_fpu(1); /* save the FPU state for the emulator */
1712 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1714 own_fpu(1); /* restore FPU state */
1716 /* If something went wrong, signal */
1717 process_fpemu_return(res, fault_addr, 0);
1724 reg = insn.mm_i_format.rt;
1728 reg = insn.mm_i_format.rt;
1732 reg = insn.mm_i_format.rt;
1736 reg = insn.mm_i_format.rt;
1740 reg = insn.mm_i_format.rt;
1744 reg = insn.mm_i_format.rt;
1748 reg = insn.mm_i_format.rt;
1752 switch (insn.mm16_m_format.func) {
1754 reg = insn.mm16_m_format.rlist;
1756 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1759 for (i = 16; rvar; rvar--, i++) {
1760 LoadW(addr, value, res);
1764 regs->regs[i] = value;
1766 LoadW(addr, value, res);
1769 regs->regs[31] = value;
1774 reg = insn.mm16_m_format.rlist;
1776 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1779 for (i = 16; rvar; rvar--, i++) {
1780 value = regs->regs[i];
1781 StoreW(addr, value, res);
1786 value = regs->regs[31];
1787 StoreW(addr, value, res);
1798 reg = reg16to32[insn.mm16_rb_format.rt];
1802 reg = reg16to32[insn.mm16_rb_format.rt];
1806 reg = reg16to32st[insn.mm16_rb_format.rt];
1810 reg = reg16to32st[insn.mm16_rb_format.rt];
1814 reg = insn.mm16_r5_format.rt;
1818 reg = insn.mm16_r5_format.rt;
1822 reg = reg16to32[insn.mm16_r3_format.rt];
1830 if (!access_ok(VERIFY_READ, addr, 2))
1833 LoadHW(addr, value, res);
1836 regs->regs[reg] = value;
1840 if (!access_ok(VERIFY_READ, addr, 2))
1843 LoadHWU(addr, value, res);
1846 regs->regs[reg] = value;
1850 if (!access_ok(VERIFY_READ, addr, 4))
1853 LoadW(addr, value, res);
1856 regs->regs[reg] = value;
1862 * A 32-bit kernel might be running on a 64-bit processor. But
1863 * if we're on a 32-bit processor and an i-cache incoherency
1864 * or race makes us see a 64-bit instruction here the sdl/sdr
1865 * would blow up, so for now we don't handle unaligned 64-bit
1866 * instructions on 32-bit kernels.
1868 if (!access_ok(VERIFY_READ, addr, 4))
1871 LoadWU(addr, value, res);
1874 regs->regs[reg] = value;
1876 #endif /* CONFIG_64BIT */
1878 /* Cannot handle 64-bit instructions in 32-bit kernel */
1884 * A 32-bit kernel might be running on a 64-bit processor. But
1885 * if we're on a 32-bit processor and an i-cache incoherency
1886 * or race makes us see a 64-bit instruction here the sdl/sdr
1887 * would blow up, so for now we don't handle unaligned 64-bit
1888 * instructions on 32-bit kernels.
1890 if (!access_ok(VERIFY_READ, addr, 8))
1893 LoadDW(addr, value, res);
1896 regs->regs[reg] = value;
1898 #endif /* CONFIG_64BIT */
1900 /* Cannot handle 64-bit instructions in 32-bit kernel */
1904 if (!access_ok(VERIFY_WRITE, addr, 2))
1907 value = regs->regs[reg];
1908 StoreHW(addr, value, res);
1914 if (!access_ok(VERIFY_WRITE, addr, 4))
1917 value = regs->regs[reg];
1918 StoreW(addr, value, res);
1926 * A 32-bit kernel might be running on a 64-bit processor. But
1927 * if we're on a 32-bit processor and an i-cache incoherency
1928 * or race makes us see a 64-bit instruction here the sdl/sdr
1929 * would blow up, so for now we don't handle unaligned 64-bit
1930 * instructions on 32-bit kernels.
1932 if (!access_ok(VERIFY_WRITE, addr, 8))
1935 value = regs->regs[reg];
1936 StoreDW(addr, value, res);
1940 #endif /* CONFIG_64BIT */
1942 /* Cannot handle 64-bit instructions in 32-bit kernel */
1946 regs->cp0_epc = contpc; /* advance or branch */
1948 #ifdef CONFIG_DEBUG_FS
1949 unaligned_instructions++;
1954 /* roll back jump/branch */
1955 regs->cp0_epc = origpc;
1956 regs->regs[31] = orig31;
1957 /* Did we have an exception handler installed? */
1958 if (fixup_exception(regs))
1961 die_if_kernel("Unhandled kernel unaligned access", regs);
1962 force_sig(SIGSEGV, current);
1967 die_if_kernel("Unhandled kernel unaligned access", regs);
1968 force_sig(SIGBUS, current);
1974 ("Unhandled kernel unaligned access or invalid instruction", regs);
1975 force_sig(SIGILL, current);
1978 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1980 unsigned long value;
1983 unsigned long orig31;
1985 unsigned long origpc;
1986 union mips16e_instruction mips16inst, oldinst;
1988 origpc = regs->cp0_epc;
1989 orig31 = regs->regs[31];
1990 pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1992 * This load never faults.
1994 __get_user(mips16inst.full, pc16);
1995 oldinst = mips16inst;
1997 /* skip EXTEND instruction */
1998 if (mips16inst.ri.opcode == MIPS16e_extend_op) {
2000 __get_user(mips16inst.full, pc16);
2001 } else if (delay_slot(regs)) {
2002 /* skip jump instructions */
2003 /* JAL/JALX are 32 bits but have OPCODE in first short int */
2004 if (mips16inst.ri.opcode == MIPS16e_jal_op)
2007 if (get_user(mips16inst.full, pc16))
2011 switch (mips16inst.ri.opcode) {
2012 case MIPS16e_i64_op: /* I64 or RI64 instruction */
2013 switch (mips16inst.i64.func) { /* I64/RI64 func field check */
2014 case MIPS16e_ldpc_func:
2015 case MIPS16e_ldsp_func:
2016 reg = reg16to32[mips16inst.ri64.ry];
2019 case MIPS16e_sdsp_func:
2020 reg = reg16to32[mips16inst.ri64.ry];
2023 case MIPS16e_sdrasp_func:
2024 reg = 29; /* GPRSP */
2030 case MIPS16e_swsp_op:
2031 case MIPS16e_lwpc_op:
2032 case MIPS16e_lwsp_op:
2033 reg = reg16to32[mips16inst.ri.rx];
2037 if (mips16inst.i8.func != MIPS16e_swrasp_func)
2039 reg = 29; /* GPRSP */
2043 reg = reg16to32[mips16inst.rri.ry];
2047 switch (mips16inst.ri.opcode) {
2050 case MIPS16e_lbu_op:
2055 if (!access_ok(VERIFY_READ, addr, 2))
2058 LoadHW(addr, value, res);
2061 MIPS16e_compute_return_epc(regs, &oldinst);
2062 regs->regs[reg] = value;
2065 case MIPS16e_lhu_op:
2066 if (!access_ok(VERIFY_READ, addr, 2))
2069 LoadHWU(addr, value, res);
2072 MIPS16e_compute_return_epc(regs, &oldinst);
2073 regs->regs[reg] = value;
2077 case MIPS16e_lwpc_op:
2078 case MIPS16e_lwsp_op:
2079 if (!access_ok(VERIFY_READ, addr, 4))
2082 LoadW(addr, value, res);
2085 MIPS16e_compute_return_epc(regs, &oldinst);
2086 regs->regs[reg] = value;
2089 case MIPS16e_lwu_op:
2092 * A 32-bit kernel might be running on a 64-bit processor. But
2093 * if we're on a 32-bit processor and an i-cache incoherency
2094 * or race makes us see a 64-bit instruction here the sdl/sdr
2095 * would blow up, so for now we don't handle unaligned 64-bit
2096 * instructions on 32-bit kernels.
2098 if (!access_ok(VERIFY_READ, addr, 4))
2101 LoadWU(addr, value, res);
2104 MIPS16e_compute_return_epc(regs, &oldinst);
2105 regs->regs[reg] = value;
2107 #endif /* CONFIG_64BIT */
2109 /* Cannot handle 64-bit instructions in 32-bit kernel */
2116 * A 32-bit kernel might be running on a 64-bit processor. But
2117 * if we're on a 32-bit processor and an i-cache incoherency
2118 * or race makes us see a 64-bit instruction here the sdl/sdr
2119 * would blow up, so for now we don't handle unaligned 64-bit
2120 * instructions on 32-bit kernels.
2122 if (!access_ok(VERIFY_READ, addr, 8))
2125 LoadDW(addr, value, res);
2128 MIPS16e_compute_return_epc(regs, &oldinst);
2129 regs->regs[reg] = value;
2131 #endif /* CONFIG_64BIT */
2133 /* Cannot handle 64-bit instructions in 32-bit kernel */
2137 if (!access_ok(VERIFY_WRITE, addr, 2))
2140 MIPS16e_compute_return_epc(regs, &oldinst);
2141 value = regs->regs[reg];
2142 StoreHW(addr, value, res);
2148 case MIPS16e_swsp_op:
2149 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
2150 if (!access_ok(VERIFY_WRITE, addr, 4))
2153 MIPS16e_compute_return_epc(regs, &oldinst);
2154 value = regs->regs[reg];
2155 StoreW(addr, value, res);
2164 * A 32-bit kernel might be running on a 64-bit processor. But
2165 * if we're on a 32-bit processor and an i-cache incoherency
2166 * or race makes us see a 64-bit instruction here the sdl/sdr
2167 * would blow up, so for now we don't handle unaligned 64-bit
2168 * instructions on 32-bit kernels.
2170 if (!access_ok(VERIFY_WRITE, addr, 8))
2173 MIPS16e_compute_return_epc(regs, &oldinst);
2174 value = regs->regs[reg];
2175 StoreDW(addr, value, res);
2179 #endif /* CONFIG_64BIT */
2181 /* Cannot handle 64-bit instructions in 32-bit kernel */
2186 * Pheeee... We encountered an yet unknown instruction or
2187 * cache coherence problem. Die sucker, die ...
2192 #ifdef CONFIG_DEBUG_FS
2193 unaligned_instructions++;
2199 /* roll back jump/branch */
2200 regs->cp0_epc = origpc;
2201 regs->regs[31] = orig31;
2202 /* Did we have an exception handler installed? */
2203 if (fixup_exception(regs))
2206 die_if_kernel("Unhandled kernel unaligned access", regs);
2207 force_sig(SIGSEGV, current);
2212 die_if_kernel("Unhandled kernel unaligned access", regs);
2213 force_sig(SIGBUS, current);
2219 ("Unhandled kernel unaligned access or invalid instruction", regs);
2220 force_sig(SIGILL, current);
2223 asmlinkage void do_ade(struct pt_regs *regs)
2225 enum ctx_state prev_state;
2226 unsigned int __user *pc;
2229 prev_state = exception_enter();
2230 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
2231 1, regs, regs->cp0_badvaddr);
2233 * Did we catch a fault trying to load an instruction?
2235 if (regs->cp0_badvaddr == regs->cp0_epc)
2238 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
2240 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
2244 * Do branch emulation only if we didn't forward the exception.
2245 * This is all so but ugly ...
2249 * Are we running in microMIPS mode?
2251 if (get_isa16_mode(regs->cp0_epc)) {
2253 * Did we catch a fault trying to load an instruction in
2256 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
2258 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2259 show_registers(regs);
2261 if (cpu_has_mmips) {
2263 if (!user_mode(regs))
2265 emulate_load_store_microMIPS(regs,
2266 (void __user *)regs->cp0_badvaddr);
2272 if (cpu_has_mips16) {
2274 if (!user_mode(regs))
2276 emulate_load_store_MIPS16e(regs,
2277 (void __user *)regs->cp0_badvaddr);
2286 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2287 show_registers(regs);
2288 pc = (unsigned int __user *)exception_epc(regs);
2291 if (!user_mode(regs))
2293 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
2299 die_if_kernel("Kernel unaligned instruction access", regs);
2300 force_sig(SIGBUS, current);
2303 * XXX On return from the signal handler we should advance the epc
2305 exception_exit(prev_state);
2308 #ifdef CONFIG_DEBUG_FS
2309 static int __init debugfs_unaligned(void)
2313 if (!mips_debugfs_dir)
2315 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
2316 mips_debugfs_dir, &unaligned_instructions);
2319 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
2320 mips_debugfs_dir, &unaligned_action);
2325 arch_initcall(debugfs_unaligned);