2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 * This file contains exception handler for address error exception with the
12 * special capability to execute faulting instructions in software. The
13 * handler does not try to handle the case when the program counter points
14 * to an address not aligned to a word boundary.
16 * Putting data to unaligned addresses is a bad practice even on Intel where
17 * only the performance is affected. Much worse is that such code is non-
18 * portable. Due to several programs that die on MIPS due to alignment
19 * problems I decided to implement this handler anyway though I originally
20 * didn't intend to do this at all for user code.
22 * For now I enable fixing of address errors by default to make life easier.
23 * I however intend to disable this somewhen in the future when the alignment
24 * problems with user programs have been fixed. For programmers this is the
27 * Fixing address errors is a per process option. The option is inherited
28 * across fork(2) and execve(2) calls. If you really want to use the
29 * option in your user programs - I discourage the use of the software
30 * emulation strongly - use the following code in your userland stuff:
32 * #include <sys/sysmips.h>
35 * sysmips(MIPS_FIXADE, x);
38 * The argument x is 0 for disabling software emulation, enabled otherwise.
40 * Below a little program to play around with this feature.
43 * #include <sys/sysmips.h>
46 * unsigned char bar[8];
49 * main(int argc, char *argv[])
51 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
52 * unsigned int *p = (unsigned int *) (x.bar + 3);
56 * sysmips(MIPS_FIXADE, atoi(argv[1]));
58 * printf("*p = %08lx\n", *p);
62 * for(i = 0; i <= 7; i++)
63 * printf("%02x ", x.bar[i]);
67 * Coprocessor loads are not supported; I think this case is unimportant
70 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
71 * exception for the R6000.
72 * A store crossing a page boundary might be executed only partially.
73 * Undo the partial store in this case.
76 #include <linux/module.h>
77 #include <linux/signal.h>
78 #include <linux/smp.h>
79 #include <linux/sched.h>
80 #include <linux/debugfs.h>
82 #include <asm/branch.h>
83 #include <asm/byteorder.h>
86 #include <asm/uaccess.h>
87 #include <asm/system.h>
89 #define STR(x) __STR(x)
93 UNALIGNED_ACTION_QUIET,
94 UNALIGNED_ACTION_SIGNAL,
95 UNALIGNED_ACTION_SHOW,
97 #ifdef CONFIG_DEBUG_FS
98 static u32 unaligned_instructions;
99 static u32 unaligned_action;
101 #define unaligned_action UNALIGNED_ACTION_QUIET
103 extern void show_registers(struct pt_regs *regs);
105 static void emulate_load_store_insn(struct pt_regs *regs,
106 void __user *addr, unsigned int __user *pc)
108 union mips_instruction insn;
113 * This load never faults.
115 __get_user(insn.word, pc);
117 switch (insn.i_format.opcode) {
119 * These are instructions that a compiler doesn't generate. We
120 * can assume therefore that the code is MIPS-aware and
121 * really buggy. Emulating these instructions would break the
130 * For these instructions the only way to create an address
131 * error is an attempted access to kernel/supervisor address
148 * The remaining opcodes are the ones that are really of interest.
151 if (!access_ok(VERIFY_READ, addr, 2))
154 __asm__ __volatile__ (".set\tnoat\n"
156 "1:\tlb\t%0, 0(%2)\n"
157 "2:\tlbu\t$1, 1(%2)\n\t"
159 #ifdef __LITTLE_ENDIAN
160 "1:\tlb\t%0, 1(%2)\n"
161 "2:\tlbu\t$1, 0(%2)\n\t"
167 ".section\t.fixup,\"ax\"\n\t"
171 ".section\t__ex_table,\"a\"\n\t"
172 STR(PTR)"\t1b, 4b\n\t"
173 STR(PTR)"\t2b, 4b\n\t"
175 : "=&r" (value), "=r" (res)
176 : "r" (addr), "i" (-EFAULT));
179 compute_return_epc(regs);
180 regs->regs[insn.i_format.rt] = value;
184 if (!access_ok(VERIFY_READ, addr, 4))
187 __asm__ __volatile__ (
189 "1:\tlwl\t%0, (%2)\n"
190 "2:\tlwr\t%0, 3(%2)\n\t"
192 #ifdef __LITTLE_ENDIAN
193 "1:\tlwl\t%0, 3(%2)\n"
194 "2:\tlwr\t%0, (%2)\n\t"
197 "3:\t.section\t.fixup,\"ax\"\n\t"
201 ".section\t__ex_table,\"a\"\n\t"
202 STR(PTR)"\t1b, 4b\n\t"
203 STR(PTR)"\t2b, 4b\n\t"
205 : "=&r" (value), "=r" (res)
206 : "r" (addr), "i" (-EFAULT));
209 compute_return_epc(regs);
210 regs->regs[insn.i_format.rt] = value;
214 if (!access_ok(VERIFY_READ, addr, 2))
217 __asm__ __volatile__ (
220 "1:\tlbu\t%0, 0(%2)\n"
221 "2:\tlbu\t$1, 1(%2)\n\t"
223 #ifdef __LITTLE_ENDIAN
224 "1:\tlbu\t%0, 1(%2)\n"
225 "2:\tlbu\t$1, 0(%2)\n\t"
231 ".section\t.fixup,\"ax\"\n\t"
235 ".section\t__ex_table,\"a\"\n\t"
236 STR(PTR)"\t1b, 4b\n\t"
237 STR(PTR)"\t2b, 4b\n\t"
239 : "=&r" (value), "=r" (res)
240 : "r" (addr), "i" (-EFAULT));
243 compute_return_epc(regs);
244 regs->regs[insn.i_format.rt] = value;
250 * A 32-bit kernel might be running on a 64-bit processor. But
251 * if we're on a 32-bit processor and an i-cache incoherency
252 * or race makes us see a 64-bit instruction here the sdl/sdr
253 * would blow up, so for now we don't handle unaligned 64-bit
254 * instructions on 32-bit kernels.
256 if (!access_ok(VERIFY_READ, addr, 4))
259 __asm__ __volatile__ (
261 "1:\tlwl\t%0, (%2)\n"
262 "2:\tlwr\t%0, 3(%2)\n\t"
264 #ifdef __LITTLE_ENDIAN
265 "1:\tlwl\t%0, 3(%2)\n"
266 "2:\tlwr\t%0, (%2)\n\t"
268 "dsll\t%0, %0, 32\n\t"
269 "dsrl\t%0, %0, 32\n\t"
271 "3:\t.section\t.fixup,\"ax\"\n\t"
275 ".section\t__ex_table,\"a\"\n\t"
276 STR(PTR)"\t1b, 4b\n\t"
277 STR(PTR)"\t2b, 4b\n\t"
279 : "=&r" (value), "=r" (res)
280 : "r" (addr), "i" (-EFAULT));
283 compute_return_epc(regs);
284 regs->regs[insn.i_format.rt] = value;
286 #endif /* CONFIG_64BIT */
288 /* Cannot handle 64-bit instructions in 32-bit kernel */
294 * A 32-bit kernel might be running on a 64-bit processor. But
295 * if we're on a 32-bit processor and an i-cache incoherency
296 * or race makes us see a 64-bit instruction here the sdl/sdr
297 * would blow up, so for now we don't handle unaligned 64-bit
298 * instructions on 32-bit kernels.
300 if (!access_ok(VERIFY_READ, addr, 8))
303 __asm__ __volatile__ (
305 "1:\tldl\t%0, (%2)\n"
306 "2:\tldr\t%0, 7(%2)\n\t"
308 #ifdef __LITTLE_ENDIAN
309 "1:\tldl\t%0, 7(%2)\n"
310 "2:\tldr\t%0, (%2)\n\t"
313 "3:\t.section\t.fixup,\"ax\"\n\t"
317 ".section\t__ex_table,\"a\"\n\t"
318 STR(PTR)"\t1b, 4b\n\t"
319 STR(PTR)"\t2b, 4b\n\t"
321 : "=&r" (value), "=r" (res)
322 : "r" (addr), "i" (-EFAULT));
325 compute_return_epc(regs);
326 regs->regs[insn.i_format.rt] = value;
328 #endif /* CONFIG_64BIT */
330 /* Cannot handle 64-bit instructions in 32-bit kernel */
334 if (!access_ok(VERIFY_WRITE, addr, 2))
337 value = regs->regs[insn.i_format.rt];
338 __asm__ __volatile__ (
341 "1:\tsb\t%1, 1(%2)\n\t"
343 "2:\tsb\t$1, 0(%2)\n\t"
346 #ifdef __LITTLE_ENDIAN
348 "1:\tsb\t%1, 0(%2)\n\t"
350 "2:\tsb\t$1, 1(%2)\n\t"
355 ".section\t.fixup,\"ax\"\n\t"
359 ".section\t__ex_table,\"a\"\n\t"
360 STR(PTR)"\t1b, 4b\n\t"
361 STR(PTR)"\t2b, 4b\n\t"
364 : "r" (value), "r" (addr), "i" (-EFAULT));
367 compute_return_epc(regs);
371 if (!access_ok(VERIFY_WRITE, addr, 4))
374 value = regs->regs[insn.i_format.rt];
375 __asm__ __volatile__ (
378 "2:\tswr\t%1, 3(%2)\n\t"
380 #ifdef __LITTLE_ENDIAN
381 "1:\tswl\t%1, 3(%2)\n"
382 "2:\tswr\t%1, (%2)\n\t"
386 ".section\t.fixup,\"ax\"\n\t"
390 ".section\t__ex_table,\"a\"\n\t"
391 STR(PTR)"\t1b, 4b\n\t"
392 STR(PTR)"\t2b, 4b\n\t"
395 : "r" (value), "r" (addr), "i" (-EFAULT));
398 compute_return_epc(regs);
404 * A 32-bit kernel might be running on a 64-bit processor. But
405 * if we're on a 32-bit processor and an i-cache incoherency
406 * or race makes us see a 64-bit instruction here the sdl/sdr
407 * would blow up, so for now we don't handle unaligned 64-bit
408 * instructions on 32-bit kernels.
410 if (!access_ok(VERIFY_WRITE, addr, 8))
413 value = regs->regs[insn.i_format.rt];
414 __asm__ __volatile__ (
417 "2:\tsdr\t%1, 7(%2)\n\t"
419 #ifdef __LITTLE_ENDIAN
420 "1:\tsdl\t%1, 7(%2)\n"
421 "2:\tsdr\t%1, (%2)\n\t"
425 ".section\t.fixup,\"ax\"\n\t"
429 ".section\t__ex_table,\"a\"\n\t"
430 STR(PTR)"\t1b, 4b\n\t"
431 STR(PTR)"\t2b, 4b\n\t"
434 : "r" (value), "r" (addr), "i" (-EFAULT));
437 compute_return_epc(regs);
439 #endif /* CONFIG_64BIT */
441 /* Cannot handle 64-bit instructions in 32-bit kernel */
449 * I herewith declare: this does not happen. So send SIGBUS.
454 * COP2 is available to implementor for application specific use.
455 * It's up to applications to register a notifier chain and do
456 * whatever they have to do, including possible sending of signals.
459 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
463 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
467 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
471 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
476 * Pheeee... We encountered an yet unknown instruction or
477 * cache coherence problem. Die sucker, die ...
482 #ifdef CONFIG_DEBUG_FS
483 unaligned_instructions++;
489 /* Did we have an exception handler installed? */
490 if (fixup_exception(regs))
493 die_if_kernel("Unhandled kernel unaligned access", regs);
494 force_sig(SIGSEGV, current);
499 die_if_kernel("Unhandled kernel unaligned access", regs);
500 force_sig(SIGBUS, current);
505 die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
506 force_sig(SIGILL, current);
509 asmlinkage void do_ade(struct pt_regs *regs)
511 unsigned int __user *pc;
515 * Did we catch a fault trying to load an instruction?
516 * Or are we running in MIPS16 mode?
518 if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1))
521 pc = (unsigned int __user *) exception_epc(regs);
522 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
524 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
526 else if (unaligned_action == UNALIGNED_ACTION_SHOW)
527 show_registers(regs);
530 * Do branch emulation only if we didn't forward the exception.
531 * This is all so but ugly ...
534 if (!user_mode(regs))
536 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
542 die_if_kernel("Kernel unaligned instruction access", regs);
543 force_sig(SIGBUS, current);
546 * XXX On return from the signal handler we should advance the epc
550 #ifdef CONFIG_DEBUG_FS
551 extern struct dentry *mips_debugfs_dir;
552 static int __init debugfs_unaligned(void)
556 if (!mips_debugfs_dir)
558 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
559 mips_debugfs_dir, &unaligned_instructions);
562 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
563 mips_debugfs_dir, &unaligned_action);
568 __initcall(debugfs_unaligned);