arch/mips/kernel/unaligned.c

   1 /*
   2  * Handle unaligned accesses by emulation.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Copyright (C) 2014 Imagination Technologies Ltd.
  11  *
  12  * This file contains exception handler for address error exception with the
  13  * special capability to execute faulting instructions in software.  The
  14  * handler does not try to handle the case when the program counter points
  15  * to an address not aligned to a word boundary.
  16  *
  17  * Putting data to unaligned addresses is a bad practice even on Intel where
  18  * only the performance is affected.  Much worse is that such code is non-
  19  * portable.  Due to several programs that die on MIPS due to alignment
  20  * problems I decided to implement this handler anyway though I originally
  21  * didn't intend to do this at all for user code.
  22  *
  23  * For now I enable fixing of address errors by default to make life easier.
  24  * I however intend to disable this somewhen in the future when the alignment
  25  * problems with user programs have been fixed.  For programmers this is the
  26  * right way to go.
  27  *
  28  * Fixing address errors is a per process option.  The option is inherited
  29  * across fork(2) and execve(2) calls.  If you really want to use the
  30  * option in your user programs - I discourage the use of the software
  31  * emulation strongly - use the following code in your userland stuff:
  32  *
  33  * #include <sys/sysmips.h>
  34  *
  35  * ...
  36  * sysmips(MIPS_FIXADE, x);
  37  * ...
  38  *
  39  * The argument x is 0 for disabling software emulation, enabled otherwise.
  40  *
  41  * Below a little program to play around with this feature.
  42  *
  43  * #include <stdio.h>
  44  * #include <sys/sysmips.h>
  45  *
  46  * struct foo {
  47  *         unsigned char bar[8];
  48  * };
  49  *
  50  * main(int argc, char *argv[])
  51  * {
  52  *         struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
  53  *         unsigned int *p = (unsigned int *) (x.bar + 3);
  54  *         int i;
  55  *
  56  *         if (argc > 1)
  57  *                 sysmips(MIPS_FIXADE, atoi(argv[1]));
  58  *
  59  *         printf("*p = %08lx\n", *p);
  60  *
  61  *         *p = 0xdeadface;
  62  *
  63  *         for(i = 0; i <= 7; i++)
  64  *         printf("%02x ", x.bar[i]);
  65  *         printf("\n");
  66  * }
  67  *
  68  * Coprocessor loads are not supported; I think this case is unimportant
  69  * in the practice.
  70  *
  71  * TODO: Handle ndc (attempted store to doubleword in uncached memory)
  72  *       exception for the R6000.
  73  *       A store crossing a page boundary might be executed only partially.
  74  *       Undo the partial store in this case.
  75  */
  76 #include <linux/context_tracking.h>
  77 #include <linux/mm.h>
  78 #include <linux/signal.h>
  79 #include <linux/smp.h>
  80 #include <linux/sched.h>
  81 #include <linux/debugfs.h>
  82 #include <linux/perf_event.h>
  83
  84 #include <asm/asm.h>
  85 #include <asm/branch.h>
  86 #include <asm/byteorder.h>
  87 #include <asm/cop2.h>
  88 #include <asm/fpu.h>
  89 #include <asm/fpu_emulator.h>
  90 #include <asm/inst.h>
  91 #include <asm/uaccess.h>
  92 #include <asm/fpu.h>
  93 #include <asm/fpu_emulator.h>
  94
  95 #define STR(x)  __STR(x)
  96 #define __STR(x)  #x
  97
  98 enum {
  99         UNALIGNED_ACTION_QUIET,
 100         UNALIGNED_ACTION_SIGNAL,
 101         UNALIGNED_ACTION_SHOW,
 102 };
 103 #ifdef CONFIG_DEBUG_FS
 104 static u32 unaligned_instructions;
 105 static u32 unaligned_action;
 106 #else
 107 #define unaligned_action UNALIGNED_ACTION_QUIET
 108 #endif
 109 extern void show_registers(struct pt_regs *regs);
 110
 111 #ifdef __BIG_ENDIAN
 112 #define     _LoadHW(addr, value, res, type)  \
 113                 __asm__ __volatile__ (".set\tnoat\n"        \
 114                         "1:\t"type##_lb("%0", "0(%2)")"\n"  \
 115                         "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
 116                         "sll\t%0, 0x8\n\t"                  \
 117                         "or\t%0, $1\n\t"                    \
 118                         "li\t%1, 0\n"                       \
 119                         "3:\t.set\tat\n\t"                  \
 120                         ".insn\n\t"                         \
 121                         ".section\t.fixup,\"ax\"\n\t"       \
 122                         "4:\tli\t%1, %3\n\t"                \
 123                         "j\t3b\n\t"                         \
 124                         ".previous\n\t"                     \
 125                         ".section\t__ex_table,\"a\"\n\t"    \
 126                         STR(PTR)"\t1b, 4b\n\t"              \
 127                         STR(PTR)"\t2b, 4b\n\t"              \
 128                         ".previous"                         \
 129                         : "=&r" (value), "=r" (res)         \
 130                         : "r" (addr), "i" (-EFAULT));
 131
 132 #ifndef CONFIG_CPU_MIPSR6
 133 #define     _LoadW(addr, value, res, type)   \
 134                 __asm__ __volatile__ (                      \
 135                         "1:\t"type##_lwl("%0", "(%2)")"\n"   \
 136                         "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
 137                         "li\t%1, 0\n"                       \
 138                         "3:\n\t"                            \
 139                         ".insn\n\t"                         \
 140                         ".section\t.fixup,\"ax\"\n\t"       \
 141                         "4:\tli\t%1, %3\n\t"                \
 142                         "j\t3b\n\t"                         \
 143                         ".previous\n\t"                     \
 144                         ".section\t__ex_table,\"a\"\n\t"    \
 145                         STR(PTR)"\t1b, 4b\n\t"              \
 146                         STR(PTR)"\t2b, 4b\n\t"              \
 147                         ".previous"                         \
 148                         : "=&r" (value), "=r" (res)         \
 149                         : "r" (addr), "i" (-EFAULT));
 150 #else
 151 /* MIPSR6 has no lwl instruction */
 152 #define     _LoadW(addr, value, res, type) \
 153                 __asm__ __volatile__ (                      \
 154                         ".set\tpush\n"                      \
 155                         ".set\tnoat\n\t"                    \
 156                         "1:"type##_lb("%0", "0(%2)")"\n\t"  \
 157                         "2:"type##_lbu("$1", "1(%2)")"\n\t" \
 158                         "sll\t%0, 0x8\n\t"                  \
 159                         "or\t%0, $1\n\t"                    \
 160                         "3:"type##_lbu("$1", "2(%2)")"\n\t" \
 161                         "sll\t%0, 0x8\n\t"                  \
 162                         "or\t%0, $1\n\t"                    \
 163                         "4:"type##_lbu("$1", "3(%2)")"\n\t" \
 164                         "sll\t%0, 0x8\n\t"                  \
 165                         "or\t%0, $1\n\t"                    \
 166                         "li\t%1, 0\n"                       \
 167                         ".set\tpop\n"                       \
 168                         "10:\n\t"                           \
 169                         ".insn\n\t"                         \
 170                         ".section\t.fixup,\"ax\"\n\t"       \
 171                         "11:\tli\t%1, %3\n\t"               \
 172                         "j\t10b\n\t"                        \
 173                         ".previous\n\t"                     \
 174                         ".section\t__ex_table,\"a\"\n\t"    \
 175                         STR(PTR)"\t1b, 11b\n\t"             \
 176                         STR(PTR)"\t2b, 11b\n\t"             \
 177                         STR(PTR)"\t3b, 11b\n\t"             \
 178                         STR(PTR)"\t4b, 11b\n\t"             \
 179                         ".previous"                         \
 180                         : "=&r" (value), "=r" (res)         \
 181                         : "r" (addr), "i" (-EFAULT));
 182 #endif /* CONFIG_CPU_MIPSR6 */
 183
 184 #define     _LoadHWU(addr, value, res, type) \
 185                 __asm__ __volatile__ (                      \
 186                         ".set\tnoat\n"                      \
 187                         "1:\t"type##_lbu("%0", "0(%2)")"\n" \
 188                         "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
 189                         "sll\t%0, 0x8\n\t"                  \
 190                         "or\t%0, $1\n\t"                    \
 191                         "li\t%1, 0\n"                       \
 192                         "3:\n\t"                            \
 193                         ".insn\n\t"                         \
 194                         ".set\tat\n\t"                      \
 195                         ".section\t.fixup,\"ax\"\n\t"       \
 196                         "4:\tli\t%1, %3\n\t"                \
 197                         "j\t3b\n\t"                         \
 198                         ".previous\n\t"                     \
 199                         ".section\t__ex_table,\"a\"\n\t"    \
 200                         STR(PTR)"\t1b, 4b\n\t"              \
 201                         STR(PTR)"\t2b, 4b\n\t"              \
 202                         ".previous"                         \
 203                         : "=&r" (value), "=r" (res)         \
 204                         : "r" (addr), "i" (-EFAULT));
 205
 206 #ifndef CONFIG_CPU_MIPSR6
 207 #define     _LoadWU(addr, value, res, type)  \
 208                 __asm__ __volatile__ (                      \
 209                         "1:\t"type##_lwl("%0", "(%2)")"\n"  \
 210                         "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
 211                         "dsll\t%0, %0, 32\n\t"              \
 212                         "dsrl\t%0, %0, 32\n\t"              \
 213                         "li\t%1, 0\n"                       \
 214                         "3:\n\t"                            \
 215                         ".insn\n\t"                         \
 216                         "\t.section\t.fixup,\"ax\"\n\t"     \
 217                         "4:\tli\t%1, %3\n\t"                \
 218                         "j\t3b\n\t"                         \
 219                         ".previous\n\t"                     \
 220                         ".section\t__ex_table,\"a\"\n\t"    \
 221                         STR(PTR)"\t1b, 4b\n\t"              \
 222                         STR(PTR)"\t2b, 4b\n\t"              \
 223                         ".previous"                         \
 224                         : "=&r" (value), "=r" (res)         \
 225                         : "r" (addr), "i" (-EFAULT));
 226
 227 #define     _LoadDW(addr, value, res)  \
 228                 __asm__ __volatile__ (                      \
 229                         "1:\tldl\t%0, (%2)\n"               \
 230                         "2:\tldr\t%0, 7(%2)\n\t"            \
 231                         "li\t%1, 0\n"                       \
 232                         "3:\n\t"                            \
 233                         ".insn\n\t"                         \
 234                         "\t.section\t.fixup,\"ax\"\n\t"     \
 235                         "4:\tli\t%1, %3\n\t"                \
 236                         "j\t3b\n\t"                         \
 237                         ".previous\n\t"                     \
 238                         ".section\t__ex_table,\"a\"\n\t"    \
 239                         STR(PTR)"\t1b, 4b\n\t"              \
 240                         STR(PTR)"\t2b, 4b\n\t"              \
 241                         ".previous"                         \
 242                         : "=&r" (value), "=r" (res)         \
 243                         : "r" (addr), "i" (-EFAULT));
 244 #else
 245 /* MIPSR6 has not lwl and ldl instructions */
 246 #define     _LoadWU(addr, value, res, type) \
 247                 __asm__ __volatile__ (                      \
 248                         ".set\tpush\n\t"                    \
 249                         ".set\tnoat\n\t"                    \
 250                         "1:"type##_lbu("%0", "0(%2)")"\n\t" \
 251                         "2:"type##_lbu("$1", "1(%2)")"\n\t" \
 252                         "sll\t%0, 0x8\n\t"                  \
 253                         "or\t%0, $1\n\t"                    \
 254                         "3:"type##_lbu("$1", "2(%2)")"\n\t" \
 255                         "sll\t%0, 0x8\n\t"                  \
 256                         "or\t%0, $1\n\t"                    \
 257                         "4:"type##_lbu("$1", "3(%2)")"\n\t" \
 258                         "sll\t%0, 0x8\n\t"                  \
 259                         "or\t%0, $1\n\t"                    \
 260                         "li\t%1, 0\n"                       \
 261                         ".set\tpop\n"                       \
 262                         "10:\n\t"                           \
 263                         ".insn\n\t"                         \
 264                         ".section\t.fixup,\"ax\"\n\t"       \
 265                         "11:\tli\t%1, %3\n\t"               \
 266                         "j\t10b\n\t"                        \
 267                         ".previous\n\t"                     \
 268                         ".section\t__ex_table,\"a\"\n\t"    \
 269                         STR(PTR)"\t1b, 11b\n\t"             \
 270                         STR(PTR)"\t2b, 11b\n\t"             \
 271                         STR(PTR)"\t3b, 11b\n\t"             \
 272                         STR(PTR)"\t4b, 11b\n\t"             \
 273                         ".previous"                         \
 274                         : "=&r" (value), "=r" (res)         \
 275                         : "r" (addr), "i" (-EFAULT));
 276
 277 #define     _LoadDW(addr, value, res)  \
 278                 __asm__ __volatile__ (                      \
 279                         ".set\tpush\n\t"                    \
 280                         ".set\tnoat\n\t"                    \
 281                         "1:lb\t%0, 0(%2)\n\t"               \
 282                         "2:lbu\t $1, 1(%2)\n\t"             \
 283                         "dsll\t%0, 0x8\n\t"                 \
 284                         "or\t%0, $1\n\t"                    \
 285                         "3:lbu\t$1, 2(%2)\n\t"              \
 286                         "dsll\t%0, 0x8\n\t"                 \
 287                         "or\t%0, $1\n\t"                    \
 288                         "4:lbu\t$1, 3(%2)\n\t"              \
 289                         "dsll\t%0, 0x8\n\t"                 \
 290                         "or\t%0, $1\n\t"                    \
 291                         "5:lbu\t$1, 4(%2)\n\t"              \
 292                         "dsll\t%0, 0x8\n\t"                 \
 293                         "or\t%0, $1\n\t"                    \
 294                         "6:lbu\t$1, 5(%2)\n\t"              \
 295                         "dsll\t%0, 0x8\n\t"                 \
 296                         "or\t%0, $1\n\t"                    \
 297                         "7:lbu\t$1, 6(%2)\n\t"              \
 298                         "dsll\t%0, 0x8\n\t"                 \
 299                         "or\t%0, $1\n\t"                    \
 300                         "8:lbu\t$1, 7(%2)\n\t"              \
 301                         "dsll\t%0, 0x8\n\t"                 \
 302                         "or\t%0, $1\n\t"                    \
 303                         "li\t%1, 0\n"                       \
 304                         ".set\tpop\n\t"                     \
 305                         "10:\n\t"                           \
 306                         ".insn\n\t"                         \
 307                         ".section\t.fixup,\"ax\"\n\t"       \
 308                         "11:\tli\t%1, %3\n\t"               \
 309                         "j\t10b\n\t"                        \
 310                         ".previous\n\t"                     \
 311                         ".section\t__ex_table,\"a\"\n\t"    \
 312                         STR(PTR)"\t1b, 11b\n\t"             \
 313                         STR(PTR)"\t2b, 11b\n\t"             \
 314                         STR(PTR)"\t3b, 11b\n\t"             \
 315                         STR(PTR)"\t4b, 11b\n\t"             \
 316                         STR(PTR)"\t5b, 11b\n\t"             \
 317                         STR(PTR)"\t6b, 11b\n\t"             \
 318                         STR(PTR)"\t7b, 11b\n\t"             \
 319                         STR(PTR)"\t8b, 11b\n\t"             \
 320                         ".previous"                         \
 321                         : "=&r" (value), "=r" (res)         \
 322                         : "r" (addr), "i" (-EFAULT));
 323 #endif /* CONFIG_CPU_MIPSR6 */
 324
 325
 326 #define     _StoreHW(addr, value, res, type) \
 327                 __asm__ __volatile__ (                      \
 328                         ".set\tnoat\n"                      \
 329                         "1:\t"type##_sb("%1", "1(%2)")"\n"  \
 330                         "srl\t$1, %1, 0x8\n"                \
 331                         "2:\t"type##_sb("$1", "0(%2)")"\n"  \
 332                         ".set\tat\n\t"                      \
 333                         "li\t%0, 0\n"                       \
 334                         "3:\n\t"                            \
 335                         ".insn\n\t"                         \
 336                         ".section\t.fixup,\"ax\"\n\t"       \
 337                         "4:\tli\t%0, %3\n\t"                \
 338                         "j\t3b\n\t"                         \
 339                         ".previous\n\t"                     \
 340                         ".section\t__ex_table,\"a\"\n\t"    \
 341                         STR(PTR)"\t1b, 4b\n\t"              \
 342                         STR(PTR)"\t2b, 4b\n\t"              \
 343                         ".previous"                         \
 344                         : "=r" (res)                        \
 345                         : "r" (value), "r" (addr), "i" (-EFAULT));
 346
 347 #ifndef CONFIG_CPU_MIPSR6
 348 #define     _StoreW(addr, value, res, type)  \
 349                 __asm__ __volatile__ (                      \
 350                         "1:\t"type##_swl("%1", "(%2)")"\n"  \
 351                         "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
 352                         "li\t%0, 0\n"                       \
 353                         "3:\n\t"                            \
 354                         ".insn\n\t"                         \
 355                         ".section\t.fixup,\"ax\"\n\t"       \
 356                         "4:\tli\t%0, %3\n\t"                \
 357                         "j\t3b\n\t"                         \
 358                         ".previous\n\t"                     \
 359                         ".section\t__ex_table,\"a\"\n\t"    \
 360                         STR(PTR)"\t1b, 4b\n\t"              \
 361                         STR(PTR)"\t2b, 4b\n\t"              \
 362                         ".previous"                         \
 363                 : "=r" (res)                                \
 364                 : "r" (value), "r" (addr), "i" (-EFAULT));
 365
 366 #define     _StoreDW(addr, value, res) \
 367                 __asm__ __volatile__ (                      \
 368                         "1:\tsdl\t%1,(%2)\n"                \
 369                         "2:\tsdr\t%1, 7(%2)\n\t"            \
 370                         "li\t%0, 0\n"                       \
 371                         "3:\n\t"                            \
 372                         ".insn\n\t"                         \
 373                         ".section\t.fixup,\"ax\"\n\t"       \
 374                         "4:\tli\t%0, %3\n\t"                \
 375                         "j\t3b\n\t"                         \
 376                         ".previous\n\t"                     \
 377                         ".section\t__ex_table,\"a\"\n\t"    \
 378                         STR(PTR)"\t1b, 4b\n\t"              \
 379                         STR(PTR)"\t2b, 4b\n\t"              \
 380                         ".previous"                         \
 381                 : "=r" (res)                                \
 382                 : "r" (value), "r" (addr), "i" (-EFAULT));
 383 #else
 384 /* MIPSR6 has no swl and sdl instructions */
 385 #define     _StoreW(addr, value, res, type)  \
 386                 __asm__ __volatile__ (                      \
 387                         ".set\tpush\n\t"                    \
 388                         ".set\tnoat\n\t"                    \
 389                         "1:"type##_sb("%1", "3(%2)")"\n\t"  \
 390                         "srl\t$1, %1, 0x8\n\t"              \
 391                         "2:"type##_sb("$1", "2(%2)")"\n\t"  \
 392                         "srl\t$1, $1,  0x8\n\t"             \
 393                         "3:"type##_sb("$1", "1(%2)")"\n\t"  \
 394                         "srl\t$1, $1, 0x8\n\t"              \
 395                         "4:"type##_sb("$1", "0(%2)")"\n\t"  \
 396                         ".set\tpop\n\t"                     \
 397                         "li\t%0, 0\n"                       \
 398                         "10:\n\t"                           \
 399                         ".insn\n\t"                         \
 400                         ".section\t.fixup,\"ax\"\n\t"       \
 401                         "11:\tli\t%0, %3\n\t"               \
 402                         "j\t10b\n\t"                        \
 403                         ".previous\n\t"                     \
 404                         ".section\t__ex_table,\"a\"\n\t"    \
 405                         STR(PTR)"\t1b, 11b\n\t"             \
 406                         STR(PTR)"\t2b, 11b\n\t"             \
 407                         STR(PTR)"\t3b, 11b\n\t"             \
 408                         STR(PTR)"\t4b, 11b\n\t"             \
 409                         ".previous"                         \
 410                 : "=&r" (res)                               \
 411                 : "r" (value), "r" (addr), "i" (-EFAULT)    \
 412                 : "memory");
 413
 414 #define     StoreDW(addr, value, res) \
 415                 __asm__ __volatile__ (                      \
 416                         ".set\tpush\n\t"                    \
 417                         ".set\tnoat\n\t"                    \
 418                         "1:sb\t%1, 7(%2)\n\t"               \
 419                         "dsrl\t$1, %1, 0x8\n\t"             \
 420                         "2:sb\t$1, 6(%2)\n\t"               \
 421                         "dsrl\t$1, $1, 0x8\n\t"             \
 422                         "3:sb\t$1, 5(%2)\n\t"               \
 423                         "dsrl\t$1, $1, 0x8\n\t"             \
 424                         "4:sb\t$1, 4(%2)\n\t"               \
 425                         "dsrl\t$1, $1, 0x8\n\t"             \
 426                         "5:sb\t$1, 3(%2)\n\t"               \
 427                         "dsrl\t$1, $1, 0x8\n\t"             \
 428                         "6:sb\t$1, 2(%2)\n\t"               \
 429                         "dsrl\t$1, $1, 0x8\n\t"             \
 430                         "7:sb\t$1, 1(%2)\n\t"               \
 431                         "dsrl\t$1, $1, 0x8\n\t"             \
 432                         "8:sb\t$1, 0(%2)\n\t"               \
 433                         "dsrl\t$1, $1, 0x8\n\t"             \
 434                         ".set\tpop\n\t"                     \
 435                         "li\t%0, 0\n"                       \
 436                         "10:\n\t"                           \
 437                         ".insn\n\t"                         \
 438                         ".section\t.fixup,\"ax\"\n\t"       \
 439                         "11:\tli\t%0, %3\n\t"               \
 440                         "j\t10b\n\t"                        \
 441                         ".previous\n\t"                     \
 442                         ".section\t__ex_table,\"a\"\n\t"    \
 443                         STR(PTR)"\t1b, 11b\n\t"             \
 444                         STR(PTR)"\t2b, 11b\n\t"             \
 445                         STR(PTR)"\t3b, 11b\n\t"             \
 446                         STR(PTR)"\t4b, 11b\n\t"             \
 447                         STR(PTR)"\t5b, 11b\n\t"             \
 448                         STR(PTR)"\t6b, 11b\n\t"             \
 449                         STR(PTR)"\t7b, 11b\n\t"             \
 450                         STR(PTR)"\t8b, 11b\n\t"             \
 451                         ".previous"                         \
 452                 : "=&r" (res)                               \
 453                 : "r" (value), "r" (addr), "i" (-EFAULT)    \
 454                 : "memory");
 455 #endif /* CONFIG_CPU_MIPSR6 */
 456
 457 #else /* __BIG_ENDIAN */
 458
 459 #define     _LoadHW(addr, value, res, type)  \
 460                 __asm__ __volatile__ (".set\tnoat\n"        \
 461                         "1:\t"type##_lb("%0", "1(%2)")"\n"  \
 462                         "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
 463                         "sll\t%0, 0x8\n\t"                  \
 464                         "or\t%0, $1\n\t"                    \
 465                         "li\t%1, 0\n"                       \
 466                         "3:\t.set\tat\n\t"                  \
 467                         ".insn\n\t"                         \
 468                         ".section\t.fixup,\"ax\"\n\t"       \
 469                         "4:\tli\t%1, %3\n\t"                \
 470                         "j\t3b\n\t"                         \
 471                         ".previous\n\t"                     \
 472                         ".section\t__ex_table,\"a\"\n\t"    \
 473                         STR(PTR)"\t1b, 4b\n\t"              \
 474                         STR(PTR)"\t2b, 4b\n\t"              \
 475                         ".previous"                         \
 476                         : "=&r" (value), "=r" (res)         \
 477                         : "r" (addr), "i" (-EFAULT));
 478
 479 #ifndef CONFIG_CPU_MIPSR6
 480 #define     _LoadW(addr, value, res, type)   \
 481                 __asm__ __volatile__ (                      \
 482                         "1:\t"type##_lwl("%0", "3(%2)")"\n" \
 483                         "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
 484                         "li\t%1, 0\n"                       \
 485                         "3:\n\t"                            \
 486                         ".insn\n\t"                         \
 487                         ".section\t.fixup,\"ax\"\n\t"       \
 488                         "4:\tli\t%1, %3\n\t"                \
 489                         "j\t3b\n\t"                         \
 490                         ".previous\n\t"                     \
 491                         ".section\t__ex_table,\"a\"\n\t"    \
 492                         STR(PTR)"\t1b, 4b\n\t"              \
 493                         STR(PTR)"\t2b, 4b\n\t"              \
 494                         ".previous"                         \
 495                         : "=&r" (value), "=r" (res)         \
 496                         : "r" (addr), "i" (-EFAULT));
 497 #else
 498 /* MIPSR6 has no lwl instruction */
 499 #define     _LoadW(addr, value, res, type) \
 500                 __asm__ __volatile__ (                      \
 501                         ".set\tpush\n"                      \
 502                         ".set\tnoat\n\t"                    \
 503                         "1:"type##_lb("%0", "3(%2)")"\n\t"  \
 504                         "2:"type##_lbu("$1", "2(%2)")"\n\t" \
 505                         "sll\t%0, 0x8\n\t"                  \
 506                         "or\t%0, $1\n\t"                    \
 507                         "3:"type##_lbu("$1", "1(%2)")"\n\t" \
 508                         "sll\t%0, 0x8\n\t"                  \
 509                         "or\t%0, $1\n\t"                    \
 510                         "4:"type##_lbu("$1", "0(%2)")"\n\t" \
 511                         "sll\t%0, 0x8\n\t"                  \
 512                         "or\t%0, $1\n\t"                    \
 513                         "li\t%1, 0\n"                       \
 514                         ".set\tpop\n"                       \
 515                         "10:\n\t"                           \
 516                         ".insn\n\t"                         \
 517                         ".section\t.fixup,\"ax\"\n\t"       \
 518                         "11:\tli\t%1, %3\n\t"               \
 519                         "j\t10b\n\t"                        \
 520                         ".previous\n\t"                     \
 521                         ".section\t__ex_table,\"a\"\n\t"    \
 522                         STR(PTR)"\t1b, 11b\n\t"             \
 523                         STR(PTR)"\t2b, 11b\n\t"             \
 524                         STR(PTR)"\t3b, 11b\n\t"             \
 525                         STR(PTR)"\t4b, 11b\n\t"             \
 526                         ".previous"                         \
 527                         : "=&r" (value), "=r" (res)         \
 528                         : "r" (addr), "i" (-EFAULT));
 529 #endif /* CONFIG_CPU_MIPSR6 */
 530
 531
 532 #define     _LoadHWU(addr, value, res, type) \
 533                 __asm__ __volatile__ (                      \
 534                         ".set\tnoat\n"                      \
 535                         "1:\t"type##_lbu("%0", "1(%2)")"\n" \
 536                         "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
 537                         "sll\t%0, 0x8\n\t"                  \
 538                         "or\t%0, $1\n\t"                    \
 539                         "li\t%1, 0\n"                       \
 540                         "3:\n\t"                            \
 541                         ".insn\n\t"                         \
 542                         ".set\tat\n\t"                      \
 543                         ".section\t.fixup,\"ax\"\n\t"       \
 544                         "4:\tli\t%1, %3\n\t"                \
 545                         "j\t3b\n\t"                         \
 546                         ".previous\n\t"                     \
 547                         ".section\t__ex_table,\"a\"\n\t"    \
 548                         STR(PTR)"\t1b, 4b\n\t"              \
 549                         STR(PTR)"\t2b, 4b\n\t"              \
 550                         ".previous"                         \
 551                         : "=&r" (value), "=r" (res)         \
 552                         : "r" (addr), "i" (-EFAULT));
 553
 554 #ifndef CONFIG_CPU_MIPSR6
 555 #define     _LoadWU(addr, value, res, type)  \
 556                 __asm__ __volatile__ (                      \
 557                         "1:\t"type##_lwl("%0", "3(%2)")"\n" \
 558                         "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
 559                         "dsll\t%0, %0, 32\n\t"              \
 560                         "dsrl\t%0, %0, 32\n\t"              \
 561                         "li\t%1, 0\n"                       \
 562                         "3:\n\t"                            \
 563                         ".insn\n\t"                         \
 564                         "\t.section\t.fixup,\"ax\"\n\t"     \
 565                         "4:\tli\t%1, %3\n\t"                \
 566                         "j\t3b\n\t"                         \
 567                         ".previous\n\t"                     \
 568                         ".section\t__ex_table,\"a\"\n\t"    \
 569                         STR(PTR)"\t1b, 4b\n\t"              \
 570                         STR(PTR)"\t2b, 4b\n\t"              \
 571                         ".previous"                         \
 572                         : "=&r" (value), "=r" (res)         \
 573                         : "r" (addr), "i" (-EFAULT));
 574
 575 #define     _LoadDW(addr, value, res)  \
 576                 __asm__ __volatile__ (                      \
 577                         "1:\tldl\t%0, 7(%2)\n"              \
 578                         "2:\tldr\t%0, (%2)\n\t"             \
 579                         "li\t%1, 0\n"                       \
 580                         "3:\n\t"                            \
 581                         ".insn\n\t"                         \
 582                         "\t.section\t.fixup,\"ax\"\n\t"     \
 583                         "4:\tli\t%1, %3\n\t"                \
 584                         "j\t3b\n\t"                         \
 585                         ".previous\n\t"                     \
 586                         ".section\t__ex_table,\"a\"\n\t"    \
 587                         STR(PTR)"\t1b, 4b\n\t"              \
 588                         STR(PTR)"\t2b, 4b\n\t"              \
 589                         ".previous"                         \
 590                         : "=&r" (value), "=r" (res)         \
 591                         : "r" (addr), "i" (-EFAULT));
 592 #else
 593 /* MIPSR6 has not lwl and ldl instructions */
 594 #define     _LoadWU(addr, value, res, type) \
 595                 __asm__ __volatile__ (                      \
 596                         ".set\tpush\n\t"                    \
 597                         ".set\tnoat\n\t"                    \
 598                         "1:"type##_lbu("%0", "3(%2)")"\n\t" \
 599                         "2:"type##_lbu("$1", "2(%2)")"\n\t" \
 600                         "sll\t%0, 0x8\n\t"                  \
 601                         "or\t%0, $1\n\t"                    \
 602                         "3:"type##_lbu("$1", "1(%2)")"\n\t" \
 603                         "sll\t%0, 0x8\n\t"                  \
 604                         "or\t%0, $1\n\t"                    \
 605                         "4:"type##_lbu("$1", "0(%2)")"\n\t" \
 606                         "sll\t%0, 0x8\n\t"                  \
 607                         "or\t%0, $1\n\t"                    \
 608                         "li\t%1, 0\n"                       \
 609                         ".set\tpop\n"                       \
 610                         "10:\n\t"                           \
 611                         ".insn\n\t"                         \
 612                         ".section\t.fixup,\"ax\"\n\t"       \
 613                         "11:\tli\t%1, %3\n\t"               \
 614                         "j\t10b\n\t"                        \
 615                         ".previous\n\t"                     \
 616                         ".section\t__ex_table,\"a\"\n\t"    \
 617                         STR(PTR)"\t1b, 11b\n\t"             \
 618                         STR(PTR)"\t2b, 11b\n\t"             \
 619                         STR(PTR)"\t3b, 11b\n\t"             \
 620                         STR(PTR)"\t4b, 11b\n\t"             \
 621                         ".previous"                         \
 622                         : "=&r" (value), "=r" (res)         \
 623                         : "r" (addr), "i" (-EFAULT));
 624
 625 #define     _LoadDW(addr, value, res)  \
 626                 __asm__ __volatile__ (                      \
 627                         ".set\tpush\n\t"                    \
 628                         ".set\tnoat\n\t"                    \
 629                         "1:lb\t%0, 7(%2)\n\t"               \
 630                         "2:lbu\t$1, 6(%2)\n\t"              \
 631                         "dsll\t%0, 0x8\n\t"                 \
 632                         "or\t%0, $1\n\t"                    \
 633                         "3:lbu\t$1, 5(%2)\n\t"              \
 634                         "dsll\t%0, 0x8\n\t"                 \
 635                         "or\t%0, $1\n\t"                    \
 636                         "4:lbu\t$1, 4(%2)\n\t"              \
 637                         "dsll\t%0, 0x8\n\t"                 \
 638                         "or\t%0, $1\n\t"                    \
 639                         "5:lbu\t$1, 3(%2)\n\t"              \
 640                         "dsll\t%0, 0x8\n\t"                 \
 641                         "or\t%0, $1\n\t"                    \
 642                         "6:lbu\t$1, 2(%2)\n\t"              \
 643                         "dsll\t%0, 0x8\n\t"                 \
 644                         "or\t%0, $1\n\t"                    \
 645                         "7:lbu\t$1, 1(%2)\n\t"              \
 646                         "dsll\t%0, 0x8\n\t"                 \
 647                         "or\t%0, $1\n\t"                    \
 648                         "8:lbu\t$1, 0(%2)\n\t"              \
 649                         "dsll\t%0, 0x8\n\t"                 \
 650                         "or\t%0, $1\n\t"                    \
 651                         "li\t%1, 0\n"                       \
 652                         ".set\tpop\n\t"                     \
 653                         "10:\n\t"                           \
 654                         ".insn\n\t"                         \
 655                         ".section\t.fixup,\"ax\"\n\t"       \
 656                         "11:\tli\t%1, %3\n\t"               \
 657                         "j\t10b\n\t"                        \
 658                         ".previous\n\t"                     \
 659                         ".section\t__ex_table,\"a\"\n\t"    \
 660                         STR(PTR)"\t1b, 11b\n\t"             \
 661                         STR(PTR)"\t2b, 11b\n\t"             \
 662                         STR(PTR)"\t3b, 11b\n\t"             \
 663                         STR(PTR)"\t4b, 11b\n\t"             \
 664                         STR(PTR)"\t5b, 11b\n\t"             \
 665                         STR(PTR)"\t6b, 11b\n\t"             \
 666                         STR(PTR)"\t7b, 11b\n\t"             \
 667                         STR(PTR)"\t8b, 11b\n\t"             \
 668                         ".previous"                         \
 669                         : "=&r" (value), "=r" (res)         \
 670                         : "r" (addr), "i" (-EFAULT));
 671 #endif /* CONFIG_CPU_MIPSR6 */
 672
 673 #define     _StoreHW(addr, value, res, type) \
 674                 __asm__ __volatile__ (                      \
 675                         ".set\tnoat\n"                      \
 676                         "1:\t"type##_sb("%1", "0(%2)")"\n"  \
 677                         "srl\t$1,%1, 0x8\n"                 \
 678                         "2:\t"type##_sb("$1", "1(%2)")"\n"  \
 679                         ".set\tat\n\t"                      \
 680                         "li\t%0, 0\n"                       \
 681                         "3:\n\t"                            \
 682                         ".insn\n\t"                         \
 683                         ".section\t.fixup,\"ax\"\n\t"       \
 684                         "4:\tli\t%0, %3\n\t"                \
 685                         "j\t3b\n\t"                         \
 686                         ".previous\n\t"                     \
 687                         ".section\t__ex_table,\"a\"\n\t"    \
 688                         STR(PTR)"\t1b, 4b\n\t"              \
 689                         STR(PTR)"\t2b, 4b\n\t"              \
 690                         ".previous"                         \
 691                         : "=r" (res)                        \
 692                         : "r" (value), "r" (addr), "i" (-EFAULT));
 693 #ifndef CONFIG_CPU_MIPSR6
 694 #define     _StoreW(addr, value, res, type)  \
 695                 __asm__ __volatile__ (                      \
 696                         "1:\t"type##_swl("%1", "3(%2)")"\n" \
 697                         "2:\t"type##_swr("%1", "(%2)")"\n\t"\
 698                         "li\t%0, 0\n"                       \
 699                         "3:\n\t"                            \
 700                         ".insn\n\t"                         \
 701                         ".section\t.fixup,\"ax\"\n\t"       \
 702                         "4:\tli\t%0, %3\n\t"                \
 703                         "j\t3b\n\t"                         \
 704                         ".previous\n\t"                     \
 705                         ".section\t__ex_table,\"a\"\n\t"    \
 706                         STR(PTR)"\t1b, 4b\n\t"              \
 707                         STR(PTR)"\t2b, 4b\n\t"              \
 708                         ".previous"                         \
 709                 : "=r" (res)                                \
 710                 : "r" (value), "r" (addr), "i" (-EFAULT));
 711
 712 #define     _StoreDW(addr, value, res) \
 713                 __asm__ __volatile__ (                      \
 714                         "1:\tsdl\t%1, 7(%2)\n"              \
 715                         "2:\tsdr\t%1, (%2)\n\t"             \
 716                         "li\t%0, 0\n"                       \
 717                         "3:\n\t"                            \
 718                         ".insn\n\t"                         \
 719                         ".section\t.fixup,\"ax\"\n\t"       \
 720                         "4:\tli\t%0, %3\n\t"                \
 721                         "j\t3b\n\t"                         \
 722                         ".previous\n\t"                     \
 723                         ".section\t__ex_table,\"a\"\n\t"    \
 724                         STR(PTR)"\t1b, 4b\n\t"              \
 725                         STR(PTR)"\t2b, 4b\n\t"              \
 726                         ".previous"                         \
 727                 : "=r" (res)                                \
 728                 : "r" (value), "r" (addr), "i" (-EFAULT));
 729 #else
 730 /* MIPSR6 has no swl and sdl instructions */
 731 #define     _StoreW(addr, value, res, type)  \
 732                 __asm__ __volatile__ (                      \
 733                         ".set\tpush\n\t"                    \
 734                         ".set\tnoat\n\t"                    \
 735                         "1:"type##_sb("%1", "0(%2)")"\n\t"  \
 736                         "srl\t$1, %1, 0x8\n\t"              \
 737                         "2:"type##_sb("$1", "1(%2)")"\n\t"  \
 738                         "srl\t$1, $1,  0x8\n\t"             \
 739                         "3:"type##_sb("$1", "2(%2)")"\n\t"  \
 740                         "srl\t$1, $1, 0x8\n\t"              \
 741                         "4:"type##_sb("$1", "3(%2)")"\n\t"  \
 742                         ".set\tpop\n\t"                     \
 743                         "li\t%0, 0\n"                       \
 744                         "10:\n\t"                           \
 745                         ".insn\n\t"                         \
 746                         ".section\t.fixup,\"ax\"\n\t"       \
 747                         "11:\tli\t%0, %3\n\t"               \
 748                         "j\t10b\n\t"                        \
 749                         ".previous\n\t"                     \
 750                         ".section\t__ex_table,\"a\"\n\t"    \
 751                         STR(PTR)"\t1b, 11b\n\t"             \
 752                         STR(PTR)"\t2b, 11b\n\t"             \
 753                         STR(PTR)"\t3b, 11b\n\t"             \
 754                         STR(PTR)"\t4b, 11b\n\t"             \
 755                         ".previous"                         \
 756                 : "=&r" (res)                               \
 757                 : "r" (value), "r" (addr), "i" (-EFAULT)    \
 758                 : "memory");
 759
 760 #define     _StoreDW(addr, value, res) \
 761                 __asm__ __volatile__ (                      \
 762                         ".set\tpush\n\t"                    \
 763                         ".set\tnoat\n\t"                    \
 764                         "1:sb\t%1, 0(%2)\n\t"               \
 765                         "dsrl\t$1, %1, 0x8\n\t"             \
 766                         "2:sb\t$1, 1(%2)\n\t"               \
 767                         "dsrl\t$1, $1, 0x8\n\t"             \
 768                         "3:sb\t$1, 2(%2)\n\t"               \
 769                         "dsrl\t$1, $1, 0x8\n\t"             \
 770                         "4:sb\t$1, 3(%2)\n\t"               \
 771                         "dsrl\t$1, $1, 0x8\n\t"             \
 772                         "5:sb\t$1, 4(%2)\n\t"               \
 773                         "dsrl\t$1, $1, 0x8\n\t"             \
 774                         "6:sb\t$1, 5(%2)\n\t"               \
 775                         "dsrl\t$1, $1, 0x8\n\t"             \
 776                         "7:sb\t$1, 6(%2)\n\t"               \
 777                         "dsrl\t$1, $1, 0x8\n\t"             \
 778                         "8:sb\t$1, 7(%2)\n\t"               \
 779                         "dsrl\t$1, $1, 0x8\n\t"             \
 780                         ".set\tpop\n\t"                     \
 781                         "li\t%0, 0\n"                       \
 782                         "10:\n\t"                           \
 783                         ".insn\n\t"                         \
 784                         ".section\t.fixup,\"ax\"\n\t"       \
 785                         "11:\tli\t%0, %3\n\t"               \
 786                         "j\t10b\n\t"                        \
 787                         ".previous\n\t"                     \
 788                         ".section\t__ex_table,\"a\"\n\t"    \
 789                         STR(PTR)"\t1b, 11b\n\t"             \
 790                         STR(PTR)"\t2b, 11b\n\t"             \
 791                         STR(PTR)"\t3b, 11b\n\t"             \
 792                         STR(PTR)"\t4b, 11b\n\t"             \
 793                         STR(PTR)"\t5b, 11b\n\t"             \
 794                         STR(PTR)"\t6b, 11b\n\t"             \
 795                         STR(PTR)"\t7b, 11b\n\t"             \
 796                         STR(PTR)"\t8b, 11b\n\t"             \
 797                         ".previous"                         \
 798                 : "=&r" (res)                               \
 799                 : "r" (value), "r" (addr), "i" (-EFAULT)    \
 800                 : "memory");
 801 #endif /* CONFIG_CPU_MIPSR6 */
 802 #endif
 803
 804 #define LoadHWU(addr, value, res)       _LoadHWU(addr, value, res, kernel)
 805 #define LoadHWUE(addr, value, res)      _LoadHWU(addr, value, res, user)
 806 #define LoadWU(addr, value, res)        _LoadWU(addr, value, res, kernel)
 807 #define LoadWUE(addr, value, res)       _LoadWU(addr, value, res, user)
 808 #define LoadHW(addr, value, res)        _LoadHW(addr, value, res, kernel)
 809 #define LoadHWE(addr, value, res)       _LoadHW(addr, value, res, user)
 810 #define LoadW(addr, value, res)         _LoadW(addr, value, res, kernel)
 811 #define LoadWE(addr, value, res)        _LoadW(addr, value, res, user)
 812 #define LoadDW(addr, value, res)        _LoadDW(addr, value, res)
 813
 814 #define StoreHW(addr, value, res)       _StoreHW(addr, value, res, kernel)
 815 #define StoreHWE(addr, value, res)      _StoreHW(addr, value, res, user)
 816 #define StoreW(addr, value, res)        _StoreW(addr, value, res, kernel)
 817 #define StoreWE(addr, value, res)       _StoreW(addr, value, res, user)
 818 #define StoreDW(addr, value, res)       _StoreDW(addr, value, res)
 819
 820 static void emulate_load_store_insn(struct pt_regs *regs,
 821         void __user *addr, unsigned int __user *pc)
 822 {
 823         union mips_instruction insn;
 824         unsigned long value;
 825         unsigned int res;
 826         unsigned long origpc;
 827         unsigned long orig31;
 828         void __user *fault_addr = NULL;
 829 #ifdef  CONFIG_EVA
 830         mm_segment_t seg;
 831 #endif
 832         origpc = (unsigned long)pc;
 833         orig31 = regs->regs[31];
 834
 835         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 836
 837         /*
 838          * This load never faults.
 839          */
 840         __get_user(insn.word, pc);
 841
 842         switch (insn.i_format.opcode) {
 843                 /*
 844                  * These are instructions that a compiler doesn't generate.  We
 845                  * can assume therefore that the code is MIPS-aware and
 846                  * really buggy.  Emulating these instructions would break the
 847                  * semantics anyway.
 848                  */
 849         case ll_op:
 850         case lld_op:
 851         case sc_op:
 852         case scd_op:
 853
 854                 /*
 855                  * For these instructions the only way to create an address
 856                  * error is an attempted access to kernel/supervisor address
 857                  * space.
 858                  */
 859         case ldl_op:
 860         case ldr_op:
 861         case lwl_op:
 862         case lwr_op:
 863         case sdl_op:
 864         case sdr_op:
 865         case swl_op:
 866         case swr_op:
 867         case lb_op:
 868         case lbu_op:
 869         case sb_op:
 870                 goto sigbus;
 871
 872                 /*
 873                  * The remaining opcodes are the ones that are really of
 874                  * interest.
 875                  */
 876 #ifdef CONFIG_EVA
 877         case spec3_op:
 878                 /*
 879                  * we can land here only from kernel accessing user memory,
 880                  * so we need to "switch" the address limit to user space, so
 881                  * address check can work properly.
 882                  */
 883                 seg = get_fs();
 884                 set_fs(USER_DS);
 885                 switch (insn.spec3_format.func) {
 886                 case lhe_op:
 887                         if (!access_ok(VERIFY_READ, addr, 2)) {
 888                                 set_fs(seg);
 889                                 goto sigbus;
 890                         }
 891                         LoadHWE(addr, value, res);
 892                         if (res) {
 893                                 set_fs(seg);
 894                                 goto fault;
 895                         }
 896                         compute_return_epc(regs);
 897                         regs->regs[insn.spec3_format.rt] = value;
 898                         break;
 899                 case lwe_op:
 900                         if (!access_ok(VERIFY_READ, addr, 4)) {
 901                                 set_fs(seg);
 902                                 goto sigbus;
 903                         }
 904                                 LoadWE(addr, value, res);
 905                         if (res) {
 906                                 set_fs(seg);
 907                                 goto fault;
 908                         }
 909                         compute_return_epc(regs);
 910                         regs->regs[insn.spec3_format.rt] = value;
 911                         break;
 912                 case lhue_op:
 913                         if (!access_ok(VERIFY_READ, addr, 2)) {
 914                                 set_fs(seg);
 915                                 goto sigbus;
 916                         }
 917                         LoadHWUE(addr, value, res);
 918                         if (res) {
 919                                 set_fs(seg);
 920                                 goto fault;
 921                         }
 922                         compute_return_epc(regs);
 923                         regs->regs[insn.spec3_format.rt] = value;
 924                         break;
 925                 case she_op:
 926                         if (!access_ok(VERIFY_WRITE, addr, 2)) {
 927                                 set_fs(seg);
 928                                 goto sigbus;
 929                         }
 930                         compute_return_epc(regs);
 931                         value = regs->regs[insn.spec3_format.rt];
 932                         StoreHWE(addr, value, res);
 933                         if (res) {
 934                                 set_fs(seg);
 935                                 goto fault;
 936                         }
 937                         break;
 938                 case swe_op:
 939                         if (!access_ok(VERIFY_WRITE, addr, 4)) {
 940                                 set_fs(seg);
 941                                 goto sigbus;
 942                         }
 943                         compute_return_epc(regs);
 944                         value = regs->regs[insn.spec3_format.rt];
 945                         StoreWE(addr, value, res);
 946                         if (res) {
 947                                 set_fs(seg);
 948                                 goto fault;
 949                         }
 950                         break;
 951                 default:
 952                         set_fs(seg);
 953                         goto sigill;
 954                 }
 955                 set_fs(seg);
 956                 break;
 957 #endif
 958         case lh_op:
 959                 if (!access_ok(VERIFY_READ, addr, 2))
 960                         goto sigbus;
 961
 962                 LoadHW(addr, value, res);
 963                 if (res)
 964                         goto fault;
 965                 compute_return_epc(regs);
 966                 regs->regs[insn.i_format.rt] = value;
 967                 break;
 968
 969         case lw_op:
 970                 if (!access_ok(VERIFY_READ, addr, 4))
 971                         goto sigbus;
 972
 973                 LoadW(addr, value, res);
 974                 if (res)
 975                         goto fault;
 976                 compute_return_epc(regs);
 977                 regs->regs[insn.i_format.rt] = value;
 978                 break;
 979
 980         case lhu_op:
 981                 if (!access_ok(VERIFY_READ, addr, 2))
 982                         goto sigbus;
 983
 984                 LoadHWU(addr, value, res);
 985                 if (res)
 986                         goto fault;
 987                 compute_return_epc(regs);
 988                 regs->regs[insn.i_format.rt] = value;
 989                 break;
 990
 991         case lwu_op:
 992 #ifdef CONFIG_64BIT
 993                 /*
 994                  * A 32-bit kernel might be running on a 64-bit processor.  But
 995                  * if we're on a 32-bit processor and an i-cache incoherency
 996                  * or race makes us see a 64-bit instruction here the sdl/sdr
 997                  * would blow up, so for now we don't handle unaligned 64-bit
 998                  * instructions on 32-bit kernels.
 999                  */
1000                 if (!access_ok(VERIFY_READ, addr, 4))
1001                         goto sigbus;
1002
1003                 LoadWU(addr, value, res);
1004                 if (res)
1005                         goto fault;
1006                 compute_return_epc(regs);
1007                 regs->regs[insn.i_format.rt] = value;
1008                 break;
1009 #endif /* CONFIG_64BIT */
1010
1011                 /* Cannot handle 64-bit instructions in 32-bit kernel */
1012                 goto sigill;
1013
1014         case ld_op:
1015 #ifdef CONFIG_64BIT
1016                 /*
1017                  * A 32-bit kernel might be running on a 64-bit processor.  But
1018                  * if we're on a 32-bit processor and an i-cache incoherency
1019                  * or race makes us see a 64-bit instruction here the sdl/sdr
1020                  * would blow up, so for now we don't handle unaligned 64-bit
1021                  * instructions on 32-bit kernels.
1022                  */
1023                 if (!access_ok(VERIFY_READ, addr, 8))
1024                         goto sigbus;
1025
1026                 LoadDW(addr, value, res);
1027                 if (res)
1028                         goto fault;
1029                 compute_return_epc(regs);
1030                 regs->regs[insn.i_format.rt] = value;
1031                 break;
1032 #endif /* CONFIG_64BIT */
1033
1034                 /* Cannot handle 64-bit instructions in 32-bit kernel */
1035                 goto sigill;
1036
1037         case sh_op:
1038                 if (!access_ok(VERIFY_WRITE, addr, 2))
1039                         goto sigbus;
1040
1041                 compute_return_epc(regs);
1042                 value = regs->regs[insn.i_format.rt];
1043                 StoreHW(addr, value, res);
1044                 if (res)
1045                         goto fault;
1046                 break;
1047
1048         case sw_op:
1049                 if (!access_ok(VERIFY_WRITE, addr, 4))
1050                         goto sigbus;
1051
1052                 compute_return_epc(regs);
1053                 value = regs->regs[insn.i_format.rt];
1054                 StoreW(addr, value, res);
1055                 if (res)
1056                         goto fault;
1057                 break;
1058
1059         case sd_op:
1060 #ifdef CONFIG_64BIT
1061                 /*
1062                  * A 32-bit kernel might be running on a 64-bit processor.  But
1063                  * if we're on a 32-bit processor and an i-cache incoherency
1064                  * or race makes us see a 64-bit instruction here the sdl/sdr
1065                  * would blow up, so for now we don't handle unaligned 64-bit
1066                  * instructions on 32-bit kernels.
1067                  */
1068                 if (!access_ok(VERIFY_WRITE, addr, 8))
1069                         goto sigbus;
1070
1071                 compute_return_epc(regs);
1072                 value = regs->regs[insn.i_format.rt];
1073                 StoreDW(addr, value, res);
1074                 if (res)
1075                         goto fault;
1076                 break;
1077 #endif /* CONFIG_64BIT */
1078
1079                 /* Cannot handle 64-bit instructions in 32-bit kernel */
1080                 goto sigill;
1081
1082         case lwc1_op:
1083         case ldc1_op:
1084         case swc1_op:
1085         case sdc1_op:
1086                 die_if_kernel("Unaligned FP access in kernel code", regs);
1087                 BUG_ON(!used_math());
1088
1089                 lose_fpu(1);    /* Save FPU state for the emulator. */
1090                 res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
1091                                                &fault_addr);
1092                 own_fpu(1);     /* Restore FPU state. */
1093
1094                 /* Signal if something went wrong. */
1095                 process_fpemu_return(res, fault_addr);
1096
1097                 if (res == 0)
1098                         break;
1099                 return;
1100
1101 #ifndef CONFIG_CPU_MIPSR6
1102         /*
1103          * COP2 is available to implementor for application specific use.
1104          * It's up to applications to register a notifier chain and do
1105          * whatever they have to do, including possible sending of signals.
1106          *
1107          * This instruction has been reallocated in Release 6
1108          */
1109         case lwc2_op:
1110                 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
1111                 break;
1112
1113         case ldc2_op:
1114                 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
1115                 break;
1116
1117         case swc2_op:
1118                 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
1119                 break;
1120
1121         case sdc2_op:
1122                 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
1123                 break;
1124 #endif
1125         default:
1126                 /*
1127                  * Pheeee...  We encountered an yet unknown instruction or
1128                  * cache coherence problem.  Die sucker, die ...
1129                  */
1130                 goto sigill;
1131         }
1132
1133 #ifdef CONFIG_DEBUG_FS
1134         unaligned_instructions++;
1135 #endif
1136
1137         return;
1138
1139 fault:
1140         /* roll back jump/branch */
1141         regs->cp0_epc = origpc;
1142         regs->regs[31] = orig31;
1143         /* Did we have an exception handler installed? */
1144         if (fixup_exception(regs))
1145                 return;
1146
1147         die_if_kernel("Unhandled kernel unaligned access", regs);
1148         force_sig(SIGSEGV, current);
1149
1150         return;
1151
1152 sigbus:
1153         die_if_kernel("Unhandled kernel unaligned access", regs);
1154         force_sig(SIGBUS, current);
1155
1156         return;
1157
1158 sigill:
1159         die_if_kernel
1160             ("Unhandled kernel unaligned access or invalid instruction", regs);
1161         force_sig(SIGILL, current);
1162 }
1163
1164 /* Recode table from 16-bit register notation to 32-bit GPR. */
1165 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
1166
1167 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1168 const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
1169
1170 static void emulate_load_store_microMIPS(struct pt_regs *regs,
1171                                          void __user *addr)
1172 {
1173         unsigned long value;
1174         unsigned int res;
1175         int i;
1176         unsigned int reg = 0, rvar;
1177         unsigned long orig31;
1178         u16 __user *pc16;
1179         u16 halfword;
1180         unsigned int word;
1181         unsigned long origpc, contpc;
1182         union mips_instruction insn;
1183         struct mm_decoded_insn mminsn;
1184         void __user *fault_addr = NULL;
1185
1186         origpc = regs->cp0_epc;
1187         orig31 = regs->regs[31];
1188
1189         mminsn.micro_mips_mode = 1;
1190
1191         /*
1192          * This load never faults.
1193          */
1194         pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
1195         __get_user(halfword, pc16);
1196         pc16++;
1197         contpc = regs->cp0_epc + 2;
1198         word = ((unsigned int)halfword << 16);
1199         mminsn.pc_inc = 2;
1200
1201         if (!mm_insn_16bit(halfword)) {
1202                 __get_user(halfword, pc16);
1203                 pc16++;
1204                 contpc = regs->cp0_epc + 4;
1205                 mminsn.pc_inc = 4;
1206                 word |= halfword;
1207         }
1208         mminsn.insn = word;
1209
1210         if (get_user(halfword, pc16))
1211                 goto fault;
1212         mminsn.next_pc_inc = 2;
1213         word = ((unsigned int)halfword << 16);
1214
1215         if (!mm_insn_16bit(halfword)) {
1216                 pc16++;
1217                 if (get_user(halfword, pc16))
1218                         goto fault;
1219                 mminsn.next_pc_inc = 4;
1220                 word |= halfword;
1221         }
1222         mminsn.next_insn = word;
1223
1224         insn = (union mips_instruction)(mminsn.insn);
1225         if (mm_isBranchInstr(regs, mminsn, &contpc))
1226                 insn = (union mips_instruction)(mminsn.next_insn);
1227
1228         /*  Parse instruction to find what to do */
1229
1230         switch (insn.mm_i_format.opcode) {
1231
1232         case mm_pool32a_op:
1233                 switch (insn.mm_x_format.func) {
1234                 case mm_lwxs_op:
1235                         reg = insn.mm_x_format.rd;
1236                         goto loadW;
1237                 }
1238
1239                 goto sigbus;
1240
1241         case mm_pool32b_op:
1242                 switch (insn.mm_m_format.func) {
1243                 case mm_lwp_func:
1244                         reg = insn.mm_m_format.rd;
1245                         if (reg == 31)
1246                                 goto sigbus;
1247
1248                         if (!access_ok(VERIFY_READ, addr, 8))
1249                                 goto sigbus;
1250
1251                         LoadW(addr, value, res);
1252                         if (res)
1253                                 goto fault;
1254                         regs->regs[reg] = value;
1255                         addr += 4;
1256                         LoadW(addr, value, res);
1257                         if (res)
1258                                 goto fault;
1259                         regs->regs[reg + 1] = value;
1260                         goto success;
1261
1262                 case mm_swp_func:
1263                         reg = insn.mm_m_format.rd;
1264                         if (reg == 31)
1265                                 goto sigbus;
1266
1267                         if (!access_ok(VERIFY_WRITE, addr, 8))
1268                                 goto sigbus;
1269
1270                         value = regs->regs[reg];
1271                         StoreW(addr, value, res);
1272                         if (res)
1273                                 goto fault;
1274                         addr += 4;
1275                         value = regs->regs[reg + 1];
1276                         StoreW(addr, value, res);
1277                         if (res)
1278                                 goto fault;
1279                         goto success;
1280
1281                 case mm_ldp_func:
1282 #ifdef CONFIG_64BIT
1283                         reg = insn.mm_m_format.rd;
1284                         if (reg == 31)
1285                                 goto sigbus;
1286
1287                         if (!access_ok(VERIFY_READ, addr, 16))
1288                                 goto sigbus;
1289
1290                         LoadDW(addr, value, res);
1291                         if (res)
1292                                 goto fault;
1293                         regs->regs[reg] = value;
1294                         addr += 8;
1295                         LoadDW(addr, value, res);
1296                         if (res)
1297                                 goto fault;
1298                         regs->regs[reg + 1] = value;
1299                         goto success;
1300 #endif /* CONFIG_64BIT */
1301
1302                         goto sigill;
1303
1304                 case mm_sdp_func:
1305 #ifdef CONFIG_64BIT
1306                         reg = insn.mm_m_format.rd;
1307                         if (reg == 31)
1308                                 goto sigbus;
1309
1310                         if (!access_ok(VERIFY_WRITE, addr, 16))
1311                                 goto sigbus;
1312
1313                         value = regs->regs[reg];
1314                         StoreDW(addr, value, res);
1315                         if (res)
1316                                 goto fault;
1317                         addr += 8;
1318                         value = regs->regs[reg + 1];
1319                         StoreDW(addr, value, res);
1320                         if (res)
1321                                 goto fault;
1322                         goto success;
1323 #endif /* CONFIG_64BIT */
1324
1325                         goto sigill;
1326
1327                 case mm_lwm32_func:
1328                         reg = insn.mm_m_format.rd;
1329                         rvar = reg & 0xf;
1330                         if ((rvar > 9) || !reg)
1331                                 goto sigill;
1332                         if (reg & 0x10) {
1333                                 if (!access_ok
1334                                     (VERIFY_READ, addr, 4 * (rvar + 1)))
1335                                         goto sigbus;
1336                         } else {
1337                                 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1338                                         goto sigbus;
1339                         }
1340                         if (rvar == 9)
1341                                 rvar = 8;
1342                         for (i = 16; rvar; rvar--, i++) {
1343                                 LoadW(addr, value, res);
1344                                 if (res)
1345                                         goto fault;
1346                                 addr += 4;
1347                                 regs->regs[i] = value;
1348                         }
1349                         if ((reg & 0xf) == 9) {
1350                                 LoadW(addr, value, res);
1351                                 if (res)
1352                                         goto fault;
1353                                 addr += 4;
1354                                 regs->regs[30] = value;
1355                         }
1356                         if (reg & 0x10) {
1357                                 LoadW(addr, value, res);
1358                                 if (res)
1359                                         goto fault;
1360                                 regs->regs[31] = value;
1361                         }
1362                         goto success;
1363
1364                 case mm_swm32_func:
1365                         reg = insn.mm_m_format.rd;
1366                         rvar = reg & 0xf;
1367                         if ((rvar > 9) || !reg)
1368                                 goto sigill;
1369                         if (reg & 0x10) {
1370                                 if (!access_ok
1371                                     (VERIFY_WRITE, addr, 4 * (rvar + 1)))
1372                                         goto sigbus;
1373                         } else {
1374                                 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1375                                         goto sigbus;
1376                         }
1377                         if (rvar == 9)
1378                                 rvar = 8;
1379                         for (i = 16; rvar; rvar--, i++) {
1380                                 value = regs->regs[i];
1381                                 StoreW(addr, value, res);
1382                                 if (res)
1383                                         goto fault;
1384                                 addr += 4;
1385                         }
1386                         if ((reg & 0xf) == 9) {
1387                                 value = regs->regs[30];
1388                                 StoreW(addr, value, res);
1389                                 if (res)
1390                                         goto fault;
1391                                 addr += 4;
1392                         }
1393                         if (reg & 0x10) {
1394                                 value = regs->regs[31];
1395                                 StoreW(addr, value, res);
1396                                 if (res)
1397                                         goto fault;
1398                         }
1399                         goto success;
1400
1401                 case mm_ldm_func:
1402 #ifdef CONFIG_64BIT
1403                         reg = insn.mm_m_format.rd;
1404                         rvar = reg & 0xf;
1405                         if ((rvar > 9) || !reg)
1406                                 goto sigill;
1407                         if (reg & 0x10) {
1408                                 if (!access_ok
1409                                     (VERIFY_READ, addr, 8 * (rvar + 1)))
1410                                         goto sigbus;
1411                         } else {
1412                                 if (!access_ok(VERIFY_READ, addr, 8 * rvar))
1413                                         goto sigbus;
1414                         }
1415                         if (rvar == 9)
1416                                 rvar = 8;
1417
1418                         for (i = 16; rvar; rvar--, i++) {
1419                                 LoadDW(addr, value, res);
1420                                 if (res)
1421                                         goto fault;
1422                                 addr += 4;
1423                                 regs->regs[i] = value;
1424                         }
1425                         if ((reg & 0xf) == 9) {
1426                                 LoadDW(addr, value, res);
1427                                 if (res)
1428                                         goto fault;
1429                                 addr += 8;
1430                                 regs->regs[30] = value;
1431                         }
1432                         if (reg & 0x10) {
1433                                 LoadDW(addr, value, res);
1434                                 if (res)
1435                                         goto fault;
1436                                 regs->regs[31] = value;
1437                         }
1438                         goto success;
1439 #endif /* CONFIG_64BIT */
1440
1441                         goto sigill;
1442
1443                 case mm_sdm_func:
1444 #ifdef CONFIG_64BIT
1445                         reg = insn.mm_m_format.rd;
1446                         rvar = reg & 0xf;
1447                         if ((rvar > 9) || !reg)
1448                                 goto sigill;
1449                         if (reg & 0x10) {
1450                                 if (!access_ok
1451                                     (VERIFY_WRITE, addr, 8 * (rvar + 1)))
1452                                         goto sigbus;
1453                         } else {
1454                                 if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
1455                                         goto sigbus;
1456                         }
1457                         if (rvar == 9)
1458                                 rvar = 8;
1459
1460                         for (i = 16; rvar; rvar--, i++) {
1461                                 value = regs->regs[i];
1462                                 StoreDW(addr, value, res);
1463                                 if (res)
1464                                         goto fault;
1465                                 addr += 8;
1466                         }
1467                         if ((reg & 0xf) == 9) {
1468                                 value = regs->regs[30];
1469                                 StoreDW(addr, value, res);
1470                                 if (res)
1471                                         goto fault;
1472                                 addr += 8;
1473                         }
1474                         if (reg & 0x10) {
1475                                 value = regs->regs[31];
1476                                 StoreDW(addr, value, res);
1477                                 if (res)
1478                                         goto fault;
1479                         }
1480                         goto success;
1481 #endif /* CONFIG_64BIT */
1482
1483                         goto sigill;
1484
1485                         /*  LWC2, SWC2, LDC2, SDC2 are not serviced */
1486                 }
1487
1488                 goto sigbus;
1489
1490         case mm_pool32c_op:
1491                 switch (insn.mm_m_format.func) {
1492                 case mm_lwu_func:
1493                         reg = insn.mm_m_format.rd;
1494                         goto loadWU;
1495                 }
1496
1497                 /*  LL,SC,LLD,SCD are not serviced */
1498                 goto sigbus;
1499
1500         case mm_pool32f_op:
1501                 switch (insn.mm_x_format.func) {
1502                 case mm_lwxc1_func:
1503                 case mm_swxc1_func:
1504                 case mm_ldxc1_func:
1505                 case mm_sdxc1_func:
1506                         goto fpu_emul;
1507                 }
1508
1509                 goto sigbus;
1510
1511         case mm_ldc132_op:
1512         case mm_sdc132_op:
1513         case mm_lwc132_op:
1514         case mm_swc132_op:
1515 fpu_emul:
1516                 /* roll back jump/branch */
1517                 regs->cp0_epc = origpc;
1518                 regs->regs[31] = orig31;
1519
1520                 die_if_kernel("Unaligned FP access in kernel code", regs);
1521                 BUG_ON(!used_math());
1522                 BUG_ON(!is_fpu_owner());
1523
1524                 lose_fpu(1);    /* save the FPU state for the emulator */
1525                 res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
1526                                                &fault_addr);
1527                 own_fpu(1);     /* restore FPU state */
1528
1529                 /* If something went wrong, signal */
1530                 process_fpemu_return(res, fault_addr);
1531
1532                 if (res == 0)
1533                         goto success;
1534                 return;
1535
1536         case mm_lh32_op:
1537                 reg = insn.mm_i_format.rt;
1538                 goto loadHW;
1539
1540         case mm_lhu32_op:
1541                 reg = insn.mm_i_format.rt;
1542                 goto loadHWU;
1543
1544         case mm_lw32_op:
1545                 reg = insn.mm_i_format.rt;
1546                 goto loadW;
1547
1548         case mm_sh32_op:
1549                 reg = insn.mm_i_format.rt;
1550                 goto storeHW;
1551
1552         case mm_sw32_op:
1553                 reg = insn.mm_i_format.rt;
1554                 goto storeW;
1555
1556         case mm_ld32_op:
1557                 reg = insn.mm_i_format.rt;
1558                 goto loadDW;
1559
1560         case mm_sd32_op:
1561                 reg = insn.mm_i_format.rt;
1562                 goto storeDW;
1563
1564         case mm_pool16c_op:
1565                 switch (insn.mm16_m_format.func) {
1566                 case mm_lwm16_op:
1567                         reg = insn.mm16_m_format.rlist;
1568                         rvar = reg + 1;
1569                         if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1570                                 goto sigbus;
1571
1572                         for (i = 16; rvar; rvar--, i++) {
1573                                 LoadW(addr, value, res);
1574                                 if (res)
1575                                         goto fault;
1576                                 addr += 4;
1577                                 regs->regs[i] = value;
1578                         }
1579                         LoadW(addr, value, res);
1580                         if (res)
1581                                 goto fault;
1582                         regs->regs[31] = value;
1583
1584                         goto success;
1585
1586                 case mm_swm16_op:
1587                         reg = insn.mm16_m_format.rlist;
1588                         rvar = reg + 1;
1589                         if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1590                                 goto sigbus;
1591
1592                         for (i = 16; rvar; rvar--, i++) {
1593                                 value = regs->regs[i];
1594                                 StoreW(addr, value, res);
1595                                 if (res)
1596                                         goto fault;
1597                                 addr += 4;
1598                         }
1599                         value = regs->regs[31];
1600                         StoreW(addr, value, res);
1601                         if (res)
1602                                 goto fault;
1603
1604                         goto success;
1605
1606                 }
1607
1608                 goto sigbus;
1609
1610         case mm_lhu16_op:
1611                 reg = reg16to32[insn.mm16_rb_format.rt];
1612                 goto loadHWU;
1613
1614         case mm_lw16_op:
1615                 reg = reg16to32[insn.mm16_rb_format.rt];
1616                 goto loadW;
1617
1618         case mm_sh16_op:
1619                 reg = reg16to32st[insn.mm16_rb_format.rt];
1620                 goto storeHW;
1621
1622         case mm_sw16_op:
1623                 reg = reg16to32st[insn.mm16_rb_format.rt];
1624                 goto storeW;
1625
1626         case mm_lwsp16_op:
1627                 reg = insn.mm16_r5_format.rt;
1628                 goto loadW;
1629
1630         case mm_swsp16_op:
1631                 reg = insn.mm16_r5_format.rt;
1632                 goto storeW;
1633
1634         case mm_lwgp16_op:
1635                 reg = reg16to32[insn.mm16_r3_format.rt];
1636                 goto loadW;
1637
1638         default:
1639                 goto sigill;
1640         }
1641
1642 loadHW:
1643         if (!access_ok(VERIFY_READ, addr, 2))
1644                 goto sigbus;
1645
1646         LoadHW(addr, value, res);
1647         if (res)
1648                 goto fault;
1649         regs->regs[reg] = value;
1650         goto success;
1651
1652 loadHWU:
1653         if (!access_ok(VERIFY_READ, addr, 2))
1654                 goto sigbus;
1655
1656         LoadHWU(addr, value, res);
1657         if (res)
1658                 goto fault;
1659         regs->regs[reg] = value;
1660         goto success;
1661
1662 loadW:
1663         if (!access_ok(VERIFY_READ, addr, 4))
1664                 goto sigbus;
1665
1666         LoadW(addr, value, res);
1667         if (res)
1668                 goto fault;
1669         regs->regs[reg] = value;
1670         goto success;
1671
1672 loadWU:
1673 #ifdef CONFIG_64BIT
1674         /*
1675          * A 32-bit kernel might be running on a 64-bit processor.  But
1676          * if we're on a 32-bit processor and an i-cache incoherency
1677          * or race makes us see a 64-bit instruction here the sdl/sdr
1678          * would blow up, so for now we don't handle unaligned 64-bit
1679          * instructions on 32-bit kernels.
1680          */
1681         if (!access_ok(VERIFY_READ, addr, 4))
1682                 goto sigbus;
1683
1684         LoadWU(addr, value, res);
1685         if (res)
1686                 goto fault;
1687         regs->regs[reg] = value;
1688         goto success;
1689 #endif /* CONFIG_64BIT */
1690
1691         /* Cannot handle 64-bit instructions in 32-bit kernel */
1692         goto sigill;
1693
1694 loadDW:
1695 #ifdef CONFIG_64BIT
1696         /*
1697          * A 32-bit kernel might be running on a 64-bit processor.  But
1698          * if we're on a 32-bit processor and an i-cache incoherency
1699          * or race makes us see a 64-bit instruction here the sdl/sdr
1700          * would blow up, so for now we don't handle unaligned 64-bit
1701          * instructions on 32-bit kernels.
1702          */
1703         if (!access_ok(VERIFY_READ, addr, 8))
1704                 goto sigbus;
1705
1706         LoadDW(addr, value, res);
1707         if (res)
1708                 goto fault;
1709         regs->regs[reg] = value;
1710         goto success;
1711 #endif /* CONFIG_64BIT */
1712
1713         /* Cannot handle 64-bit instructions in 32-bit kernel */
1714         goto sigill;
1715
1716 storeHW:
1717         if (!access_ok(VERIFY_WRITE, addr, 2))
1718                 goto sigbus;
1719
1720         value = regs->regs[reg];
1721         StoreHW(addr, value, res);
1722         if (res)
1723                 goto fault;
1724         goto success;
1725
1726 storeW:
1727         if (!access_ok(VERIFY_WRITE, addr, 4))
1728                 goto sigbus;
1729
1730         value = regs->regs[reg];
1731         StoreW(addr, value, res);
1732         if (res)
1733                 goto fault;
1734         goto success;
1735
1736 storeDW:
1737 #ifdef CONFIG_64BIT
1738         /*
1739          * A 32-bit kernel might be running on a 64-bit processor.  But
1740          * if we're on a 32-bit processor and an i-cache incoherency
1741          * or race makes us see a 64-bit instruction here the sdl/sdr
1742          * would blow up, so for now we don't handle unaligned 64-bit
1743          * instructions on 32-bit kernels.
1744          */
1745         if (!access_ok(VERIFY_WRITE, addr, 8))
1746                 goto sigbus;
1747
1748         value = regs->regs[reg];
1749         StoreDW(addr, value, res);
1750         if (res)
1751                 goto fault;
1752         goto success;
1753 #endif /* CONFIG_64BIT */
1754
1755         /* Cannot handle 64-bit instructions in 32-bit kernel */
1756         goto sigill;
1757
1758 success:
1759         regs->cp0_epc = contpc; /* advance or branch */
1760
1761 #ifdef CONFIG_DEBUG_FS
1762         unaligned_instructions++;
1763 #endif
1764         return;
1765
1766 fault:
1767         /* roll back jump/branch */
1768         regs->cp0_epc = origpc;
1769         regs->regs[31] = orig31;
1770         /* Did we have an exception handler installed? */
1771         if (fixup_exception(regs))
1772                 return;
1773
1774         die_if_kernel("Unhandled kernel unaligned access", regs);
1775         force_sig(SIGSEGV, current);
1776
1777         return;
1778
1779 sigbus:
1780         die_if_kernel("Unhandled kernel unaligned access", regs);
1781         force_sig(SIGBUS, current);
1782
1783         return;
1784
1785 sigill:
1786         die_if_kernel
1787             ("Unhandled kernel unaligned access or invalid instruction", regs);
1788         force_sig(SIGILL, current);
1789 }
1790
1791 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1792 {
1793         unsigned long value;
1794         unsigned int res;
1795         int reg;
1796         unsigned long orig31;
1797         u16 __user *pc16;
1798         unsigned long origpc;
1799         union mips16e_instruction mips16inst, oldinst;
1800
1801         origpc = regs->cp0_epc;
1802         orig31 = regs->regs[31];
1803         pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1804         /*
1805          * This load never faults.
1806          */
1807         __get_user(mips16inst.full, pc16);
1808         oldinst = mips16inst;
1809
1810         /* skip EXTEND instruction */
1811         if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1812                 pc16++;
1813                 __get_user(mips16inst.full, pc16);
1814         } else if (delay_slot(regs)) {
1815                 /*  skip jump instructions */
1816                 /*  JAL/JALX are 32 bits but have OPCODE in first short int */
1817                 if (mips16inst.ri.opcode == MIPS16e_jal_op)
1818                         pc16++;
1819                 pc16++;
1820                 if (get_user(mips16inst.full, pc16))
1821                         goto sigbus;
1822         }
1823
1824         switch (mips16inst.ri.opcode) {
1825         case MIPS16e_i64_op:    /* I64 or RI64 instruction */
1826                 switch (mips16inst.i64.func) {  /* I64/RI64 func field check */
1827                 case MIPS16e_ldpc_func:
1828                 case MIPS16e_ldsp_func:
1829                         reg = reg16to32[mips16inst.ri64.ry];
1830                         goto loadDW;
1831
1832                 case MIPS16e_sdsp_func:
1833                         reg = reg16to32[mips16inst.ri64.ry];
1834                         goto writeDW;
1835
1836                 case MIPS16e_sdrasp_func:
1837                         reg = 29;       /* GPRSP */
1838                         goto writeDW;
1839                 }
1840
1841                 goto sigbus;
1842
1843         case MIPS16e_swsp_op:
1844         case MIPS16e_lwpc_op:
1845         case MIPS16e_lwsp_op:
1846                 reg = reg16to32[mips16inst.ri.rx];
1847                 break;
1848
1849         case MIPS16e_i8_op:
1850                 if (mips16inst.i8.func != MIPS16e_swrasp_func)
1851                         goto sigbus;
1852                 reg = 29;       /* GPRSP */
1853                 break;
1854
1855         default:
1856                 reg = reg16to32[mips16inst.rri.ry];
1857                 break;
1858         }
1859
1860         switch (mips16inst.ri.opcode) {
1861
1862         case MIPS16e_lb_op:
1863         case MIPS16e_lbu_op:
1864         case MIPS16e_sb_op:
1865                 goto sigbus;
1866
1867         case MIPS16e_lh_op:
1868                 if (!access_ok(VERIFY_READ, addr, 2))
1869                         goto sigbus;
1870
1871                 LoadHW(addr, value, res);
1872                 if (res)
1873                         goto fault;
1874                 MIPS16e_compute_return_epc(regs, &oldinst);
1875                 regs->regs[reg] = value;
1876                 break;
1877
1878         case MIPS16e_lhu_op:
1879                 if (!access_ok(VERIFY_READ, addr, 2))
1880                         goto sigbus;
1881
1882                 LoadHWU(addr, value, res);
1883                 if (res)
1884                         goto fault;
1885                 MIPS16e_compute_return_epc(regs, &oldinst);
1886                 regs->regs[reg] = value;
1887                 break;
1888
1889         case MIPS16e_lw_op:
1890         case MIPS16e_lwpc_op:
1891         case MIPS16e_lwsp_op:
1892                 if (!access_ok(VERIFY_READ, addr, 4))
1893                         goto sigbus;
1894
1895                 LoadW(addr, value, res);
1896                 if (res)
1897                         goto fault;
1898                 MIPS16e_compute_return_epc(regs, &oldinst);
1899                 regs->regs[reg] = value;
1900                 break;
1901
1902         case MIPS16e_lwu_op:
1903 #ifdef CONFIG_64BIT
1904                 /*
1905                  * A 32-bit kernel might be running on a 64-bit processor.  But
1906                  * if we're on a 32-bit processor and an i-cache incoherency
1907                  * or race makes us see a 64-bit instruction here the sdl/sdr
1908                  * would blow up, so for now we don't handle unaligned 64-bit
1909                  * instructions on 32-bit kernels.
1910                  */
1911                 if (!access_ok(VERIFY_READ, addr, 4))
1912                         goto sigbus;
1913
1914                 LoadWU(addr, value, res);
1915                 if (res)
1916                         goto fault;
1917                 MIPS16e_compute_return_epc(regs, &oldinst);
1918                 regs->regs[reg] = value;
1919                 break;
1920 #endif /* CONFIG_64BIT */
1921
1922                 /* Cannot handle 64-bit instructions in 32-bit kernel */
1923                 goto sigill;
1924
1925         case MIPS16e_ld_op:
1926 loadDW:
1927 #ifdef CONFIG_64BIT
1928                 /*
1929                  * A 32-bit kernel might be running on a 64-bit processor.  But
1930                  * if we're on a 32-bit processor and an i-cache incoherency
1931                  * or race makes us see a 64-bit instruction here the sdl/sdr
1932                  * would blow up, so for now we don't handle unaligned 64-bit
1933                  * instructions on 32-bit kernels.
1934                  */
1935                 if (!access_ok(VERIFY_READ, addr, 8))
1936                         goto sigbus;
1937
1938                 LoadDW(addr, value, res);
1939                 if (res)
1940                         goto fault;
1941                 MIPS16e_compute_return_epc(regs, &oldinst);
1942                 regs->regs[reg] = value;
1943                 break;
1944 #endif /* CONFIG_64BIT */
1945
1946                 /* Cannot handle 64-bit instructions in 32-bit kernel */
1947                 goto sigill;
1948
1949         case MIPS16e_sh_op:
1950                 if (!access_ok(VERIFY_WRITE, addr, 2))
1951                         goto sigbus;
1952
1953                 MIPS16e_compute_return_epc(regs, &oldinst);
1954                 value = regs->regs[reg];
1955                 StoreHW(addr, value, res);
1956                 if (res)
1957                         goto fault;
1958                 break;
1959
1960         case MIPS16e_sw_op:
1961         case MIPS16e_swsp_op:
1962         case MIPS16e_i8_op:     /* actually - MIPS16e_swrasp_func */
1963                 if (!access_ok(VERIFY_WRITE, addr, 4))
1964                         goto sigbus;
1965
1966                 MIPS16e_compute_return_epc(regs, &oldinst);
1967                 value = regs->regs[reg];
1968                 StoreW(addr, value, res);
1969                 if (res)
1970                         goto fault;
1971                 break;
1972
1973         case MIPS16e_sd_op:
1974 writeDW:
1975 #ifdef CONFIG_64BIT
1976                 /*
1977                  * A 32-bit kernel might be running on a 64-bit processor.  But
1978                  * if we're on a 32-bit processor and an i-cache incoherency
1979                  * or race makes us see a 64-bit instruction here the sdl/sdr
1980                  * would blow up, so for now we don't handle unaligned 64-bit
1981                  * instructions on 32-bit kernels.
1982                  */
1983                 if (!access_ok(VERIFY_WRITE, addr, 8))
1984                         goto sigbus;
1985
1986                 MIPS16e_compute_return_epc(regs, &oldinst);
1987                 value = regs->regs[reg];
1988                 StoreDW(addr, value, res);
1989                 if (res)
1990                         goto fault;
1991                 break;
1992 #endif /* CONFIG_64BIT */
1993
1994                 /* Cannot handle 64-bit instructions in 32-bit kernel */
1995                 goto sigill;
1996
1997         default:
1998                 /*
1999                  * Pheeee...  We encountered an yet unknown instruction or
2000                  * cache coherence problem.  Die sucker, die ...
2001                  */
2002                 goto sigill;
2003         }
2004
2005 #ifdef CONFIG_DEBUG_FS
2006         unaligned_instructions++;
2007 #endif
2008
2009         return;
2010
2011 fault:
2012         /* roll back jump/branch */
2013         regs->cp0_epc = origpc;
2014         regs->regs[31] = orig31;
2015         /* Did we have an exception handler installed? */
2016         if (fixup_exception(regs))
2017                 return;
2018
2019         die_if_kernel("Unhandled kernel unaligned access", regs);
2020         force_sig(SIGSEGV, current);
2021
2022         return;
2023
2024 sigbus:
2025         die_if_kernel("Unhandled kernel unaligned access", regs);
2026         force_sig(SIGBUS, current);
2027
2028         return;
2029
2030 sigill:
2031         die_if_kernel
2032             ("Unhandled kernel unaligned access or invalid instruction", regs);
2033         force_sig(SIGILL, current);
2034 }
2035
2036 asmlinkage void do_ade(struct pt_regs *regs)
2037 {
2038         enum ctx_state prev_state;
2039         unsigned int __user *pc;
2040         mm_segment_t seg;
2041
2042         prev_state = exception_enter();
2043         perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
2044                         1, regs, regs->cp0_badvaddr);
2045         /*
2046          * Did we catch a fault trying to load an instruction?
2047          */
2048         if (regs->cp0_badvaddr == regs->cp0_epc)
2049                 goto sigbus;
2050
2051         if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
2052                 goto sigbus;
2053         if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
2054                 goto sigbus;
2055
2056         /*
2057          * Do branch emulation only if we didn't forward the exception.
2058          * This is all so but ugly ...
2059          */
2060
2061         /*
2062          * Are we running in microMIPS mode?
2063          */
2064         if (get_isa16_mode(regs->cp0_epc)) {
2065                 /*
2066                  * Did we catch a fault trying to load an instruction in
2067                  * 16-bit mode?
2068                  */
2069                 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
2070                         goto sigbus;
2071                 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2072                         show_registers(regs);
2073
2074                 if (cpu_has_mmips) {
2075                         seg = get_fs();
2076                         if (!user_mode(regs))
2077                                 set_fs(KERNEL_DS);
2078                         emulate_load_store_microMIPS(regs,
2079                                 (void __user *)regs->cp0_badvaddr);
2080                         set_fs(seg);
2081
2082                         return;
2083                 }
2084
2085                 if (cpu_has_mips16) {
2086                         seg = get_fs();
2087                         if (!user_mode(regs))
2088                                 set_fs(KERNEL_DS);
2089                         emulate_load_store_MIPS16e(regs,
2090                                 (void __user *)regs->cp0_badvaddr);
2091                         set_fs(seg);
2092
2093                         return;
2094         }
2095
2096                 goto sigbus;
2097         }
2098
2099         if (unaligned_action == UNALIGNED_ACTION_SHOW)
2100                 show_registers(regs);
2101         pc = (unsigned int __user *)exception_epc(regs);
2102
2103         seg = get_fs();
2104         if (!user_mode(regs))
2105                 set_fs(KERNEL_DS);
2106         emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
2107         set_fs(seg);
2108
2109         return;
2110
2111 sigbus:
2112         die_if_kernel("Kernel unaligned instruction access", regs);
2113         force_sig(SIGBUS, current);
2114
2115         /*
2116          * XXX On return from the signal handler we should advance the epc
2117          */
2118         exception_exit(prev_state);
2119 }
2120
2121 #ifdef CONFIG_DEBUG_FS
2122 extern struct dentry *mips_debugfs_dir;
2123 static int __init debugfs_unaligned(void)
2124 {
2125         struct dentry *d;
2126
2127         if (!mips_debugfs_dir)
2128                 return -ENODEV;
2129         d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
2130                                mips_debugfs_dir, &unaligned_instructions);
2131         if (!d)
2132                 return -ENOMEM;
2133         d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
2134                                mips_debugfs_dir, &unaligned_action);
2135         if (!d)
2136                 return -ENOMEM;
2137         return 0;
2138 }
2139 __initcall(debugfs_unaligned);
2140 #endif