2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2014 Imagination Technologies Ltd.
12 * This file contains exception handler for address error exception with the
13 * special capability to execute faulting instructions in software. The
14 * handler does not try to handle the case when the program counter points
15 * to an address not aligned to a word boundary.
17 * Putting data to unaligned addresses is a bad practice even on Intel where
18 * only the performance is affected. Much worse is that such code is non-
19 * portable. Due to several programs that die on MIPS due to alignment
20 * problems I decided to implement this handler anyway though I originally
21 * didn't intend to do this at all for user code.
23 * For now I enable fixing of address errors by default to make life easier.
24 * I however intend to disable this somewhen in the future when the alignment
25 * problems with user programs have been fixed. For programmers this is the
28 * Fixing address errors is a per process option. The option is inherited
29 * across fork(2) and execve(2) calls. If you really want to use the
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
33 * #include <sys/sysmips.h>
36 * sysmips(MIPS_FIXADE, x);
39 * The argument x is 0 for disabling software emulation, enabled otherwise.
41 * Below a little program to play around with this feature.
44 * #include <sys/sysmips.h>
47 * unsigned char bar[8];
50 * main(int argc, char *argv[])
52 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
53 * unsigned int *p = (unsigned int *) (x.bar + 3);
57 * sysmips(MIPS_FIXADE, atoi(argv[1]));
59 * printf("*p = %08lx\n", *p);
63 * for(i = 0; i <= 7; i++)
64 * printf("%02x ", x.bar[i]);
68 * Coprocessor loads are not supported; I think this case is unimportant
71 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
72 * exception for the R6000.
73 * A store crossing a page boundary might be executed only partially.
74 * Undo the partial store in this case.
76 #include <linux/context_tracking.h>
78 #include <linux/signal.h>
79 #include <linux/smp.h>
80 #include <linux/sched.h>
81 #include <linux/debugfs.h>
82 #include <linux/perf_event.h>
85 #include <asm/branch.h>
86 #include <asm/byteorder.h>
89 #include <asm/fpu_emulator.h>
91 #include <asm/uaccess.h>
93 #include <asm/fpu_emulator.h>
95 #define STR(x) __STR(x)
99 UNALIGNED_ACTION_QUIET,
100 UNALIGNED_ACTION_SIGNAL,
101 UNALIGNED_ACTION_SHOW,
103 #ifdef CONFIG_DEBUG_FS
104 static u32 unaligned_instructions;
105 static u32 unaligned_action;
107 #define unaligned_action UNALIGNED_ACTION_QUIET
109 extern void show_registers(struct pt_regs *regs);
112 #define _LoadHW(addr, value, res, type) \
114 __asm__ __volatile__ (".set\tnoat\n" \
115 "1:\t"type##_lb("%0", "0(%2)")"\n" \
116 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
122 ".section\t.fixup,\"ax\"\n\t" \
123 "4:\tli\t%1, %3\n\t" \
126 ".section\t__ex_table,\"a\"\n\t" \
127 STR(PTR)"\t1b, 4b\n\t" \
128 STR(PTR)"\t2b, 4b\n\t" \
130 : "=&r" (value), "=r" (res) \
131 : "r" (addr), "i" (-EFAULT)); \
134 #ifndef CONFIG_CPU_MIPSR6
135 #define _LoadW(addr, value, res, type) \
137 __asm__ __volatile__ ( \
138 "1:\t"type##_lwl("%0", "(%2)")"\n" \
139 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
143 ".section\t.fixup,\"ax\"\n\t" \
144 "4:\tli\t%1, %3\n\t" \
147 ".section\t__ex_table,\"a\"\n\t" \
148 STR(PTR)"\t1b, 4b\n\t" \
149 STR(PTR)"\t2b, 4b\n\t" \
151 : "=&r" (value), "=r" (res) \
152 : "r" (addr), "i" (-EFAULT)); \
156 /* MIPSR6 has no lwl instruction */
157 #define _LoadW(addr, value, res, type) \
159 __asm__ __volatile__ ( \
162 "1:"type##_lb("%0", "0(%2)")"\n\t" \
163 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
166 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
169 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
176 ".section\t.fixup,\"ax\"\n\t" \
177 "11:\tli\t%1, %3\n\t" \
180 ".section\t__ex_table,\"a\"\n\t" \
181 STR(PTR)"\t1b, 11b\n\t" \
182 STR(PTR)"\t2b, 11b\n\t" \
183 STR(PTR)"\t3b, 11b\n\t" \
184 STR(PTR)"\t4b, 11b\n\t" \
186 : "=&r" (value), "=r" (res) \
187 : "r" (addr), "i" (-EFAULT)); \
190 #endif /* CONFIG_CPU_MIPSR6 */
192 #define _LoadHWU(addr, value, res, type) \
194 __asm__ __volatile__ ( \
196 "1:\t"type##_lbu("%0", "0(%2)")"\n" \
197 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
204 ".section\t.fixup,\"ax\"\n\t" \
205 "4:\tli\t%1, %3\n\t" \
208 ".section\t__ex_table,\"a\"\n\t" \
209 STR(PTR)"\t1b, 4b\n\t" \
210 STR(PTR)"\t2b, 4b\n\t" \
212 : "=&r" (value), "=r" (res) \
213 : "r" (addr), "i" (-EFAULT)); \
216 #ifndef CONFIG_CPU_MIPSR6
217 #define _LoadWU(addr, value, res, type) \
219 __asm__ __volatile__ ( \
220 "1:\t"type##_lwl("%0", "(%2)")"\n" \
221 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
222 "dsll\t%0, %0, 32\n\t" \
223 "dsrl\t%0, %0, 32\n\t" \
227 "\t.section\t.fixup,\"ax\"\n\t" \
228 "4:\tli\t%1, %3\n\t" \
231 ".section\t__ex_table,\"a\"\n\t" \
232 STR(PTR)"\t1b, 4b\n\t" \
233 STR(PTR)"\t2b, 4b\n\t" \
235 : "=&r" (value), "=r" (res) \
236 : "r" (addr), "i" (-EFAULT)); \
239 #define _LoadDW(addr, value, res) \
241 __asm__ __volatile__ ( \
242 "1:\tldl\t%0, (%2)\n" \
243 "2:\tldr\t%0, 7(%2)\n\t" \
247 "\t.section\t.fixup,\"ax\"\n\t" \
248 "4:\tli\t%1, %3\n\t" \
251 ".section\t__ex_table,\"a\"\n\t" \
252 STR(PTR)"\t1b, 4b\n\t" \
253 STR(PTR)"\t2b, 4b\n\t" \
255 : "=&r" (value), "=r" (res) \
256 : "r" (addr), "i" (-EFAULT)); \
260 /* MIPSR6 has not lwl and ldl instructions */
261 #define _LoadWU(addr, value, res, type) \
263 __asm__ __volatile__ ( \
266 "1:"type##_lbu("%0", "0(%2)")"\n\t" \
267 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
270 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
273 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
280 ".section\t.fixup,\"ax\"\n\t" \
281 "11:\tli\t%1, %3\n\t" \
284 ".section\t__ex_table,\"a\"\n\t" \
285 STR(PTR)"\t1b, 11b\n\t" \
286 STR(PTR)"\t2b, 11b\n\t" \
287 STR(PTR)"\t3b, 11b\n\t" \
288 STR(PTR)"\t4b, 11b\n\t" \
290 : "=&r" (value), "=r" (res) \
291 : "r" (addr), "i" (-EFAULT)); \
294 #define _LoadDW(addr, value, res) \
296 __asm__ __volatile__ ( \
299 "1:lb\t%0, 0(%2)\n\t" \
300 "2:lbu\t $1, 1(%2)\n\t" \
301 "dsll\t%0, 0x8\n\t" \
303 "3:lbu\t$1, 2(%2)\n\t" \
304 "dsll\t%0, 0x8\n\t" \
306 "4:lbu\t$1, 3(%2)\n\t" \
307 "dsll\t%0, 0x8\n\t" \
309 "5:lbu\t$1, 4(%2)\n\t" \
310 "dsll\t%0, 0x8\n\t" \
312 "6:lbu\t$1, 5(%2)\n\t" \
313 "dsll\t%0, 0x8\n\t" \
315 "7:lbu\t$1, 6(%2)\n\t" \
316 "dsll\t%0, 0x8\n\t" \
318 "8:lbu\t$1, 7(%2)\n\t" \
319 "dsll\t%0, 0x8\n\t" \
325 ".section\t.fixup,\"ax\"\n\t" \
326 "11:\tli\t%1, %3\n\t" \
329 ".section\t__ex_table,\"a\"\n\t" \
330 STR(PTR)"\t1b, 11b\n\t" \
331 STR(PTR)"\t2b, 11b\n\t" \
332 STR(PTR)"\t3b, 11b\n\t" \
333 STR(PTR)"\t4b, 11b\n\t" \
334 STR(PTR)"\t5b, 11b\n\t" \
335 STR(PTR)"\t6b, 11b\n\t" \
336 STR(PTR)"\t7b, 11b\n\t" \
337 STR(PTR)"\t8b, 11b\n\t" \
339 : "=&r" (value), "=r" (res) \
340 : "r" (addr), "i" (-EFAULT)); \
343 #endif /* CONFIG_CPU_MIPSR6 */
346 #define _StoreHW(addr, value, res, type) \
348 __asm__ __volatile__ ( \
350 "1:\t"type##_sb("%1", "1(%2)")"\n" \
351 "srl\t$1, %1, 0x8\n" \
352 "2:\t"type##_sb("$1", "0(%2)")"\n" \
357 ".section\t.fixup,\"ax\"\n\t" \
358 "4:\tli\t%0, %3\n\t" \
361 ".section\t__ex_table,\"a\"\n\t" \
362 STR(PTR)"\t1b, 4b\n\t" \
363 STR(PTR)"\t2b, 4b\n\t" \
366 : "r" (value), "r" (addr), "i" (-EFAULT));\
369 #ifndef CONFIG_CPU_MIPSR6
370 #define _StoreW(addr, value, res, type) \
372 __asm__ __volatile__ ( \
373 "1:\t"type##_swl("%1", "(%2)")"\n" \
374 "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
378 ".section\t.fixup,\"ax\"\n\t" \
379 "4:\tli\t%0, %3\n\t" \
382 ".section\t__ex_table,\"a\"\n\t" \
383 STR(PTR)"\t1b, 4b\n\t" \
384 STR(PTR)"\t2b, 4b\n\t" \
387 : "r" (value), "r" (addr), "i" (-EFAULT)); \
390 #define _StoreDW(addr, value, res) \
392 __asm__ __volatile__ ( \
393 "1:\tsdl\t%1,(%2)\n" \
394 "2:\tsdr\t%1, 7(%2)\n\t" \
398 ".section\t.fixup,\"ax\"\n\t" \
399 "4:\tli\t%0, %3\n\t" \
402 ".section\t__ex_table,\"a\"\n\t" \
403 STR(PTR)"\t1b, 4b\n\t" \
404 STR(PTR)"\t2b, 4b\n\t" \
407 : "r" (value), "r" (addr), "i" (-EFAULT)); \
411 /* MIPSR6 has no swl and sdl instructions */
412 #define _StoreW(addr, value, res, type) \
414 __asm__ __volatile__ ( \
417 "1:"type##_sb("%1", "3(%2)")"\n\t" \
418 "srl\t$1, %1, 0x8\n\t" \
419 "2:"type##_sb("$1", "2(%2)")"\n\t" \
420 "srl\t$1, $1, 0x8\n\t" \
421 "3:"type##_sb("$1", "1(%2)")"\n\t" \
422 "srl\t$1, $1, 0x8\n\t" \
423 "4:"type##_sb("$1", "0(%2)")"\n\t" \
428 ".section\t.fixup,\"ax\"\n\t" \
429 "11:\tli\t%0, %3\n\t" \
432 ".section\t__ex_table,\"a\"\n\t" \
433 STR(PTR)"\t1b, 11b\n\t" \
434 STR(PTR)"\t2b, 11b\n\t" \
435 STR(PTR)"\t3b, 11b\n\t" \
436 STR(PTR)"\t4b, 11b\n\t" \
439 : "r" (value), "r" (addr), "i" (-EFAULT) \
443 #define StoreDW(addr, value, res) \
445 __asm__ __volatile__ ( \
448 "1:sb\t%1, 7(%2)\n\t" \
449 "dsrl\t$1, %1, 0x8\n\t" \
450 "2:sb\t$1, 6(%2)\n\t" \
451 "dsrl\t$1, $1, 0x8\n\t" \
452 "3:sb\t$1, 5(%2)\n\t" \
453 "dsrl\t$1, $1, 0x8\n\t" \
454 "4:sb\t$1, 4(%2)\n\t" \
455 "dsrl\t$1, $1, 0x8\n\t" \
456 "5:sb\t$1, 3(%2)\n\t" \
457 "dsrl\t$1, $1, 0x8\n\t" \
458 "6:sb\t$1, 2(%2)\n\t" \
459 "dsrl\t$1, $1, 0x8\n\t" \
460 "7:sb\t$1, 1(%2)\n\t" \
461 "dsrl\t$1, $1, 0x8\n\t" \
462 "8:sb\t$1, 0(%2)\n\t" \
463 "dsrl\t$1, $1, 0x8\n\t" \
468 ".section\t.fixup,\"ax\"\n\t" \
469 "11:\tli\t%0, %3\n\t" \
472 ".section\t__ex_table,\"a\"\n\t" \
473 STR(PTR)"\t1b, 11b\n\t" \
474 STR(PTR)"\t2b, 11b\n\t" \
475 STR(PTR)"\t3b, 11b\n\t" \
476 STR(PTR)"\t4b, 11b\n\t" \
477 STR(PTR)"\t5b, 11b\n\t" \
478 STR(PTR)"\t6b, 11b\n\t" \
479 STR(PTR)"\t7b, 11b\n\t" \
480 STR(PTR)"\t8b, 11b\n\t" \
483 : "r" (value), "r" (addr), "i" (-EFAULT) \
487 #endif /* CONFIG_CPU_MIPSR6 */
489 #else /* __BIG_ENDIAN */
491 #define _LoadHW(addr, value, res, type) \
493 __asm__ __volatile__ (".set\tnoat\n" \
494 "1:\t"type##_lb("%0", "1(%2)")"\n" \
495 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
501 ".section\t.fixup,\"ax\"\n\t" \
502 "4:\tli\t%1, %3\n\t" \
505 ".section\t__ex_table,\"a\"\n\t" \
506 STR(PTR)"\t1b, 4b\n\t" \
507 STR(PTR)"\t2b, 4b\n\t" \
509 : "=&r" (value), "=r" (res) \
510 : "r" (addr), "i" (-EFAULT)); \
513 #ifndef CONFIG_CPU_MIPSR6
514 #define _LoadW(addr, value, res, type) \
516 __asm__ __volatile__ ( \
517 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
518 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
522 ".section\t.fixup,\"ax\"\n\t" \
523 "4:\tli\t%1, %3\n\t" \
526 ".section\t__ex_table,\"a\"\n\t" \
527 STR(PTR)"\t1b, 4b\n\t" \
528 STR(PTR)"\t2b, 4b\n\t" \
530 : "=&r" (value), "=r" (res) \
531 : "r" (addr), "i" (-EFAULT)); \
535 /* MIPSR6 has no lwl instruction */
536 #define _LoadW(addr, value, res, type) \
538 __asm__ __volatile__ ( \
541 "1:"type##_lb("%0", "3(%2)")"\n\t" \
542 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
545 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
548 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
555 ".section\t.fixup,\"ax\"\n\t" \
556 "11:\tli\t%1, %3\n\t" \
559 ".section\t__ex_table,\"a\"\n\t" \
560 STR(PTR)"\t1b, 11b\n\t" \
561 STR(PTR)"\t2b, 11b\n\t" \
562 STR(PTR)"\t3b, 11b\n\t" \
563 STR(PTR)"\t4b, 11b\n\t" \
565 : "=&r" (value), "=r" (res) \
566 : "r" (addr), "i" (-EFAULT)); \
569 #endif /* CONFIG_CPU_MIPSR6 */
572 #define _LoadHWU(addr, value, res, type) \
574 __asm__ __volatile__ ( \
576 "1:\t"type##_lbu("%0", "1(%2)")"\n" \
577 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
584 ".section\t.fixup,\"ax\"\n\t" \
585 "4:\tli\t%1, %3\n\t" \
588 ".section\t__ex_table,\"a\"\n\t" \
589 STR(PTR)"\t1b, 4b\n\t" \
590 STR(PTR)"\t2b, 4b\n\t" \
592 : "=&r" (value), "=r" (res) \
593 : "r" (addr), "i" (-EFAULT)); \
596 #ifndef CONFIG_CPU_MIPSR6
597 #define _LoadWU(addr, value, res, type) \
599 __asm__ __volatile__ ( \
600 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
601 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
602 "dsll\t%0, %0, 32\n\t" \
603 "dsrl\t%0, %0, 32\n\t" \
607 "\t.section\t.fixup,\"ax\"\n\t" \
608 "4:\tli\t%1, %3\n\t" \
611 ".section\t__ex_table,\"a\"\n\t" \
612 STR(PTR)"\t1b, 4b\n\t" \
613 STR(PTR)"\t2b, 4b\n\t" \
615 : "=&r" (value), "=r" (res) \
616 : "r" (addr), "i" (-EFAULT)); \
619 #define _LoadDW(addr, value, res) \
621 __asm__ __volatile__ ( \
622 "1:\tldl\t%0, 7(%2)\n" \
623 "2:\tldr\t%0, (%2)\n\t" \
627 "\t.section\t.fixup,\"ax\"\n\t" \
628 "4:\tli\t%1, %3\n\t" \
631 ".section\t__ex_table,\"a\"\n\t" \
632 STR(PTR)"\t1b, 4b\n\t" \
633 STR(PTR)"\t2b, 4b\n\t" \
635 : "=&r" (value), "=r" (res) \
636 : "r" (addr), "i" (-EFAULT)); \
640 /* MIPSR6 has not lwl and ldl instructions */
641 #define _LoadWU(addr, value, res, type) \
643 __asm__ __volatile__ ( \
646 "1:"type##_lbu("%0", "3(%2)")"\n\t" \
647 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
650 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
653 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
660 ".section\t.fixup,\"ax\"\n\t" \
661 "11:\tli\t%1, %3\n\t" \
664 ".section\t__ex_table,\"a\"\n\t" \
665 STR(PTR)"\t1b, 11b\n\t" \
666 STR(PTR)"\t2b, 11b\n\t" \
667 STR(PTR)"\t3b, 11b\n\t" \
668 STR(PTR)"\t4b, 11b\n\t" \
670 : "=&r" (value), "=r" (res) \
671 : "r" (addr), "i" (-EFAULT)); \
674 #define _LoadDW(addr, value, res) \
676 __asm__ __volatile__ ( \
679 "1:lb\t%0, 7(%2)\n\t" \
680 "2:lbu\t$1, 6(%2)\n\t" \
681 "dsll\t%0, 0x8\n\t" \
683 "3:lbu\t$1, 5(%2)\n\t" \
684 "dsll\t%0, 0x8\n\t" \
686 "4:lbu\t$1, 4(%2)\n\t" \
687 "dsll\t%0, 0x8\n\t" \
689 "5:lbu\t$1, 3(%2)\n\t" \
690 "dsll\t%0, 0x8\n\t" \
692 "6:lbu\t$1, 2(%2)\n\t" \
693 "dsll\t%0, 0x8\n\t" \
695 "7:lbu\t$1, 1(%2)\n\t" \
696 "dsll\t%0, 0x8\n\t" \
698 "8:lbu\t$1, 0(%2)\n\t" \
699 "dsll\t%0, 0x8\n\t" \
705 ".section\t.fixup,\"ax\"\n\t" \
706 "11:\tli\t%1, %3\n\t" \
709 ".section\t__ex_table,\"a\"\n\t" \
710 STR(PTR)"\t1b, 11b\n\t" \
711 STR(PTR)"\t2b, 11b\n\t" \
712 STR(PTR)"\t3b, 11b\n\t" \
713 STR(PTR)"\t4b, 11b\n\t" \
714 STR(PTR)"\t5b, 11b\n\t" \
715 STR(PTR)"\t6b, 11b\n\t" \
716 STR(PTR)"\t7b, 11b\n\t" \
717 STR(PTR)"\t8b, 11b\n\t" \
719 : "=&r" (value), "=r" (res) \
720 : "r" (addr), "i" (-EFAULT)); \
722 #endif /* CONFIG_CPU_MIPSR6 */
724 #define _StoreHW(addr, value, res, type) \
726 __asm__ __volatile__ ( \
728 "1:\t"type##_sb("%1", "0(%2)")"\n" \
729 "srl\t$1,%1, 0x8\n" \
730 "2:\t"type##_sb("$1", "1(%2)")"\n" \
735 ".section\t.fixup,\"ax\"\n\t" \
736 "4:\tli\t%0, %3\n\t" \
739 ".section\t__ex_table,\"a\"\n\t" \
740 STR(PTR)"\t1b, 4b\n\t" \
741 STR(PTR)"\t2b, 4b\n\t" \
744 : "r" (value), "r" (addr), "i" (-EFAULT));\
747 #ifndef CONFIG_CPU_MIPSR6
748 #define _StoreW(addr, value, res, type) \
750 __asm__ __volatile__ ( \
751 "1:\t"type##_swl("%1", "3(%2)")"\n" \
752 "2:\t"type##_swr("%1", "(%2)")"\n\t"\
756 ".section\t.fixup,\"ax\"\n\t" \
757 "4:\tli\t%0, %3\n\t" \
760 ".section\t__ex_table,\"a\"\n\t" \
761 STR(PTR)"\t1b, 4b\n\t" \
762 STR(PTR)"\t2b, 4b\n\t" \
765 : "r" (value), "r" (addr), "i" (-EFAULT)); \
768 #define _StoreDW(addr, value, res) \
770 __asm__ __volatile__ ( \
771 "1:\tsdl\t%1, 7(%2)\n" \
772 "2:\tsdr\t%1, (%2)\n\t" \
776 ".section\t.fixup,\"ax\"\n\t" \
777 "4:\tli\t%0, %3\n\t" \
780 ".section\t__ex_table,\"a\"\n\t" \
781 STR(PTR)"\t1b, 4b\n\t" \
782 STR(PTR)"\t2b, 4b\n\t" \
785 : "r" (value), "r" (addr), "i" (-EFAULT)); \
789 /* MIPSR6 has no swl and sdl instructions */
790 #define _StoreW(addr, value, res, type) \
792 __asm__ __volatile__ ( \
795 "1:"type##_sb("%1", "0(%2)")"\n\t" \
796 "srl\t$1, %1, 0x8\n\t" \
797 "2:"type##_sb("$1", "1(%2)")"\n\t" \
798 "srl\t$1, $1, 0x8\n\t" \
799 "3:"type##_sb("$1", "2(%2)")"\n\t" \
800 "srl\t$1, $1, 0x8\n\t" \
801 "4:"type##_sb("$1", "3(%2)")"\n\t" \
806 ".section\t.fixup,\"ax\"\n\t" \
807 "11:\tli\t%0, %3\n\t" \
810 ".section\t__ex_table,\"a\"\n\t" \
811 STR(PTR)"\t1b, 11b\n\t" \
812 STR(PTR)"\t2b, 11b\n\t" \
813 STR(PTR)"\t3b, 11b\n\t" \
814 STR(PTR)"\t4b, 11b\n\t" \
817 : "r" (value), "r" (addr), "i" (-EFAULT) \
821 #define _StoreDW(addr, value, res) \
823 __asm__ __volatile__ ( \
826 "1:sb\t%1, 0(%2)\n\t" \
827 "dsrl\t$1, %1, 0x8\n\t" \
828 "2:sb\t$1, 1(%2)\n\t" \
829 "dsrl\t$1, $1, 0x8\n\t" \
830 "3:sb\t$1, 2(%2)\n\t" \
831 "dsrl\t$1, $1, 0x8\n\t" \
832 "4:sb\t$1, 3(%2)\n\t" \
833 "dsrl\t$1, $1, 0x8\n\t" \
834 "5:sb\t$1, 4(%2)\n\t" \
835 "dsrl\t$1, $1, 0x8\n\t" \
836 "6:sb\t$1, 5(%2)\n\t" \
837 "dsrl\t$1, $1, 0x8\n\t" \
838 "7:sb\t$1, 6(%2)\n\t" \
839 "dsrl\t$1, $1, 0x8\n\t" \
840 "8:sb\t$1, 7(%2)\n\t" \
841 "dsrl\t$1, $1, 0x8\n\t" \
846 ".section\t.fixup,\"ax\"\n\t" \
847 "11:\tli\t%0, %3\n\t" \
850 ".section\t__ex_table,\"a\"\n\t" \
851 STR(PTR)"\t1b, 11b\n\t" \
852 STR(PTR)"\t2b, 11b\n\t" \
853 STR(PTR)"\t3b, 11b\n\t" \
854 STR(PTR)"\t4b, 11b\n\t" \
855 STR(PTR)"\t5b, 11b\n\t" \
856 STR(PTR)"\t6b, 11b\n\t" \
857 STR(PTR)"\t7b, 11b\n\t" \
858 STR(PTR)"\t8b, 11b\n\t" \
861 : "r" (value), "r" (addr), "i" (-EFAULT) \
865 #endif /* CONFIG_CPU_MIPSR6 */
868 #define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
869 #define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
870 #define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
871 #define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
872 #define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
873 #define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
874 #define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
875 #define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
876 #define LoadDW(addr, value, res) _LoadDW(addr, value, res)
878 #define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
879 #define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
880 #define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
881 #define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
882 #define StoreDW(addr, value, res) _StoreDW(addr, value, res)
884 static void emulate_load_store_insn(struct pt_regs *regs,
885 void __user *addr, unsigned int __user *pc)
887 union mips_instruction insn;
890 unsigned long origpc;
891 unsigned long orig31;
892 void __user *fault_addr = NULL;
896 origpc = (unsigned long)pc;
897 orig31 = regs->regs[31];
899 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
902 * This load never faults.
904 __get_user(insn.word, pc);
906 switch (insn.i_format.opcode) {
908 * These are instructions that a compiler doesn't generate. We
909 * can assume therefore that the code is MIPS-aware and
910 * really buggy. Emulating these instructions would break the
919 * For these instructions the only way to create an address
920 * error is an attempted access to kernel/supervisor address
937 * The remaining opcodes are the ones that are really of
943 * we can land here only from kernel accessing user memory,
944 * so we need to "switch" the address limit to user space, so
945 * address check can work properly.
949 switch (insn.spec3_format.func) {
951 if (!access_ok(VERIFY_READ, addr, 2)) {
955 LoadHWE(addr, value, res);
960 compute_return_epc(regs);
961 regs->regs[insn.spec3_format.rt] = value;
964 if (!access_ok(VERIFY_READ, addr, 4)) {
968 LoadWE(addr, value, res);
973 compute_return_epc(regs);
974 regs->regs[insn.spec3_format.rt] = value;
977 if (!access_ok(VERIFY_READ, addr, 2)) {
981 LoadHWUE(addr, value, res);
986 compute_return_epc(regs);
987 regs->regs[insn.spec3_format.rt] = value;
990 if (!access_ok(VERIFY_WRITE, addr, 2)) {
994 compute_return_epc(regs);
995 value = regs->regs[insn.spec3_format.rt];
996 StoreHWE(addr, value, res);
1003 if (!access_ok(VERIFY_WRITE, addr, 4)) {
1007 compute_return_epc(regs);
1008 value = regs->regs[insn.spec3_format.rt];
1009 StoreWE(addr, value, res);
1023 if (!access_ok(VERIFY_READ, addr, 2))
1026 LoadHW(addr, value, res);
1029 compute_return_epc(regs);
1030 regs->regs[insn.i_format.rt] = value;
1034 if (!access_ok(VERIFY_READ, addr, 4))
1037 LoadW(addr, value, res);
1040 compute_return_epc(regs);
1041 regs->regs[insn.i_format.rt] = value;
1045 if (!access_ok(VERIFY_READ, addr, 2))
1048 LoadHWU(addr, value, res);
1051 compute_return_epc(regs);
1052 regs->regs[insn.i_format.rt] = value;
1058 * A 32-bit kernel might be running on a 64-bit processor. But
1059 * if we're on a 32-bit processor and an i-cache incoherency
1060 * or race makes us see a 64-bit instruction here the sdl/sdr
1061 * would blow up, so for now we don't handle unaligned 64-bit
1062 * instructions on 32-bit kernels.
1064 if (!access_ok(VERIFY_READ, addr, 4))
1067 LoadWU(addr, value, res);
1070 compute_return_epc(regs);
1071 regs->regs[insn.i_format.rt] = value;
1073 #endif /* CONFIG_64BIT */
1075 /* Cannot handle 64-bit instructions in 32-bit kernel */
1081 * A 32-bit kernel might be running on a 64-bit processor. But
1082 * if we're on a 32-bit processor and an i-cache incoherency
1083 * or race makes us see a 64-bit instruction here the sdl/sdr
1084 * would blow up, so for now we don't handle unaligned 64-bit
1085 * instructions on 32-bit kernels.
1087 if (!access_ok(VERIFY_READ, addr, 8))
1090 LoadDW(addr, value, res);
1093 compute_return_epc(regs);
1094 regs->regs[insn.i_format.rt] = value;
1096 #endif /* CONFIG_64BIT */
1098 /* Cannot handle 64-bit instructions in 32-bit kernel */
1102 if (!access_ok(VERIFY_WRITE, addr, 2))
1105 compute_return_epc(regs);
1106 value = regs->regs[insn.i_format.rt];
1107 StoreHW(addr, value, res);
1113 if (!access_ok(VERIFY_WRITE, addr, 4))
1116 compute_return_epc(regs);
1117 value = regs->regs[insn.i_format.rt];
1118 StoreW(addr, value, res);
1126 * A 32-bit kernel might be running on a 64-bit processor. But
1127 * if we're on a 32-bit processor and an i-cache incoherency
1128 * or race makes us see a 64-bit instruction here the sdl/sdr
1129 * would blow up, so for now we don't handle unaligned 64-bit
1130 * instructions on 32-bit kernels.
1132 if (!access_ok(VERIFY_WRITE, addr, 8))
1135 compute_return_epc(regs);
1136 value = regs->regs[insn.i_format.rt];
1137 StoreDW(addr, value, res);
1141 #endif /* CONFIG_64BIT */
1143 /* Cannot handle 64-bit instructions in 32-bit kernel */
1150 die_if_kernel("Unaligned FP access in kernel code", regs);
1151 BUG_ON(!used_math());
1153 lose_fpu(1); /* Save FPU state for the emulator. */
1154 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1156 own_fpu(1); /* Restore FPU state. */
1158 /* Signal if something went wrong. */
1159 process_fpemu_return(res, fault_addr);
1165 #ifndef CONFIG_CPU_MIPSR6
1167 * COP2 is available to implementor for application specific use.
1168 * It's up to applications to register a notifier chain and do
1169 * whatever they have to do, including possible sending of signals.
1171 * This instruction has been reallocated in Release 6
1174 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
1178 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
1182 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
1186 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
1191 * Pheeee... We encountered an yet unknown instruction or
1192 * cache coherence problem. Die sucker, die ...
1197 #ifdef CONFIG_DEBUG_FS
1198 unaligned_instructions++;
1204 /* roll back jump/branch */
1205 regs->cp0_epc = origpc;
1206 regs->regs[31] = orig31;
1207 /* Did we have an exception handler installed? */
1208 if (fixup_exception(regs))
1211 die_if_kernel("Unhandled kernel unaligned access", regs);
1212 force_sig(SIGSEGV, current);
1217 die_if_kernel("Unhandled kernel unaligned access", regs);
1218 force_sig(SIGBUS, current);
1224 ("Unhandled kernel unaligned access or invalid instruction", regs);
1225 force_sig(SIGILL, current);
1228 /* Recode table from 16-bit register notation to 32-bit GPR. */
1229 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
1231 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1232 const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
1234 static void emulate_load_store_microMIPS(struct pt_regs *regs,
1237 unsigned long value;
1240 unsigned int reg = 0, rvar;
1241 unsigned long orig31;
1245 unsigned long origpc, contpc;
1246 union mips_instruction insn;
1247 struct mm_decoded_insn mminsn;
1248 void __user *fault_addr = NULL;
1250 origpc = regs->cp0_epc;
1251 orig31 = regs->regs[31];
1253 mminsn.micro_mips_mode = 1;
1256 * This load never faults.
1258 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
1259 __get_user(halfword, pc16);
1261 contpc = regs->cp0_epc + 2;
1262 word = ((unsigned int)halfword << 16);
1265 if (!mm_insn_16bit(halfword)) {
1266 __get_user(halfword, pc16);
1268 contpc = regs->cp0_epc + 4;
1274 if (get_user(halfword, pc16))
1276 mminsn.next_pc_inc = 2;
1277 word = ((unsigned int)halfword << 16);
1279 if (!mm_insn_16bit(halfword)) {
1281 if (get_user(halfword, pc16))
1283 mminsn.next_pc_inc = 4;
1286 mminsn.next_insn = word;
1288 insn = (union mips_instruction)(mminsn.insn);
1289 if (mm_isBranchInstr(regs, mminsn, &contpc))
1290 insn = (union mips_instruction)(mminsn.next_insn);
1292 /* Parse instruction to find what to do */
1294 switch (insn.mm_i_format.opcode) {
1297 switch (insn.mm_x_format.func) {
1299 reg = insn.mm_x_format.rd;
1306 switch (insn.mm_m_format.func) {
1308 reg = insn.mm_m_format.rd;
1312 if (!access_ok(VERIFY_READ, addr, 8))
1315 LoadW(addr, value, res);
1318 regs->regs[reg] = value;
1320 LoadW(addr, value, res);
1323 regs->regs[reg + 1] = value;
1327 reg = insn.mm_m_format.rd;
1331 if (!access_ok(VERIFY_WRITE, addr, 8))
1334 value = regs->regs[reg];
1335 StoreW(addr, value, res);
1339 value = regs->regs[reg + 1];
1340 StoreW(addr, value, res);
1347 reg = insn.mm_m_format.rd;
1351 if (!access_ok(VERIFY_READ, addr, 16))
1354 LoadDW(addr, value, res);
1357 regs->regs[reg] = value;
1359 LoadDW(addr, value, res);
1362 regs->regs[reg + 1] = value;
1364 #endif /* CONFIG_64BIT */
1370 reg = insn.mm_m_format.rd;
1374 if (!access_ok(VERIFY_WRITE, addr, 16))
1377 value = regs->regs[reg];
1378 StoreDW(addr, value, res);
1382 value = regs->regs[reg + 1];
1383 StoreDW(addr, value, res);
1387 #endif /* CONFIG_64BIT */
1392 reg = insn.mm_m_format.rd;
1394 if ((rvar > 9) || !reg)
1398 (VERIFY_READ, addr, 4 * (rvar + 1)))
1401 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1406 for (i = 16; rvar; rvar--, i++) {
1407 LoadW(addr, value, res);
1411 regs->regs[i] = value;
1413 if ((reg & 0xf) == 9) {
1414 LoadW(addr, value, res);
1418 regs->regs[30] = value;
1421 LoadW(addr, value, res);
1424 regs->regs[31] = value;
1429 reg = insn.mm_m_format.rd;
1431 if ((rvar > 9) || !reg)
1435 (VERIFY_WRITE, addr, 4 * (rvar + 1)))
1438 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1443 for (i = 16; rvar; rvar--, i++) {
1444 value = regs->regs[i];
1445 StoreW(addr, value, res);
1450 if ((reg & 0xf) == 9) {
1451 value = regs->regs[30];
1452 StoreW(addr, value, res);
1458 value = regs->regs[31];
1459 StoreW(addr, value, res);
1467 reg = insn.mm_m_format.rd;
1469 if ((rvar > 9) || !reg)
1473 (VERIFY_READ, addr, 8 * (rvar + 1)))
1476 if (!access_ok(VERIFY_READ, addr, 8 * rvar))
1482 for (i = 16; rvar; rvar--, i++) {
1483 LoadDW(addr, value, res);
1487 regs->regs[i] = value;
1489 if ((reg & 0xf) == 9) {
1490 LoadDW(addr, value, res);
1494 regs->regs[30] = value;
1497 LoadDW(addr, value, res);
1500 regs->regs[31] = value;
1503 #endif /* CONFIG_64BIT */
1509 reg = insn.mm_m_format.rd;
1511 if ((rvar > 9) || !reg)
1515 (VERIFY_WRITE, addr, 8 * (rvar + 1)))
1518 if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
1524 for (i = 16; rvar; rvar--, i++) {
1525 value = regs->regs[i];
1526 StoreDW(addr, value, res);
1531 if ((reg & 0xf) == 9) {
1532 value = regs->regs[30];
1533 StoreDW(addr, value, res);
1539 value = regs->regs[31];
1540 StoreDW(addr, value, res);
1545 #endif /* CONFIG_64BIT */
1549 /* LWC2, SWC2, LDC2, SDC2 are not serviced */
1555 switch (insn.mm_m_format.func) {
1557 reg = insn.mm_m_format.rd;
1561 /* LL,SC,LLD,SCD are not serviced */
1565 switch (insn.mm_x_format.func) {
1580 /* roll back jump/branch */
1581 regs->cp0_epc = origpc;
1582 regs->regs[31] = orig31;
1584 die_if_kernel("Unaligned FP access in kernel code", regs);
1585 BUG_ON(!used_math());
1586 BUG_ON(!is_fpu_owner());
1588 lose_fpu(1); /* save the FPU state for the emulator */
1589 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1591 own_fpu(1); /* restore FPU state */
1593 /* If something went wrong, signal */
1594 process_fpemu_return(res, fault_addr);
1601 reg = insn.mm_i_format.rt;
1605 reg = insn.mm_i_format.rt;
1609 reg = insn.mm_i_format.rt;
1613 reg = insn.mm_i_format.rt;
1617 reg = insn.mm_i_format.rt;
1621 reg = insn.mm_i_format.rt;
1625 reg = insn.mm_i_format.rt;
1629 switch (insn.mm16_m_format.func) {
1631 reg = insn.mm16_m_format.rlist;
1633 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1636 for (i = 16; rvar; rvar--, i++) {
1637 LoadW(addr, value, res);
1641 regs->regs[i] = value;
1643 LoadW(addr, value, res);
1646 regs->regs[31] = value;
1651 reg = insn.mm16_m_format.rlist;
1653 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1656 for (i = 16; rvar; rvar--, i++) {
1657 value = regs->regs[i];
1658 StoreW(addr, value, res);
1663 value = regs->regs[31];
1664 StoreW(addr, value, res);
1675 reg = reg16to32[insn.mm16_rb_format.rt];
1679 reg = reg16to32[insn.mm16_rb_format.rt];
1683 reg = reg16to32st[insn.mm16_rb_format.rt];
1687 reg = reg16to32st[insn.mm16_rb_format.rt];
1691 reg = insn.mm16_r5_format.rt;
1695 reg = insn.mm16_r5_format.rt;
1699 reg = reg16to32[insn.mm16_r3_format.rt];
1707 if (!access_ok(VERIFY_READ, addr, 2))
1710 LoadHW(addr, value, res);
1713 regs->regs[reg] = value;
1717 if (!access_ok(VERIFY_READ, addr, 2))
1720 LoadHWU(addr, value, res);
1723 regs->regs[reg] = value;
1727 if (!access_ok(VERIFY_READ, addr, 4))
1730 LoadW(addr, value, res);
1733 regs->regs[reg] = value;
1739 * A 32-bit kernel might be running on a 64-bit processor. But
1740 * if we're on a 32-bit processor and an i-cache incoherency
1741 * or race makes us see a 64-bit instruction here the sdl/sdr
1742 * would blow up, so for now we don't handle unaligned 64-bit
1743 * instructions on 32-bit kernels.
1745 if (!access_ok(VERIFY_READ, addr, 4))
1748 LoadWU(addr, value, res);
1751 regs->regs[reg] = value;
1753 #endif /* CONFIG_64BIT */
1755 /* Cannot handle 64-bit instructions in 32-bit kernel */
1761 * A 32-bit kernel might be running on a 64-bit processor. But
1762 * if we're on a 32-bit processor and an i-cache incoherency
1763 * or race makes us see a 64-bit instruction here the sdl/sdr
1764 * would blow up, so for now we don't handle unaligned 64-bit
1765 * instructions on 32-bit kernels.
1767 if (!access_ok(VERIFY_READ, addr, 8))
1770 LoadDW(addr, value, res);
1773 regs->regs[reg] = value;
1775 #endif /* CONFIG_64BIT */
1777 /* Cannot handle 64-bit instructions in 32-bit kernel */
1781 if (!access_ok(VERIFY_WRITE, addr, 2))
1784 value = regs->regs[reg];
1785 StoreHW(addr, value, res);
1791 if (!access_ok(VERIFY_WRITE, addr, 4))
1794 value = regs->regs[reg];
1795 StoreW(addr, value, res);
1803 * A 32-bit kernel might be running on a 64-bit processor. But
1804 * if we're on a 32-bit processor and an i-cache incoherency
1805 * or race makes us see a 64-bit instruction here the sdl/sdr
1806 * would blow up, so for now we don't handle unaligned 64-bit
1807 * instructions on 32-bit kernels.
1809 if (!access_ok(VERIFY_WRITE, addr, 8))
1812 value = regs->regs[reg];
1813 StoreDW(addr, value, res);
1817 #endif /* CONFIG_64BIT */
1819 /* Cannot handle 64-bit instructions in 32-bit kernel */
1823 regs->cp0_epc = contpc; /* advance or branch */
1825 #ifdef CONFIG_DEBUG_FS
1826 unaligned_instructions++;
1831 /* roll back jump/branch */
1832 regs->cp0_epc = origpc;
1833 regs->regs[31] = orig31;
1834 /* Did we have an exception handler installed? */
1835 if (fixup_exception(regs))
1838 die_if_kernel("Unhandled kernel unaligned access", regs);
1839 force_sig(SIGSEGV, current);
1844 die_if_kernel("Unhandled kernel unaligned access", regs);
1845 force_sig(SIGBUS, current);
1851 ("Unhandled kernel unaligned access or invalid instruction", regs);
1852 force_sig(SIGILL, current);
1855 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1857 unsigned long value;
1860 unsigned long orig31;
1862 unsigned long origpc;
1863 union mips16e_instruction mips16inst, oldinst;
1865 origpc = regs->cp0_epc;
1866 orig31 = regs->regs[31];
1867 pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1869 * This load never faults.
1871 __get_user(mips16inst.full, pc16);
1872 oldinst = mips16inst;
1874 /* skip EXTEND instruction */
1875 if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1877 __get_user(mips16inst.full, pc16);
1878 } else if (delay_slot(regs)) {
1879 /* skip jump instructions */
1880 /* JAL/JALX are 32 bits but have OPCODE in first short int */
1881 if (mips16inst.ri.opcode == MIPS16e_jal_op)
1884 if (get_user(mips16inst.full, pc16))
1888 switch (mips16inst.ri.opcode) {
1889 case MIPS16e_i64_op: /* I64 or RI64 instruction */
1890 switch (mips16inst.i64.func) { /* I64/RI64 func field check */
1891 case MIPS16e_ldpc_func:
1892 case MIPS16e_ldsp_func:
1893 reg = reg16to32[mips16inst.ri64.ry];
1896 case MIPS16e_sdsp_func:
1897 reg = reg16to32[mips16inst.ri64.ry];
1900 case MIPS16e_sdrasp_func:
1901 reg = 29; /* GPRSP */
1907 case MIPS16e_swsp_op:
1908 case MIPS16e_lwpc_op:
1909 case MIPS16e_lwsp_op:
1910 reg = reg16to32[mips16inst.ri.rx];
1914 if (mips16inst.i8.func != MIPS16e_swrasp_func)
1916 reg = 29; /* GPRSP */
1920 reg = reg16to32[mips16inst.rri.ry];
1924 switch (mips16inst.ri.opcode) {
1927 case MIPS16e_lbu_op:
1932 if (!access_ok(VERIFY_READ, addr, 2))
1935 LoadHW(addr, value, res);
1938 MIPS16e_compute_return_epc(regs, &oldinst);
1939 regs->regs[reg] = value;
1942 case MIPS16e_lhu_op:
1943 if (!access_ok(VERIFY_READ, addr, 2))
1946 LoadHWU(addr, value, res);
1949 MIPS16e_compute_return_epc(regs, &oldinst);
1950 regs->regs[reg] = value;
1954 case MIPS16e_lwpc_op:
1955 case MIPS16e_lwsp_op:
1956 if (!access_ok(VERIFY_READ, addr, 4))
1959 LoadW(addr, value, res);
1962 MIPS16e_compute_return_epc(regs, &oldinst);
1963 regs->regs[reg] = value;
1966 case MIPS16e_lwu_op:
1969 * A 32-bit kernel might be running on a 64-bit processor. But
1970 * if we're on a 32-bit processor and an i-cache incoherency
1971 * or race makes us see a 64-bit instruction here the sdl/sdr
1972 * would blow up, so for now we don't handle unaligned 64-bit
1973 * instructions on 32-bit kernels.
1975 if (!access_ok(VERIFY_READ, addr, 4))
1978 LoadWU(addr, value, res);
1981 MIPS16e_compute_return_epc(regs, &oldinst);
1982 regs->regs[reg] = value;
1984 #endif /* CONFIG_64BIT */
1986 /* Cannot handle 64-bit instructions in 32-bit kernel */
1993 * A 32-bit kernel might be running on a 64-bit processor. But
1994 * if we're on a 32-bit processor and an i-cache incoherency
1995 * or race makes us see a 64-bit instruction here the sdl/sdr
1996 * would blow up, so for now we don't handle unaligned 64-bit
1997 * instructions on 32-bit kernels.
1999 if (!access_ok(VERIFY_READ, addr, 8))
2002 LoadDW(addr, value, res);
2005 MIPS16e_compute_return_epc(regs, &oldinst);
2006 regs->regs[reg] = value;
2008 #endif /* CONFIG_64BIT */
2010 /* Cannot handle 64-bit instructions in 32-bit kernel */
2014 if (!access_ok(VERIFY_WRITE, addr, 2))
2017 MIPS16e_compute_return_epc(regs, &oldinst);
2018 value = regs->regs[reg];
2019 StoreHW(addr, value, res);
2025 case MIPS16e_swsp_op:
2026 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
2027 if (!access_ok(VERIFY_WRITE, addr, 4))
2030 MIPS16e_compute_return_epc(regs, &oldinst);
2031 value = regs->regs[reg];
2032 StoreW(addr, value, res);
2041 * A 32-bit kernel might be running on a 64-bit processor. But
2042 * if we're on a 32-bit processor and an i-cache incoherency
2043 * or race makes us see a 64-bit instruction here the sdl/sdr
2044 * would blow up, so for now we don't handle unaligned 64-bit
2045 * instructions on 32-bit kernels.
2047 if (!access_ok(VERIFY_WRITE, addr, 8))
2050 MIPS16e_compute_return_epc(regs, &oldinst);
2051 value = regs->regs[reg];
2052 StoreDW(addr, value, res);
2056 #endif /* CONFIG_64BIT */
2058 /* Cannot handle 64-bit instructions in 32-bit kernel */
2063 * Pheeee... We encountered an yet unknown instruction or
2064 * cache coherence problem. Die sucker, die ...
2069 #ifdef CONFIG_DEBUG_FS
2070 unaligned_instructions++;
2076 /* roll back jump/branch */
2077 regs->cp0_epc = origpc;
2078 regs->regs[31] = orig31;
2079 /* Did we have an exception handler installed? */
2080 if (fixup_exception(regs))
2083 die_if_kernel("Unhandled kernel unaligned access", regs);
2084 force_sig(SIGSEGV, current);
2089 die_if_kernel("Unhandled kernel unaligned access", regs);
2090 force_sig(SIGBUS, current);
2096 ("Unhandled kernel unaligned access or invalid instruction", regs);
2097 force_sig(SIGILL, current);
2100 asmlinkage void do_ade(struct pt_regs *regs)
2102 enum ctx_state prev_state;
2103 unsigned int __user *pc;
2106 prev_state = exception_enter();
2107 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
2108 1, regs, regs->cp0_badvaddr);
2110 * Did we catch a fault trying to load an instruction?
2112 if (regs->cp0_badvaddr == regs->cp0_epc)
2115 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
2117 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
2121 * Do branch emulation only if we didn't forward the exception.
2122 * This is all so but ugly ...
2126 * Are we running in microMIPS mode?
2128 if (get_isa16_mode(regs->cp0_epc)) {
2130 * Did we catch a fault trying to load an instruction in
2133 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
2135 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2136 show_registers(regs);
2138 if (cpu_has_mmips) {
2140 if (!user_mode(regs))
2142 emulate_load_store_microMIPS(regs,
2143 (void __user *)regs->cp0_badvaddr);
2149 if (cpu_has_mips16) {
2151 if (!user_mode(regs))
2153 emulate_load_store_MIPS16e(regs,
2154 (void __user *)regs->cp0_badvaddr);
2163 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2164 show_registers(regs);
2165 pc = (unsigned int __user *)exception_epc(regs);
2168 if (!user_mode(regs))
2170 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
2176 die_if_kernel("Kernel unaligned instruction access", regs);
2177 force_sig(SIGBUS, current);
2180 * XXX On return from the signal handler we should advance the epc
2182 exception_exit(prev_state);
2185 #ifdef CONFIG_DEBUG_FS
2186 extern struct dentry *mips_debugfs_dir;
2187 static int __init debugfs_unaligned(void)
2191 if (!mips_debugfs_dir)
2193 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
2194 mips_debugfs_dir, &unaligned_instructions);
2197 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
2198 mips_debugfs_dir, &unaligned_action);
2203 __initcall(debugfs_unaligned);