arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/fs.h>
  19 #include <linux/bootmem.h>
  20 #include <asm/fpu.h>
  21 #include <asm/page.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/mmu_context.h>
  24 #include <asm/pgtable.h>
  25
  26 #include <linux/kvm_host.h>
  27
  28 #include "interrupt.h"
  29 #include "commpage.h"
  30
  31 #define CREATE_TRACE_POINTS
  32 #include "trace.h"
  33
  34 #ifndef VECTORSPACING
  35 #define VECTORSPACING 0x100     /* for EI/VI mode */
  36 #endif
  37
  38 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  39 struct kvm_stats_debugfs_item debugfs_entries[] = {
  40         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  41         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  42         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  43         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  44         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  45         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  46         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  47         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  48         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  49         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  50         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  51         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  52         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  53         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  54         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  55         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  56         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  57         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  58         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  59         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  60         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  61         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  62         {NULL}
  63 };
  64
  65 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
  66 {
  67         int i;
  68
  69         for_each_possible_cpu(i) {
  70                 vcpu->arch.guest_kernel_asid[i] = 0;
  71                 vcpu->arch.guest_user_asid[i] = 0;
  72         }
  73
  74         return 0;
  75 }
  76
  77 /*
  78  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  79  * Config7, so we are "runnable" if interrupts are pending
  80  */
  81 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  82 {
  83         return !!(vcpu->arch.pending_exceptions);
  84 }
  85
  86 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  87 {
  88         return 1;
  89 }
  90
  91 int kvm_arch_hardware_enable(void)
  92 {
  93         return 0;
  94 }
  95
  96 int kvm_arch_hardware_setup(void)
  97 {
  98         return 0;
  99 }
 100
 101 void kvm_arch_check_processor_compat(void *rtn)
 102 {
 103         *(int *)rtn = 0;
 104 }
 105
 106 static void kvm_mips_init_tlbs(struct kvm *kvm)
 107 {
 108         unsigned long wired;
 109
 110         /*
 111          * Add a wired entry to the TLB, it is used to map the commpage to
 112          * the Guest kernel
 113          */
 114         wired = read_c0_wired();
 115         write_c0_wired(wired + 1);
 116         mtc0_tlbw_hazard();
 117         kvm->arch.commpage_tlb = wired;
 118
 119         kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
 120                   kvm->arch.commpage_tlb);
 121 }
 122
 123 static void kvm_mips_init_vm_percpu(void *arg)
 124 {
 125         struct kvm *kvm = (struct kvm *)arg;
 126
 127         kvm_mips_init_tlbs(kvm);
 128         kvm_mips_callbacks->vm_init(kvm);
 129
 130 }
 131
 132 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 133 {
 134         if (atomic_inc_return(&kvm_mips_instance) == 1) {
 135                 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
 136                           __func__);
 137                 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
 138         }
 139
 140         return 0;
 141 }
 142
 143 bool kvm_arch_has_vcpu_debugfs(void)
 144 {
 145         return false;
 146 }
 147
 148 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
 149 {
 150         return 0;
 151 }
 152
 153 void kvm_mips_free_vcpus(struct kvm *kvm)
 154 {
 155         unsigned int i;
 156         struct kvm_vcpu *vcpu;
 157
 158         /* Put the pages we reserved for the guest pmap */
 159         for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
 160                 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
 161                         kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
 162         }
 163         kfree(kvm->arch.guest_pmap);
 164
 165         kvm_for_each_vcpu(i, vcpu, kvm) {
 166                 kvm_arch_vcpu_free(vcpu);
 167         }
 168
 169         mutex_lock(&kvm->lock);
 170
 171         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 172                 kvm->vcpus[i] = NULL;
 173
 174         atomic_set(&kvm->online_vcpus, 0);
 175
 176         mutex_unlock(&kvm->lock);
 177 }
 178
 179 static void kvm_mips_uninit_tlbs(void *arg)
 180 {
 181         /* Restore wired count */
 182         write_c0_wired(0);
 183         mtc0_tlbw_hazard();
 184         /* Clear out all the TLBs */
 185         kvm_local_flush_tlb_all();
 186 }
 187
 188 void kvm_arch_destroy_vm(struct kvm *kvm)
 189 {
 190         kvm_mips_free_vcpus(kvm);
 191
 192         /* If this is the last instance, restore wired count */
 193         if (atomic_dec_return(&kvm_mips_instance) == 0) {
 194                 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
 195                           __func__);
 196                 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
 197         }
 198 }
 199
 200 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 201                         unsigned long arg)
 202 {
 203         return -ENOIOCTLCMD;
 204 }
 205
 206 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 207                             unsigned long npages)
 208 {
 209         return 0;
 210 }
 211
 212 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 213                                    struct kvm_memory_slot *memslot,
 214                                    const struct kvm_userspace_memory_region *mem,
 215                                    enum kvm_mr_change change)
 216 {
 217         return 0;
 218 }
 219
 220 void kvm_arch_commit_memory_region(struct kvm *kvm,
 221                                    const struct kvm_userspace_memory_region *mem,
 222                                    const struct kvm_memory_slot *old,
 223                                    const struct kvm_memory_slot *new,
 224                                    enum kvm_mr_change change)
 225 {
 226         unsigned long npages = 0;
 227         int i;
 228
 229         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 230                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 231                   mem->memory_size, mem->userspace_addr);
 232
 233         /* Setup Guest PMAP table */
 234         if (!kvm->arch.guest_pmap) {
 235                 if (mem->slot == 0)
 236                         npages = mem->memory_size >> PAGE_SHIFT;
 237
 238                 if (npages) {
 239                         kvm->arch.guest_pmap_npages = npages;
 240                         kvm->arch.guest_pmap =
 241                             kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
 242
 243                         if (!kvm->arch.guest_pmap) {
 244                                 kvm_err("Failed to allocate guest PMAP\n");
 245                                 return;
 246                         }
 247
 248                         kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
 249                                   npages, kvm->arch.guest_pmap);
 250
 251                         /* Now setup the page table */
 252                         for (i = 0; i < npages; i++)
 253                                 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
 254                 }
 255         }
 256 }
 257
 258 static inline void dump_handler(const char *symbol, void *start, void *end)
 259 {
 260         u32 *p;
 261
 262         pr_debug("LEAF(%s)\n", symbol);
 263
 264         pr_debug("\t.set push\n");
 265         pr_debug("\t.set noreorder\n");
 266
 267         for (p = start; p < (u32 *)end; ++p)
 268                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 269
 270         pr_debug("\t.set\tpop\n");
 271
 272         pr_debug("\tEND(%s)\n", symbol);
 273 }
 274
 275 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 276 {
 277         int err, size;
 278         void *gebase, *p, *handler;
 279         int i;
 280
 281         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 282
 283         if (!vcpu) {
 284                 err = -ENOMEM;
 285                 goto out;
 286         }
 287
 288         err = kvm_vcpu_init(vcpu, kvm, id);
 289
 290         if (err)
 291                 goto out_free_cpu;
 292
 293         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 294
 295         /*
 296          * Allocate space for host mode exception handlers that handle
 297          * guest mode exits
 298          */
 299         if (cpu_has_veic || cpu_has_vint)
 300                 size = 0x200 + VECTORSPACING * 64;
 301         else
 302                 size = 0x4000;
 303
 304         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 305
 306         if (!gebase) {
 307                 err = -ENOMEM;
 308                 goto out_uninit_cpu;
 309         }
 310         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 311                   ALIGN(size, PAGE_SIZE), gebase);
 312
 313         /*
 314          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 315          * limits us to the low 512MB of physical address space. If the memory
 316          * we allocate is out of range, just give up now.
 317          */
 318         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 319                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 320                         gebase);
 321                 err = -ENOMEM;
 322                 goto out_free_gebase;
 323         }
 324
 325         /* Save new ebase */
 326         vcpu->arch.guest_ebase = gebase;
 327
 328         /* Build guest exception vectors dynamically in unmapped memory */
 329         handler = gebase + 0x2000;
 330
 331         /* TLB Refill, EXL = 0 */
 332         kvm_mips_build_exception(gebase, handler);
 333
 334         /* General Exception Entry point */
 335         kvm_mips_build_exception(gebase + 0x180, handler);
 336
 337         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 338         for (i = 0; i < 8; i++) {
 339                 kvm_debug("L1 Vectored handler @ %p\n",
 340                           gebase + 0x200 + (i * VECTORSPACING));
 341                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 342                                          handler);
 343         }
 344
 345         /* General exit handler */
 346         p = handler;
 347         p = kvm_mips_build_exit(p);
 348
 349         /* Guest entry routine */
 350         vcpu->arch.vcpu_run = p;
 351         p = kvm_mips_build_vcpu_run(p);
 352
 353         /* Dump the generated code */
 354         pr_debug("#include <asm/asm.h>\n");
 355         pr_debug("#include <asm/regdef.h>\n");
 356         pr_debug("\n");
 357         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 358         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 359         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 360
 361         /* Invalidate the icache for these ranges */
 362         local_flush_icache_range((unsigned long)gebase,
 363                                 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 364
 365         /*
 366          * Allocate comm page for guest kernel, a TLB will be reserved for
 367          * mapping GVA @ 0xFFFF8000 to this page
 368          */
 369         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 370
 371         if (!vcpu->arch.kseg0_commpage) {
 372                 err = -ENOMEM;
 373                 goto out_free_gebase;
 374         }
 375
 376         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 377         kvm_mips_commpage_init(vcpu);
 378
 379         /* Init */
 380         vcpu->arch.last_sched_cpu = -1;
 381
 382         /* Start off the timer */
 383         kvm_mips_init_count(vcpu);
 384
 385         return vcpu;
 386
 387 out_free_gebase:
 388         kfree(gebase);
 389
 390 out_uninit_cpu:
 391         kvm_vcpu_uninit(vcpu);
 392
 393 out_free_cpu:
 394         kfree(vcpu);
 395
 396 out:
 397         return ERR_PTR(err);
 398 }
 399
 400 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 401 {
 402         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 403
 404         kvm_vcpu_uninit(vcpu);
 405
 406         kvm_mips_dump_stats(vcpu);
 407
 408         kfree(vcpu->arch.guest_ebase);
 409         kfree(vcpu->arch.kseg0_commpage);
 410         kfree(vcpu);
 411 }
 412
 413 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 414 {
 415         kvm_arch_vcpu_free(vcpu);
 416 }
 417
 418 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 419                                         struct kvm_guest_debug *dbg)
 420 {
 421         return -ENOIOCTLCMD;
 422 }
 423
 424 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 425 {
 426         int r = 0;
 427         sigset_t sigsaved;
 428
 429         if (vcpu->sigset_active)
 430                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 431
 432         if (vcpu->mmio_needed) {
 433                 if (!vcpu->mmio_is_write)
 434                         kvm_mips_complete_mmio_load(vcpu, run);
 435                 vcpu->mmio_needed = 0;
 436         }
 437
 438         lose_fpu(1);
 439
 440         local_irq_disable();
 441         /* Check if we have any exceptions/interrupts pending */
 442         kvm_mips_deliver_interrupts(vcpu,
 443                                     kvm_read_c0_guest_cause(vcpu->arch.cop0));
 444
 445         guest_enter_irqoff();
 446
 447         /* Disable hardware page table walking while in guest */
 448         htw_stop();
 449
 450         trace_kvm_enter(vcpu);
 451         r = vcpu->arch.vcpu_run(run, vcpu);
 452         trace_kvm_out(vcpu);
 453
 454         /* Re-enable HTW before enabling interrupts */
 455         htw_start();
 456
 457         guest_exit_irqoff();
 458         local_irq_enable();
 459
 460         if (vcpu->sigset_active)
 461                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 462
 463         return r;
 464 }
 465
 466 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 467                              struct kvm_mips_interrupt *irq)
 468 {
 469         int intr = (int)irq->irq;
 470         struct kvm_vcpu *dvcpu = NULL;
 471
 472         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 473                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 474                           (int)intr);
 475
 476         if (irq->cpu == -1)
 477                 dvcpu = vcpu;
 478         else
 479                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 480
 481         if (intr == 2 || intr == 3 || intr == 4) {
 482                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 483
 484         } else if (intr == -2 || intr == -3 || intr == -4) {
 485                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 486         } else {
 487                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 488                         irq->cpu, irq->irq);
 489                 return -EINVAL;
 490         }
 491
 492         dvcpu->arch.wait = 0;
 493
 494         if (swait_active(&dvcpu->wq))
 495                 swake_up(&dvcpu->wq);
 496
 497         return 0;
 498 }
 499
 500 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 501                                     struct kvm_mp_state *mp_state)
 502 {
 503         return -ENOIOCTLCMD;
 504 }
 505
 506 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 507                                     struct kvm_mp_state *mp_state)
 508 {
 509         return -ENOIOCTLCMD;
 510 }
 511
 512 static u64 kvm_mips_get_one_regs[] = {
 513         KVM_REG_MIPS_R0,
 514         KVM_REG_MIPS_R1,
 515         KVM_REG_MIPS_R2,
 516         KVM_REG_MIPS_R3,
 517         KVM_REG_MIPS_R4,
 518         KVM_REG_MIPS_R5,
 519         KVM_REG_MIPS_R6,
 520         KVM_REG_MIPS_R7,
 521         KVM_REG_MIPS_R8,
 522         KVM_REG_MIPS_R9,
 523         KVM_REG_MIPS_R10,
 524         KVM_REG_MIPS_R11,
 525         KVM_REG_MIPS_R12,
 526         KVM_REG_MIPS_R13,
 527         KVM_REG_MIPS_R14,
 528         KVM_REG_MIPS_R15,
 529         KVM_REG_MIPS_R16,
 530         KVM_REG_MIPS_R17,
 531         KVM_REG_MIPS_R18,
 532         KVM_REG_MIPS_R19,
 533         KVM_REG_MIPS_R20,
 534         KVM_REG_MIPS_R21,
 535         KVM_REG_MIPS_R22,
 536         KVM_REG_MIPS_R23,
 537         KVM_REG_MIPS_R24,
 538         KVM_REG_MIPS_R25,
 539         KVM_REG_MIPS_R26,
 540         KVM_REG_MIPS_R27,
 541         KVM_REG_MIPS_R28,
 542         KVM_REG_MIPS_R29,
 543         KVM_REG_MIPS_R30,
 544         KVM_REG_MIPS_R31,
 545
 546 #ifndef CONFIG_CPU_MIPSR6
 547         KVM_REG_MIPS_HI,
 548         KVM_REG_MIPS_LO,
 549 #endif
 550         KVM_REG_MIPS_PC,
 551
 552         KVM_REG_MIPS_CP0_INDEX,
 553         KVM_REG_MIPS_CP0_CONTEXT,
 554         KVM_REG_MIPS_CP0_USERLOCAL,
 555         KVM_REG_MIPS_CP0_PAGEMASK,
 556         KVM_REG_MIPS_CP0_WIRED,
 557         KVM_REG_MIPS_CP0_HWRENA,
 558         KVM_REG_MIPS_CP0_BADVADDR,
 559         KVM_REG_MIPS_CP0_COUNT,
 560         KVM_REG_MIPS_CP0_ENTRYHI,
 561         KVM_REG_MIPS_CP0_COMPARE,
 562         KVM_REG_MIPS_CP0_STATUS,
 563         KVM_REG_MIPS_CP0_CAUSE,
 564         KVM_REG_MIPS_CP0_EPC,
 565         KVM_REG_MIPS_CP0_PRID,
 566         KVM_REG_MIPS_CP0_CONFIG,
 567         KVM_REG_MIPS_CP0_CONFIG1,
 568         KVM_REG_MIPS_CP0_CONFIG2,
 569         KVM_REG_MIPS_CP0_CONFIG3,
 570         KVM_REG_MIPS_CP0_CONFIG4,
 571         KVM_REG_MIPS_CP0_CONFIG5,
 572         KVM_REG_MIPS_CP0_CONFIG7,
 573         KVM_REG_MIPS_CP0_ERROREPC,
 574
 575         KVM_REG_MIPS_COUNT_CTL,
 576         KVM_REG_MIPS_COUNT_RESUME,
 577         KVM_REG_MIPS_COUNT_HZ,
 578 };
 579
 580 static u64 kvm_mips_get_one_regs_fpu[] = {
 581         KVM_REG_MIPS_FCR_IR,
 582         KVM_REG_MIPS_FCR_CSR,
 583 };
 584
 585 static u64 kvm_mips_get_one_regs_msa[] = {
 586         KVM_REG_MIPS_MSA_IR,
 587         KVM_REG_MIPS_MSA_CSR,
 588 };
 589
 590 static u64 kvm_mips_get_one_regs_kscratch[] = {
 591         KVM_REG_MIPS_CP0_KSCRATCH1,
 592         KVM_REG_MIPS_CP0_KSCRATCH2,
 593         KVM_REG_MIPS_CP0_KSCRATCH3,
 594         KVM_REG_MIPS_CP0_KSCRATCH4,
 595         KVM_REG_MIPS_CP0_KSCRATCH5,
 596         KVM_REG_MIPS_CP0_KSCRATCH6,
 597 };
 598
 599 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 600 {
 601         unsigned long ret;
 602
 603         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 604         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 605                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 606                 /* odd doubles */
 607                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 608                         ret += 16;
 609         }
 610         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 611                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 612         ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
 613         ret += kvm_mips_callbacks->num_regs(vcpu);
 614
 615         return ret;
 616 }
 617
 618 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 619 {
 620         u64 index;
 621         unsigned int i;
 622
 623         if (copy_to_user(indices, kvm_mips_get_one_regs,
 624                          sizeof(kvm_mips_get_one_regs)))
 625                 return -EFAULT;
 626         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 627
 628         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 629                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 630                                  sizeof(kvm_mips_get_one_regs_fpu)))
 631                         return -EFAULT;
 632                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 633
 634                 for (i = 0; i < 32; ++i) {
 635                         index = KVM_REG_MIPS_FPR_32(i);
 636                         if (copy_to_user(indices, &index, sizeof(index)))
 637                                 return -EFAULT;
 638                         ++indices;
 639
 640                         /* skip odd doubles if no F64 */
 641                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 642                                 continue;
 643
 644                         index = KVM_REG_MIPS_FPR_64(i);
 645                         if (copy_to_user(indices, &index, sizeof(index)))
 646                                 return -EFAULT;
 647                         ++indices;
 648                 }
 649         }
 650
 651         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 652                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 653                                  sizeof(kvm_mips_get_one_regs_msa)))
 654                         return -EFAULT;
 655                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 656
 657                 for (i = 0; i < 32; ++i) {
 658                         index = KVM_REG_MIPS_VEC_128(i);
 659                         if (copy_to_user(indices, &index, sizeof(index)))
 660                                 return -EFAULT;
 661                         ++indices;
 662                 }
 663         }
 664
 665         for (i = 0; i < 6; ++i) {
 666                 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
 667                         continue;
 668
 669                 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
 670                                  sizeof(kvm_mips_get_one_regs_kscratch[i])))
 671                         return -EFAULT;
 672                 ++indices;
 673         }
 674
 675         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 676 }
 677
 678 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 679                             const struct kvm_one_reg *reg)
 680 {
 681         struct mips_coproc *cop0 = vcpu->arch.cop0;
 682         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 683         int ret;
 684         s64 v;
 685         s64 vs[2];
 686         unsigned int idx;
 687
 688         switch (reg->id) {
 689         /* General purpose registers */
 690         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 691                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 692                 break;
 693 #ifndef CONFIG_CPU_MIPSR6
 694         case KVM_REG_MIPS_HI:
 695                 v = (long)vcpu->arch.hi;
 696                 break;
 697         case KVM_REG_MIPS_LO:
 698                 v = (long)vcpu->arch.lo;
 699                 break;
 700 #endif
 701         case KVM_REG_MIPS_PC:
 702                 v = (long)vcpu->arch.pc;
 703                 break;
 704
 705         /* Floating point registers */
 706         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 707                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 708                         return -EINVAL;
 709                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 710                 /* Odd singles in top of even double when FR=0 */
 711                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 712                         v = get_fpr32(&fpu->fpr[idx], 0);
 713                 else
 714                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 715                 break;
 716         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 717                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 718                         return -EINVAL;
 719                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 720                 /* Can't access odd doubles in FR=0 mode */
 721                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 722                         return -EINVAL;
 723                 v = get_fpr64(&fpu->fpr[idx], 0);
 724                 break;
 725         case KVM_REG_MIPS_FCR_IR:
 726                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 727                         return -EINVAL;
 728                 v = boot_cpu_data.fpu_id;
 729                 break;
 730         case KVM_REG_MIPS_FCR_CSR:
 731                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 732                         return -EINVAL;
 733                 v = fpu->fcr31;
 734                 break;
 735
 736         /* MIPS SIMD Architecture (MSA) registers */
 737         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 738                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 739                         return -EINVAL;
 740                 /* Can't access MSA registers in FR=0 mode */
 741                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 742                         return -EINVAL;
 743                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 744 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 745                 /* least significant byte first */
 746                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 747                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 748 #else
 749                 /* most significant byte first */
 750                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 751                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 752 #endif
 753                 break;
 754         case KVM_REG_MIPS_MSA_IR:
 755                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 756                         return -EINVAL;
 757                 v = boot_cpu_data.msa_id;
 758                 break;
 759         case KVM_REG_MIPS_MSA_CSR:
 760                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 761                         return -EINVAL;
 762                 v = fpu->msacsr;
 763                 break;
 764
 765         /* Co-processor 0 registers */
 766         case KVM_REG_MIPS_CP0_INDEX:
 767                 v = (long)kvm_read_c0_guest_index(cop0);
 768                 break;
 769         case KVM_REG_MIPS_CP0_CONTEXT:
 770                 v = (long)kvm_read_c0_guest_context(cop0);
 771                 break;
 772         case KVM_REG_MIPS_CP0_USERLOCAL:
 773                 v = (long)kvm_read_c0_guest_userlocal(cop0);
 774                 break;
 775         case KVM_REG_MIPS_CP0_PAGEMASK:
 776                 v = (long)kvm_read_c0_guest_pagemask(cop0);
 777                 break;
 778         case KVM_REG_MIPS_CP0_WIRED:
 779                 v = (long)kvm_read_c0_guest_wired(cop0);
 780                 break;
 781         case KVM_REG_MIPS_CP0_HWRENA:
 782                 v = (long)kvm_read_c0_guest_hwrena(cop0);
 783                 break;
 784         case KVM_REG_MIPS_CP0_BADVADDR:
 785                 v = (long)kvm_read_c0_guest_badvaddr(cop0);
 786                 break;
 787         case KVM_REG_MIPS_CP0_ENTRYHI:
 788                 v = (long)kvm_read_c0_guest_entryhi(cop0);
 789                 break;
 790         case KVM_REG_MIPS_CP0_COMPARE:
 791                 v = (long)kvm_read_c0_guest_compare(cop0);
 792                 break;
 793         case KVM_REG_MIPS_CP0_STATUS:
 794                 v = (long)kvm_read_c0_guest_status(cop0);
 795                 break;
 796         case KVM_REG_MIPS_CP0_CAUSE:
 797                 v = (long)kvm_read_c0_guest_cause(cop0);
 798                 break;
 799         case KVM_REG_MIPS_CP0_EPC:
 800                 v = (long)kvm_read_c0_guest_epc(cop0);
 801                 break;
 802         case KVM_REG_MIPS_CP0_PRID:
 803                 v = (long)kvm_read_c0_guest_prid(cop0);
 804                 break;
 805         case KVM_REG_MIPS_CP0_CONFIG:
 806                 v = (long)kvm_read_c0_guest_config(cop0);
 807                 break;
 808         case KVM_REG_MIPS_CP0_CONFIG1:
 809                 v = (long)kvm_read_c0_guest_config1(cop0);
 810                 break;
 811         case KVM_REG_MIPS_CP0_CONFIG2:
 812                 v = (long)kvm_read_c0_guest_config2(cop0);
 813                 break;
 814         case KVM_REG_MIPS_CP0_CONFIG3:
 815                 v = (long)kvm_read_c0_guest_config3(cop0);
 816                 break;
 817         case KVM_REG_MIPS_CP0_CONFIG4:
 818                 v = (long)kvm_read_c0_guest_config4(cop0);
 819                 break;
 820         case KVM_REG_MIPS_CP0_CONFIG5:
 821                 v = (long)kvm_read_c0_guest_config5(cop0);
 822                 break;
 823         case KVM_REG_MIPS_CP0_CONFIG7:
 824                 v = (long)kvm_read_c0_guest_config7(cop0);
 825                 break;
 826         case KVM_REG_MIPS_CP0_ERROREPC:
 827                 v = (long)kvm_read_c0_guest_errorepc(cop0);
 828                 break;
 829         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
 830                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
 831                 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
 832                         return -EINVAL;
 833                 switch (idx) {
 834                 case 2:
 835                         v = (long)kvm_read_c0_guest_kscratch1(cop0);
 836                         break;
 837                 case 3:
 838                         v = (long)kvm_read_c0_guest_kscratch2(cop0);
 839                         break;
 840                 case 4:
 841                         v = (long)kvm_read_c0_guest_kscratch3(cop0);
 842                         break;
 843                 case 5:
 844                         v = (long)kvm_read_c0_guest_kscratch4(cop0);
 845                         break;
 846                 case 6:
 847                         v = (long)kvm_read_c0_guest_kscratch5(cop0);
 848                         break;
 849                 case 7:
 850                         v = (long)kvm_read_c0_guest_kscratch6(cop0);
 851                         break;
 852                 }
 853                 break;
 854         /* registers to be handled specially */
 855         default:
 856                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 857                 if (ret)
 858                         return ret;
 859                 break;
 860         }
 861         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 862                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 863
 864                 return put_user(v, uaddr64);
 865         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 866                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 867                 u32 v32 = (u32)v;
 868
 869                 return put_user(v32, uaddr32);
 870         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 871                 void __user *uaddr = (void __user *)(long)reg->addr;
 872
 873                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 874         } else {
 875                 return -EINVAL;
 876         }
 877 }
 878
 879 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 880                             const struct kvm_one_reg *reg)
 881 {
 882         struct mips_coproc *cop0 = vcpu->arch.cop0;
 883         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 884         s64 v;
 885         s64 vs[2];
 886         unsigned int idx;
 887
 888         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 889                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 890
 891                 if (get_user(v, uaddr64) != 0)
 892                         return -EFAULT;
 893         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 894                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 895                 s32 v32;
 896
 897                 if (get_user(v32, uaddr32) != 0)
 898                         return -EFAULT;
 899                 v = (s64)v32;
 900         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 901                 void __user *uaddr = (void __user *)(long)reg->addr;
 902
 903                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 904         } else {
 905                 return -EINVAL;
 906         }
 907
 908         switch (reg->id) {
 909         /* General purpose registers */
 910         case KVM_REG_MIPS_R0:
 911                 /* Silently ignore requests to set $0 */
 912                 break;
 913         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 914                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 915                 break;
 916 #ifndef CONFIG_CPU_MIPSR6
 917         case KVM_REG_MIPS_HI:
 918                 vcpu->arch.hi = v;
 919                 break;
 920         case KVM_REG_MIPS_LO:
 921                 vcpu->arch.lo = v;
 922                 break;
 923 #endif
 924         case KVM_REG_MIPS_PC:
 925                 vcpu->arch.pc = v;
 926                 break;
 927
 928         /* Floating point registers */
 929         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 930                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 931                         return -EINVAL;
 932                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 933                 /* Odd singles in top of even double when FR=0 */
 934                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 935                         set_fpr32(&fpu->fpr[idx], 0, v);
 936                 else
 937                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 938                 break;
 939         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 940                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 941                         return -EINVAL;
 942                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 943                 /* Can't access odd doubles in FR=0 mode */
 944                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 945                         return -EINVAL;
 946                 set_fpr64(&fpu->fpr[idx], 0, v);
 947                 break;
 948         case KVM_REG_MIPS_FCR_IR:
 949                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 950                         return -EINVAL;
 951                 /* Read-only */
 952                 break;
 953         case KVM_REG_MIPS_FCR_CSR:
 954                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 955                         return -EINVAL;
 956                 fpu->fcr31 = v;
 957                 break;
 958
 959         /* MIPS SIMD Architecture (MSA) registers */
 960         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 961                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 962                         return -EINVAL;
 963                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 964 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 965                 /* least significant byte first */
 966                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 967                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 968 #else
 969                 /* most significant byte first */
 970                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 971                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 972 #endif
 973                 break;
 974         case KVM_REG_MIPS_MSA_IR:
 975                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 976                         return -EINVAL;
 977                 /* Read-only */
 978                 break;
 979         case KVM_REG_MIPS_MSA_CSR:
 980                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 981                         return -EINVAL;
 982                 fpu->msacsr = v;
 983                 break;
 984
 985         /* Co-processor 0 registers */
 986         case KVM_REG_MIPS_CP0_INDEX:
 987                 kvm_write_c0_guest_index(cop0, v);
 988                 break;
 989         case KVM_REG_MIPS_CP0_CONTEXT:
 990                 kvm_write_c0_guest_context(cop0, v);
 991                 break;
 992         case KVM_REG_MIPS_CP0_USERLOCAL:
 993                 kvm_write_c0_guest_userlocal(cop0, v);
 994                 break;
 995         case KVM_REG_MIPS_CP0_PAGEMASK:
 996                 kvm_write_c0_guest_pagemask(cop0, v);
 997                 break;
 998         case KVM_REG_MIPS_CP0_WIRED:
 999                 kvm_write_c0_guest_wired(cop0, v);
1000                 break;
1001         case KVM_REG_MIPS_CP0_HWRENA:
1002                 kvm_write_c0_guest_hwrena(cop0, v);
1003                 break;
1004         case KVM_REG_MIPS_CP0_BADVADDR:
1005                 kvm_write_c0_guest_badvaddr(cop0, v);
1006                 break;
1007         case KVM_REG_MIPS_CP0_ENTRYHI:
1008                 kvm_write_c0_guest_entryhi(cop0, v);
1009                 break;
1010         case KVM_REG_MIPS_CP0_STATUS:
1011                 kvm_write_c0_guest_status(cop0, v);
1012                 break;
1013         case KVM_REG_MIPS_CP0_EPC:
1014                 kvm_write_c0_guest_epc(cop0, v);
1015                 break;
1016         case KVM_REG_MIPS_CP0_PRID:
1017                 kvm_write_c0_guest_prid(cop0, v);
1018                 break;
1019         case KVM_REG_MIPS_CP0_ERROREPC:
1020                 kvm_write_c0_guest_errorepc(cop0, v);
1021                 break;
1022         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
1023                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
1024                 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
1025                         return -EINVAL;
1026                 switch (idx) {
1027                 case 2:
1028                         kvm_write_c0_guest_kscratch1(cop0, v);
1029                         break;
1030                 case 3:
1031                         kvm_write_c0_guest_kscratch2(cop0, v);
1032                         break;
1033                 case 4:
1034                         kvm_write_c0_guest_kscratch3(cop0, v);
1035                         break;
1036                 case 5:
1037                         kvm_write_c0_guest_kscratch4(cop0, v);
1038                         break;
1039                 case 6:
1040                         kvm_write_c0_guest_kscratch5(cop0, v);
1041                         break;
1042                 case 7:
1043                         kvm_write_c0_guest_kscratch6(cop0, v);
1044                         break;
1045                 }
1046                 break;
1047         /* registers to be handled specially */
1048         default:
1049                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
1050         }
1051         return 0;
1052 }
1053
1054 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1055                                      struct kvm_enable_cap *cap)
1056 {
1057         int r = 0;
1058
1059         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1060                 return -EINVAL;
1061         if (cap->flags)
1062                 return -EINVAL;
1063         if (cap->args[0])
1064                 return -EINVAL;
1065
1066         switch (cap->cap) {
1067         case KVM_CAP_MIPS_FPU:
1068                 vcpu->arch.fpu_enabled = true;
1069                 break;
1070         case KVM_CAP_MIPS_MSA:
1071                 vcpu->arch.msa_enabled = true;
1072                 break;
1073         default:
1074                 r = -EINVAL;
1075                 break;
1076         }
1077
1078         return r;
1079 }
1080
1081 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1082                          unsigned long arg)
1083 {
1084         struct kvm_vcpu *vcpu = filp->private_data;
1085         void __user *argp = (void __user *)arg;
1086         long r;
1087
1088         switch (ioctl) {
1089         case KVM_SET_ONE_REG:
1090         case KVM_GET_ONE_REG: {
1091                 struct kvm_one_reg reg;
1092
1093                 if (copy_from_user(&reg, argp, sizeof(reg)))
1094                         return -EFAULT;
1095                 if (ioctl == KVM_SET_ONE_REG)
1096                         return kvm_mips_set_reg(vcpu, &reg);
1097                 else
1098                         return kvm_mips_get_reg(vcpu, &reg);
1099         }
1100         case KVM_GET_REG_LIST: {
1101                 struct kvm_reg_list __user *user_list = argp;
1102                 struct kvm_reg_list reg_list;
1103                 unsigned n;
1104
1105                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
1106                         return -EFAULT;
1107                 n = reg_list.n;
1108                 reg_list.n = kvm_mips_num_regs(vcpu);
1109                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
1110                         return -EFAULT;
1111                 if (n < reg_list.n)
1112                         return -E2BIG;
1113                 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
1114         }
1115         case KVM_NMI:
1116                 /* Treat the NMI as a CPU reset */
1117                 r = kvm_mips_reset_vcpu(vcpu);
1118                 break;
1119         case KVM_INTERRUPT:
1120                 {
1121                         struct kvm_mips_interrupt irq;
1122
1123                         r = -EFAULT;
1124                         if (copy_from_user(&irq, argp, sizeof(irq)))
1125                                 goto out;
1126
1127                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1128                                   irq.irq);
1129
1130                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1131                         break;
1132                 }
1133         case KVM_ENABLE_CAP: {
1134                 struct kvm_enable_cap cap;
1135
1136                 r = -EFAULT;
1137                 if (copy_from_user(&cap, argp, sizeof(cap)))
1138                         goto out;
1139                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1140                 break;
1141         }
1142         default:
1143                 r = -ENOIOCTLCMD;
1144         }
1145
1146 out:
1147         return r;
1148 }
1149
1150 /* Get (and clear) the dirty memory log for a memory slot. */
1151 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1152 {
1153         struct kvm_memslots *slots;
1154         struct kvm_memory_slot *memslot;
1155         unsigned long ga, ga_end;
1156         int is_dirty = 0;
1157         int r;
1158         unsigned long n;
1159
1160         mutex_lock(&kvm->slots_lock);
1161
1162         r = kvm_get_dirty_log(kvm, log, &is_dirty);
1163         if (r)
1164                 goto out;
1165
1166         /* If nothing is dirty, don't bother messing with page tables. */
1167         if (is_dirty) {
1168                 slots = kvm_memslots(kvm);
1169                 memslot = id_to_memslot(slots, log->slot);
1170
1171                 ga = memslot->base_gfn << PAGE_SHIFT;
1172                 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1173
1174                 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1175                          ga_end);
1176
1177                 n = kvm_dirty_bitmap_bytes(memslot);
1178                 memset(memslot->dirty_bitmap, 0, n);
1179         }
1180
1181         r = 0;
1182 out:
1183         mutex_unlock(&kvm->slots_lock);
1184         return r;
1185
1186 }
1187
1188 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1189 {
1190         long r;
1191
1192         switch (ioctl) {
1193         default:
1194                 r = -ENOIOCTLCMD;
1195         }
1196
1197         return r;
1198 }
1199
1200 int kvm_arch_init(void *opaque)
1201 {
1202         if (kvm_mips_callbacks) {
1203                 kvm_err("kvm: module already exists\n");
1204                 return -EEXIST;
1205         }
1206
1207         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1208 }
1209
1210 void kvm_arch_exit(void)
1211 {
1212         kvm_mips_callbacks = NULL;
1213 }
1214
1215 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1216                                   struct kvm_sregs *sregs)
1217 {
1218         return -ENOIOCTLCMD;
1219 }
1220
1221 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1222                                   struct kvm_sregs *sregs)
1223 {
1224         return -ENOIOCTLCMD;
1225 }
1226
1227 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1228 {
1229 }
1230
1231 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1232 {
1233         return -ENOIOCTLCMD;
1234 }
1235
1236 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1237 {
1238         return -ENOIOCTLCMD;
1239 }
1240
1241 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1242 {
1243         return VM_FAULT_SIGBUS;
1244 }
1245
1246 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1247 {
1248         int r;
1249
1250         switch (ext) {
1251         case KVM_CAP_ONE_REG:
1252         case KVM_CAP_ENABLE_CAP:
1253                 r = 1;
1254                 break;
1255         case KVM_CAP_COALESCED_MMIO:
1256                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1257                 break;
1258         case KVM_CAP_MIPS_FPU:
1259                 /* We don't handle systems with inconsistent cpu_has_fpu */
1260                 r = !!raw_cpu_has_fpu;
1261                 break;
1262         case KVM_CAP_MIPS_MSA:
1263                 /*
1264                  * We don't support MSA vector partitioning yet:
1265                  * 1) It would require explicit support which can't be tested
1266                  *    yet due to lack of support in current hardware.
1267                  * 2) It extends the state that would need to be saved/restored
1268                  *    by e.g. QEMU for migration.
1269                  *
1270                  * When vector partitioning hardware becomes available, support
1271                  * could be added by requiring a flag when enabling
1272                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1273                  * to save/restore the appropriate extra state.
1274                  */
1275                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1276                 break;
1277         default:
1278                 r = 0;
1279                 break;
1280         }
1281         return r;
1282 }
1283
1284 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1285 {
1286         return kvm_mips_pending_timer(vcpu);
1287 }
1288
1289 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1290 {
1291         int i;
1292         struct mips_coproc *cop0;
1293
1294         if (!vcpu)
1295                 return -1;
1296
1297         kvm_debug("VCPU Register Dump:\n");
1298         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1299         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1300
1301         for (i = 0; i < 32; i += 4) {
1302                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1303                        vcpu->arch.gprs[i],
1304                        vcpu->arch.gprs[i + 1],
1305                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1306         }
1307         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1308         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1309
1310         cop0 = vcpu->arch.cop0;
1311         kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1312                   kvm_read_c0_guest_status(cop0),
1313                   kvm_read_c0_guest_cause(cop0));
1314
1315         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1316
1317         return 0;
1318 }
1319
1320 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1321 {
1322         int i;
1323
1324         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1325                 vcpu->arch.gprs[i] = regs->gpr[i];
1326         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1327         vcpu->arch.hi = regs->hi;
1328         vcpu->arch.lo = regs->lo;
1329         vcpu->arch.pc = regs->pc;
1330
1331         return 0;
1332 }
1333
1334 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1335 {
1336         int i;
1337
1338         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1339                 regs->gpr[i] = vcpu->arch.gprs[i];
1340
1341         regs->hi = vcpu->arch.hi;
1342         regs->lo = vcpu->arch.lo;
1343         regs->pc = vcpu->arch.pc;
1344
1345         return 0;
1346 }
1347
1348 static void kvm_mips_comparecount_func(unsigned long data)
1349 {
1350         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1351
1352         kvm_mips_callbacks->queue_timer_int(vcpu);
1353
1354         vcpu->arch.wait = 0;
1355         if (swait_active(&vcpu->wq))
1356                 swake_up(&vcpu->wq);
1357 }
1358
1359 /* low level hrtimer wake routine */
1360 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1361 {
1362         struct kvm_vcpu *vcpu;
1363
1364         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1365         kvm_mips_comparecount_func((unsigned long) vcpu);
1366         return kvm_mips_count_timeout(vcpu);
1367 }
1368
1369 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1370 {
1371         kvm_mips_callbacks->vcpu_init(vcpu);
1372         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1373                      HRTIMER_MODE_REL);
1374         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1375         return 0;
1376 }
1377
1378 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1379                                   struct kvm_translation *tr)
1380 {
1381         return 0;
1382 }
1383
1384 /* Initial guest state */
1385 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1386 {
1387         return kvm_mips_callbacks->vcpu_setup(vcpu);
1388 }
1389
1390 static void kvm_mips_set_c0_status(void)
1391 {
1392         u32 status = read_c0_status();
1393
1394         if (cpu_has_dsp)
1395                 status |= (ST0_MX);
1396
1397         write_c0_status(status);
1398         ehb();
1399 }
1400
1401 /*
1402  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1403  */
1404 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1405 {
1406         u32 cause = vcpu->arch.host_cp0_cause;
1407         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1408         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1409         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1410         enum emulation_result er = EMULATE_DONE;
1411         int ret = RESUME_GUEST;
1412
1413         /* re-enable HTW before enabling interrupts */
1414         htw_start();
1415
1416         /* Set a default exit reason */
1417         run->exit_reason = KVM_EXIT_UNKNOWN;
1418         run->ready_for_interrupt_injection = 1;
1419
1420         /*
1421          * Set the appropriate status bits based on host CPU features,
1422          * before we hit the scheduler
1423          */
1424         kvm_mips_set_c0_status();
1425
1426         local_irq_enable();
1427
1428         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1429                         cause, opc, run, vcpu);
1430         trace_kvm_exit(vcpu, exccode);
1431
1432         /*
1433          * Do a privilege check, if in UM most of these exit conditions end up
1434          * causing an exception to be delivered to the Guest Kernel
1435          */
1436         er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1437         if (er == EMULATE_PRIV_FAIL) {
1438                 goto skip_emul;
1439         } else if (er == EMULATE_FAIL) {
1440                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1441                 ret = RESUME_HOST;
1442                 goto skip_emul;
1443         }
1444
1445         switch (exccode) {
1446         case EXCCODE_INT:
1447                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1448
1449                 ++vcpu->stat.int_exits;
1450
1451                 if (need_resched())
1452                         cond_resched();
1453
1454                 ret = RESUME_GUEST;
1455                 break;
1456
1457         case EXCCODE_CPU:
1458                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1459
1460                 ++vcpu->stat.cop_unusable_exits;
1461                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1462                 /* XXXKYMA: Might need to return to user space */
1463                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1464                         ret = RESUME_HOST;
1465                 break;
1466
1467         case EXCCODE_MOD:
1468                 ++vcpu->stat.tlbmod_exits;
1469                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1470                 break;
1471
1472         case EXCCODE_TLBS:
1473                 kvm_debug("TLB ST fault:  cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1474                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1475                           badvaddr);
1476
1477                 ++vcpu->stat.tlbmiss_st_exits;
1478                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1479                 break;
1480
1481         case EXCCODE_TLBL:
1482                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1483                           cause, opc, badvaddr);
1484
1485                 ++vcpu->stat.tlbmiss_ld_exits;
1486                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1487                 break;
1488
1489         case EXCCODE_ADES:
1490                 ++vcpu->stat.addrerr_st_exits;
1491                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1492                 break;
1493
1494         case EXCCODE_ADEL:
1495                 ++vcpu->stat.addrerr_ld_exits;
1496                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1497                 break;
1498
1499         case EXCCODE_SYS:
1500                 ++vcpu->stat.syscall_exits;
1501                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1502                 break;
1503
1504         case EXCCODE_RI:
1505                 ++vcpu->stat.resvd_inst_exits;
1506                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1507                 break;
1508
1509         case EXCCODE_BP:
1510                 ++vcpu->stat.break_inst_exits;
1511                 ret = kvm_mips_callbacks->handle_break(vcpu);
1512                 break;
1513
1514         case EXCCODE_TR:
1515                 ++vcpu->stat.trap_inst_exits;
1516                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1517                 break;
1518
1519         case EXCCODE_MSAFPE:
1520                 ++vcpu->stat.msa_fpe_exits;
1521                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1522                 break;
1523
1524         case EXCCODE_FPE:
1525                 ++vcpu->stat.fpe_exits;
1526                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1527                 break;
1528
1529         case EXCCODE_MSADIS:
1530                 ++vcpu->stat.msa_disabled_exits;
1531                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1532                 break;
1533
1534         default:
1535                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#lx\n",
1536                         exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1537                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1538                 kvm_arch_vcpu_dump_regs(vcpu);
1539                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1540                 ret = RESUME_HOST;
1541                 break;
1542
1543         }
1544
1545 skip_emul:
1546         local_irq_disable();
1547
1548         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1549                 kvm_mips_deliver_interrupts(vcpu, cause);
1550
1551         if (!(ret & RESUME_HOST)) {
1552                 /* Only check for signals if not already exiting to userspace */
1553                 if (signal_pending(current)) {
1554                         run->exit_reason = KVM_EXIT_INTR;
1555                         ret = (-EINTR << 2) | RESUME_HOST;
1556                         ++vcpu->stat.signal_exits;
1557                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1558                 }
1559         }
1560
1561         if (ret == RESUME_GUEST) {
1562                 trace_kvm_reenter(vcpu);
1563
1564                 /*
1565                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1566                  * is live), restore FCR31 / MSACSR.
1567                  *
1568                  * This should be before returning to the guest exception
1569                  * vector, as it may well cause an [MSA] FP exception if there
1570                  * are pending exception bits unmasked. (see
1571                  * kvm_mips_csr_die_notifier() for how that is handled).
1572                  */
1573                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1574                     read_c0_status() & ST0_CU1)
1575                         __kvm_restore_fcsr(&vcpu->arch);
1576
1577                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1578                     read_c0_config5() & MIPS_CONF5_MSAEN)
1579                         __kvm_restore_msacsr(&vcpu->arch);
1580         }
1581
1582         /* Disable HTW before returning to guest or host */
1583         htw_stop();
1584
1585         return ret;
1586 }
1587
1588 /* Enable FPU for guest and restore context */
1589 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1590 {
1591         struct mips_coproc *cop0 = vcpu->arch.cop0;
1592         unsigned int sr, cfg5;
1593
1594         preempt_disable();
1595
1596         sr = kvm_read_c0_guest_status(cop0);
1597
1598         /*
1599          * If MSA state is already live, it is undefined how it interacts with
1600          * FR=0 FPU state, and we don't want to hit reserved instruction
1601          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1602          * play it safe and save it first.
1603          *
1604          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1605          * get called when guest CU1 is set, however we can't trust the guest
1606          * not to clobber the status register directly via the commpage.
1607          */
1608         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1609             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1610                 kvm_lose_fpu(vcpu);
1611
1612         /*
1613          * Enable FPU for guest
1614          * We set FR and FRE according to guest context
1615          */
1616         change_c0_status(ST0_CU1 | ST0_FR, sr);
1617         if (cpu_has_fre) {
1618                 cfg5 = kvm_read_c0_guest_config5(cop0);
1619                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1620         }
1621         enable_fpu_hazard();
1622
1623         /* If guest FPU state not active, restore it now */
1624         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1625                 __kvm_restore_fpu(&vcpu->arch);
1626                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1627                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1628         } else {
1629                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1630         }
1631
1632         preempt_enable();
1633 }
1634
1635 #ifdef CONFIG_CPU_HAS_MSA
1636 /* Enable MSA for guest and restore context */
1637 void kvm_own_msa(struct kvm_vcpu *vcpu)
1638 {
1639         struct mips_coproc *cop0 = vcpu->arch.cop0;
1640         unsigned int sr, cfg5;
1641
1642         preempt_disable();
1643
1644         /*
1645          * Enable FPU if enabled in guest, since we're restoring FPU context
1646          * anyway. We set FR and FRE according to guest context.
1647          */
1648         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1649                 sr = kvm_read_c0_guest_status(cop0);
1650
1651                 /*
1652                  * If FR=0 FPU state is already live, it is undefined how it
1653                  * interacts with MSA state, so play it safe and save it first.
1654                  */
1655                 if (!(sr & ST0_FR) &&
1656                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1657                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1658                         kvm_lose_fpu(vcpu);
1659
1660                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1661                 if (sr & ST0_CU1 && cpu_has_fre) {
1662                         cfg5 = kvm_read_c0_guest_config5(cop0);
1663                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1664                 }
1665         }
1666
1667         /* Enable MSA for guest */
1668         set_c0_config5(MIPS_CONF5_MSAEN);
1669         enable_fpu_hazard();
1670
1671         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1672         case KVM_MIPS_AUX_FPU:
1673                 /*
1674                  * Guest FPU state already loaded, only restore upper MSA state
1675                  */
1676                 __kvm_restore_msa_upper(&vcpu->arch);
1677                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1678                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1679                 break;
1680         case 0:
1681                 /* Neither FPU or MSA already active, restore full MSA state */
1682                 __kvm_restore_msa(&vcpu->arch);
1683                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1684                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1685                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1686                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1687                               KVM_TRACE_AUX_FPU_MSA);
1688                 break;
1689         default:
1690                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1691                 break;
1692         }
1693
1694         preempt_enable();
1695 }
1696 #endif
1697
1698 /* Drop FPU & MSA without saving it */
1699 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1700 {
1701         preempt_disable();
1702         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1703                 disable_msa();
1704                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1705                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1706         }
1707         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1708                 clear_c0_status(ST0_CU1 | ST0_FR);
1709                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1710                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1711         }
1712         preempt_enable();
1713 }
1714
1715 /* Save and disable FPU & MSA */
1716 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1717 {
1718         /*
1719          * FPU & MSA get disabled in root context (hardware) when it is disabled
1720          * in guest context (software), but the register state in the hardware
1721          * may still be in use. This is why we explicitly re-enable the hardware
1722          * before saving.
1723          */
1724
1725         preempt_disable();
1726         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1727                 set_c0_config5(MIPS_CONF5_MSAEN);
1728                 enable_fpu_hazard();
1729
1730                 __kvm_save_msa(&vcpu->arch);
1731                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1732
1733                 /* Disable MSA & FPU */
1734                 disable_msa();
1735                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1736                         clear_c0_status(ST0_CU1 | ST0_FR);
1737                         disable_fpu_hazard();
1738                 }
1739                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1740         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1741                 set_c0_status(ST0_CU1);
1742                 enable_fpu_hazard();
1743
1744                 __kvm_save_fpu(&vcpu->arch);
1745                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1746                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1747
1748                 /* Disable FPU */
1749                 clear_c0_status(ST0_CU1 | ST0_FR);
1750                 disable_fpu_hazard();
1751         }
1752         preempt_enable();
1753 }
1754
1755 /*
1756  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1757  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1758  * exception if cause bits are set in the value being written.
1759  */
1760 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1761                                    unsigned long cmd, void *ptr)
1762 {
1763         struct die_args *args = (struct die_args *)ptr;
1764         struct pt_regs *regs = args->regs;
1765         unsigned long pc;
1766
1767         /* Only interested in FPE and MSAFPE */
1768         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1769                 return NOTIFY_DONE;
1770
1771         /* Return immediately if guest context isn't active */
1772         if (!(current->flags & PF_VCPU))
1773                 return NOTIFY_DONE;
1774
1775         /* Should never get here from user mode */
1776         BUG_ON(user_mode(regs));
1777
1778         pc = instruction_pointer(regs);
1779         switch (cmd) {
1780         case DIE_FP:
1781                 /* match 2nd instruction in __kvm_restore_fcsr */
1782                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1783                         return NOTIFY_DONE;
1784                 break;
1785         case DIE_MSAFP:
1786                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1787                 if (!cpu_has_msa ||
1788                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1789                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1790                         return NOTIFY_DONE;
1791                 break;
1792         }
1793
1794         /* Move PC forward a little and continue executing */
1795         instruction_pointer(regs) += 4;
1796
1797         return NOTIFY_STOP;
1798 }
1799
1800 static struct notifier_block kvm_mips_csr_die_notifier = {
1801         .notifier_call = kvm_mips_csr_die_notify,
1802 };
1803
1804 static int __init kvm_mips_init(void)
1805 {
1806         int ret;
1807
1808         ret = kvm_mips_entry_setup();
1809         if (ret)
1810                 return ret;
1811
1812         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1813
1814         if (ret)
1815                 return ret;
1816
1817         register_die_notifier(&kvm_mips_csr_die_notifier);
1818
1819         return 0;
1820 }
1821
1822 static void __exit kvm_mips_exit(void)
1823 {
1824         kvm_exit();
1825
1826         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1827 }
1828
1829 module_init(kvm_mips_init);
1830 module_exit(kvm_mips_exit);
1831
1832 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);