2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/kdebug.h>
15 #include <linux/module.h>
16 #include <linux/vmalloc.h>
18 #include <linux/bootmem.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mmu_context.h>
23 #include <asm/pgtable.h>
25 #include <linux/kvm_host.h>
27 #include "interrupt.h"
30 #define CREATE_TRACE_POINTS
34 #define VECTORSPACING 0x100 /* for EI/VI mode */
37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
38 struct kvm_stats_debugfs_item debugfs_entries[] = {
39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
58 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
59 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
60 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
64 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
68 for_each_possible_cpu(i) {
69 vcpu->arch.guest_kernel_asid[i] = 0;
70 vcpu->arch.guest_user_asid[i] = 0;
77 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
78 * Config7, so we are "runnable" if interrupts are pending
80 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
82 return !!(vcpu->arch.pending_exceptions);
85 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
90 int kvm_arch_hardware_enable(void)
95 int kvm_arch_hardware_setup(void)
100 void kvm_arch_check_processor_compat(void *rtn)
105 static void kvm_mips_init_tlbs(struct kvm *kvm)
110 * Add a wired entry to the TLB, it is used to map the commpage to
113 wired = read_c0_wired();
114 write_c0_wired(wired + 1);
116 kvm->arch.commpage_tlb = wired;
118 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
119 kvm->arch.commpage_tlb);
122 static void kvm_mips_init_vm_percpu(void *arg)
124 struct kvm *kvm = (struct kvm *)arg;
126 kvm_mips_init_tlbs(kvm);
127 kvm_mips_callbacks->vm_init(kvm);
131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
133 if (atomic_inc_return(&kvm_mips_instance) == 1) {
134 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
136 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
142 void kvm_mips_free_vcpus(struct kvm *kvm)
145 struct kvm_vcpu *vcpu;
147 /* Put the pages we reserved for the guest pmap */
148 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
149 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
150 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
152 kfree(kvm->arch.guest_pmap);
154 kvm_for_each_vcpu(i, vcpu, kvm) {
155 kvm_arch_vcpu_free(vcpu);
158 mutex_lock(&kvm->lock);
160 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
161 kvm->vcpus[i] = NULL;
163 atomic_set(&kvm->online_vcpus, 0);
165 mutex_unlock(&kvm->lock);
168 static void kvm_mips_uninit_tlbs(void *arg)
170 /* Restore wired count */
173 /* Clear out all the TLBs */
174 kvm_local_flush_tlb_all();
177 void kvm_arch_destroy_vm(struct kvm *kvm)
179 kvm_mips_free_vcpus(kvm);
181 /* If this is the last instance, restore wired count */
182 if (atomic_dec_return(&kvm_mips_instance) == 0) {
183 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
185 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
189 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
195 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
196 unsigned long npages)
201 int kvm_arch_prepare_memory_region(struct kvm *kvm,
202 struct kvm_memory_slot *memslot,
203 const struct kvm_userspace_memory_region *mem,
204 enum kvm_mr_change change)
209 void kvm_arch_commit_memory_region(struct kvm *kvm,
210 const struct kvm_userspace_memory_region *mem,
211 const struct kvm_memory_slot *old,
212 const struct kvm_memory_slot *new,
213 enum kvm_mr_change change)
215 unsigned long npages = 0;
218 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
219 __func__, kvm, mem->slot, mem->guest_phys_addr,
220 mem->memory_size, mem->userspace_addr);
222 /* Setup Guest PMAP table */
223 if (!kvm->arch.guest_pmap) {
225 npages = mem->memory_size >> PAGE_SHIFT;
228 kvm->arch.guest_pmap_npages = npages;
229 kvm->arch.guest_pmap =
230 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
232 if (!kvm->arch.guest_pmap) {
233 kvm_err("Failed to allocate guest PMAP\n");
237 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
238 npages, kvm->arch.guest_pmap);
240 /* Now setup the page table */
241 for (i = 0; i < npages; i++)
242 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
247 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
249 int err, size, offset;
253 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
260 err = kvm_vcpu_init(vcpu, kvm, id);
265 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
268 * Allocate space for host mode exception handlers that handle
271 if (cpu_has_veic || cpu_has_vint)
272 size = 0x200 + VECTORSPACING * 64;
276 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
282 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
283 ALIGN(size, PAGE_SIZE), gebase);
286 vcpu->arch.guest_ebase = gebase;
288 /* Copy L1 Guest Exception handler to correct offset */
290 /* TLB Refill, EXL = 0 */
291 memcpy(gebase, mips32_exception,
292 mips32_exceptionEnd - mips32_exception);
294 /* General Exception Entry point */
295 memcpy(gebase + 0x180, mips32_exception,
296 mips32_exceptionEnd - mips32_exception);
298 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
299 for (i = 0; i < 8; i++) {
300 kvm_debug("L1 Vectored handler @ %p\n",
301 gebase + 0x200 + (i * VECTORSPACING));
302 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
303 mips32_exceptionEnd - mips32_exception);
306 /* General handler, relocate to unmapped space for sanity's sake */
308 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
310 mips32_GuestExceptionEnd - mips32_GuestException);
312 memcpy(gebase + offset, mips32_GuestException,
313 mips32_GuestExceptionEnd - mips32_GuestException);
316 offset += mips32_GuestExceptionEnd - mips32_GuestException;
317 memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
318 __kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
319 vcpu->arch.vcpu_run = gebase + offset;
321 vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
324 /* Invalidate the icache for these ranges */
325 local_flush_icache_range((unsigned long)gebase,
326 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
329 * Allocate comm page for guest kernel, a TLB will be reserved for
330 * mapping GVA @ 0xFFFF8000 to this page
332 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
334 if (!vcpu->arch.kseg0_commpage) {
336 goto out_free_gebase;
339 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
340 kvm_mips_commpage_init(vcpu);
343 vcpu->arch.last_sched_cpu = -1;
345 /* Start off the timer */
346 kvm_mips_init_count(vcpu);
354 kvm_vcpu_uninit(vcpu);
363 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
365 hrtimer_cancel(&vcpu->arch.comparecount_timer);
367 kvm_vcpu_uninit(vcpu);
369 kvm_mips_dump_stats(vcpu);
371 kfree(vcpu->arch.guest_ebase);
372 kfree(vcpu->arch.kseg0_commpage);
376 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
378 kvm_arch_vcpu_free(vcpu);
381 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
382 struct kvm_guest_debug *dbg)
387 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
392 if (vcpu->sigset_active)
393 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
395 if (vcpu->mmio_needed) {
396 if (!vcpu->mmio_is_write)
397 kvm_mips_complete_mmio_load(vcpu, run);
398 vcpu->mmio_needed = 0;
404 /* Check if we have any exceptions/interrupts pending */
405 kvm_mips_deliver_interrupts(vcpu,
406 kvm_read_c0_guest_cause(vcpu->arch.cop0));
410 /* Disable hardware page table walking while in guest */
413 r = vcpu->arch.vcpu_run(run, vcpu);
415 /* Re-enable HTW before enabling interrupts */
421 if (vcpu->sigset_active)
422 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
427 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
428 struct kvm_mips_interrupt *irq)
430 int intr = (int)irq->irq;
431 struct kvm_vcpu *dvcpu = NULL;
433 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
434 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
440 dvcpu = vcpu->kvm->vcpus[irq->cpu];
442 if (intr == 2 || intr == 3 || intr == 4) {
443 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
445 } else if (intr == -2 || intr == -3 || intr == -4) {
446 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
448 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
453 dvcpu->arch.wait = 0;
455 if (swait_active(&dvcpu->wq))
456 swake_up(&dvcpu->wq);
461 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
462 struct kvm_mp_state *mp_state)
467 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
468 struct kvm_mp_state *mp_state)
473 static u64 kvm_mips_get_one_regs[] = {
511 KVM_REG_MIPS_CP0_INDEX,
512 KVM_REG_MIPS_CP0_CONTEXT,
513 KVM_REG_MIPS_CP0_USERLOCAL,
514 KVM_REG_MIPS_CP0_PAGEMASK,
515 KVM_REG_MIPS_CP0_WIRED,
516 KVM_REG_MIPS_CP0_HWRENA,
517 KVM_REG_MIPS_CP0_BADVADDR,
518 KVM_REG_MIPS_CP0_COUNT,
519 KVM_REG_MIPS_CP0_ENTRYHI,
520 KVM_REG_MIPS_CP0_COMPARE,
521 KVM_REG_MIPS_CP0_STATUS,
522 KVM_REG_MIPS_CP0_CAUSE,
523 KVM_REG_MIPS_CP0_EPC,
524 KVM_REG_MIPS_CP0_PRID,
525 KVM_REG_MIPS_CP0_CONFIG,
526 KVM_REG_MIPS_CP0_CONFIG1,
527 KVM_REG_MIPS_CP0_CONFIG2,
528 KVM_REG_MIPS_CP0_CONFIG3,
529 KVM_REG_MIPS_CP0_CONFIG4,
530 KVM_REG_MIPS_CP0_CONFIG5,
531 KVM_REG_MIPS_CP0_CONFIG7,
532 KVM_REG_MIPS_CP0_ERROREPC,
534 KVM_REG_MIPS_COUNT_CTL,
535 KVM_REG_MIPS_COUNT_RESUME,
536 KVM_REG_MIPS_COUNT_HZ,
539 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
540 const struct kvm_one_reg *reg)
542 struct mips_coproc *cop0 = vcpu->arch.cop0;
543 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
550 /* General purpose registers */
551 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
552 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
554 case KVM_REG_MIPS_HI:
555 v = (long)vcpu->arch.hi;
557 case KVM_REG_MIPS_LO:
558 v = (long)vcpu->arch.lo;
560 case KVM_REG_MIPS_PC:
561 v = (long)vcpu->arch.pc;
564 /* Floating point registers */
565 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
566 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
568 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
569 /* Odd singles in top of even double when FR=0 */
570 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
571 v = get_fpr32(&fpu->fpr[idx], 0);
573 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
575 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
576 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
578 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
579 /* Can't access odd doubles in FR=0 mode */
580 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
582 v = get_fpr64(&fpu->fpr[idx], 0);
584 case KVM_REG_MIPS_FCR_IR:
585 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
587 v = boot_cpu_data.fpu_id;
589 case KVM_REG_MIPS_FCR_CSR:
590 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
595 /* MIPS SIMD Architecture (MSA) registers */
596 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
597 if (!kvm_mips_guest_has_msa(&vcpu->arch))
599 /* Can't access MSA registers in FR=0 mode */
600 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
602 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
603 #ifdef CONFIG_CPU_LITTLE_ENDIAN
604 /* least significant byte first */
605 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
606 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
608 /* most significant byte first */
609 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
610 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
613 case KVM_REG_MIPS_MSA_IR:
614 if (!kvm_mips_guest_has_msa(&vcpu->arch))
616 v = boot_cpu_data.msa_id;
618 case KVM_REG_MIPS_MSA_CSR:
619 if (!kvm_mips_guest_has_msa(&vcpu->arch))
624 /* Co-processor 0 registers */
625 case KVM_REG_MIPS_CP0_INDEX:
626 v = (long)kvm_read_c0_guest_index(cop0);
628 case KVM_REG_MIPS_CP0_CONTEXT:
629 v = (long)kvm_read_c0_guest_context(cop0);
631 case KVM_REG_MIPS_CP0_USERLOCAL:
632 v = (long)kvm_read_c0_guest_userlocal(cop0);
634 case KVM_REG_MIPS_CP0_PAGEMASK:
635 v = (long)kvm_read_c0_guest_pagemask(cop0);
637 case KVM_REG_MIPS_CP0_WIRED:
638 v = (long)kvm_read_c0_guest_wired(cop0);
640 case KVM_REG_MIPS_CP0_HWRENA:
641 v = (long)kvm_read_c0_guest_hwrena(cop0);
643 case KVM_REG_MIPS_CP0_BADVADDR:
644 v = (long)kvm_read_c0_guest_badvaddr(cop0);
646 case KVM_REG_MIPS_CP0_ENTRYHI:
647 v = (long)kvm_read_c0_guest_entryhi(cop0);
649 case KVM_REG_MIPS_CP0_COMPARE:
650 v = (long)kvm_read_c0_guest_compare(cop0);
652 case KVM_REG_MIPS_CP0_STATUS:
653 v = (long)kvm_read_c0_guest_status(cop0);
655 case KVM_REG_MIPS_CP0_CAUSE:
656 v = (long)kvm_read_c0_guest_cause(cop0);
658 case KVM_REG_MIPS_CP0_EPC:
659 v = (long)kvm_read_c0_guest_epc(cop0);
661 case KVM_REG_MIPS_CP0_PRID:
662 v = (long)kvm_read_c0_guest_prid(cop0);
664 case KVM_REG_MIPS_CP0_CONFIG:
665 v = (long)kvm_read_c0_guest_config(cop0);
667 case KVM_REG_MIPS_CP0_CONFIG1:
668 v = (long)kvm_read_c0_guest_config1(cop0);
670 case KVM_REG_MIPS_CP0_CONFIG2:
671 v = (long)kvm_read_c0_guest_config2(cop0);
673 case KVM_REG_MIPS_CP0_CONFIG3:
674 v = (long)kvm_read_c0_guest_config3(cop0);
676 case KVM_REG_MIPS_CP0_CONFIG4:
677 v = (long)kvm_read_c0_guest_config4(cop0);
679 case KVM_REG_MIPS_CP0_CONFIG5:
680 v = (long)kvm_read_c0_guest_config5(cop0);
682 case KVM_REG_MIPS_CP0_CONFIG7:
683 v = (long)kvm_read_c0_guest_config7(cop0);
685 case KVM_REG_MIPS_CP0_ERROREPC:
686 v = (long)kvm_read_c0_guest_errorepc(cop0);
688 /* registers to be handled specially */
689 case KVM_REG_MIPS_CP0_COUNT:
690 case KVM_REG_MIPS_COUNT_CTL:
691 case KVM_REG_MIPS_COUNT_RESUME:
692 case KVM_REG_MIPS_COUNT_HZ:
693 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
700 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
701 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
703 return put_user(v, uaddr64);
704 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
705 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
708 return put_user(v32, uaddr32);
709 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
710 void __user *uaddr = (void __user *)(long)reg->addr;
712 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
718 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
719 const struct kvm_one_reg *reg)
721 struct mips_coproc *cop0 = vcpu->arch.cop0;
722 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
727 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
728 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
730 if (get_user(v, uaddr64) != 0)
732 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
733 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
736 if (get_user(v32, uaddr32) != 0)
739 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
740 void __user *uaddr = (void __user *)(long)reg->addr;
742 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
748 /* General purpose registers */
749 case KVM_REG_MIPS_R0:
750 /* Silently ignore requests to set $0 */
752 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
753 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
755 case KVM_REG_MIPS_HI:
758 case KVM_REG_MIPS_LO:
761 case KVM_REG_MIPS_PC:
765 /* Floating point registers */
766 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
767 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
769 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
770 /* Odd singles in top of even double when FR=0 */
771 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
772 set_fpr32(&fpu->fpr[idx], 0, v);
774 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
776 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
777 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
779 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
780 /* Can't access odd doubles in FR=0 mode */
781 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
783 set_fpr64(&fpu->fpr[idx], 0, v);
785 case KVM_REG_MIPS_FCR_IR:
786 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
790 case KVM_REG_MIPS_FCR_CSR:
791 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
796 /* MIPS SIMD Architecture (MSA) registers */
797 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
798 if (!kvm_mips_guest_has_msa(&vcpu->arch))
800 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
801 #ifdef CONFIG_CPU_LITTLE_ENDIAN
802 /* least significant byte first */
803 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
804 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
806 /* most significant byte first */
807 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
808 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
811 case KVM_REG_MIPS_MSA_IR:
812 if (!kvm_mips_guest_has_msa(&vcpu->arch))
816 case KVM_REG_MIPS_MSA_CSR:
817 if (!kvm_mips_guest_has_msa(&vcpu->arch))
822 /* Co-processor 0 registers */
823 case KVM_REG_MIPS_CP0_INDEX:
824 kvm_write_c0_guest_index(cop0, v);
826 case KVM_REG_MIPS_CP0_CONTEXT:
827 kvm_write_c0_guest_context(cop0, v);
829 case KVM_REG_MIPS_CP0_USERLOCAL:
830 kvm_write_c0_guest_userlocal(cop0, v);
832 case KVM_REG_MIPS_CP0_PAGEMASK:
833 kvm_write_c0_guest_pagemask(cop0, v);
835 case KVM_REG_MIPS_CP0_WIRED:
836 kvm_write_c0_guest_wired(cop0, v);
838 case KVM_REG_MIPS_CP0_HWRENA:
839 kvm_write_c0_guest_hwrena(cop0, v);
841 case KVM_REG_MIPS_CP0_BADVADDR:
842 kvm_write_c0_guest_badvaddr(cop0, v);
844 case KVM_REG_MIPS_CP0_ENTRYHI:
845 kvm_write_c0_guest_entryhi(cop0, v);
847 case KVM_REG_MIPS_CP0_STATUS:
848 kvm_write_c0_guest_status(cop0, v);
850 case KVM_REG_MIPS_CP0_EPC:
851 kvm_write_c0_guest_epc(cop0, v);
853 case KVM_REG_MIPS_CP0_PRID:
854 kvm_write_c0_guest_prid(cop0, v);
856 case KVM_REG_MIPS_CP0_ERROREPC:
857 kvm_write_c0_guest_errorepc(cop0, v);
859 /* registers to be handled specially */
860 case KVM_REG_MIPS_CP0_COUNT:
861 case KVM_REG_MIPS_CP0_COMPARE:
862 case KVM_REG_MIPS_CP0_CAUSE:
863 case KVM_REG_MIPS_CP0_CONFIG:
864 case KVM_REG_MIPS_CP0_CONFIG1:
865 case KVM_REG_MIPS_CP0_CONFIG2:
866 case KVM_REG_MIPS_CP0_CONFIG3:
867 case KVM_REG_MIPS_CP0_CONFIG4:
868 case KVM_REG_MIPS_CP0_CONFIG5:
869 case KVM_REG_MIPS_COUNT_CTL:
870 case KVM_REG_MIPS_COUNT_RESUME:
871 case KVM_REG_MIPS_COUNT_HZ:
872 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
879 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
880 struct kvm_enable_cap *cap)
884 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
892 case KVM_CAP_MIPS_FPU:
893 vcpu->arch.fpu_enabled = true;
895 case KVM_CAP_MIPS_MSA:
896 vcpu->arch.msa_enabled = true;
906 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
909 struct kvm_vcpu *vcpu = filp->private_data;
910 void __user *argp = (void __user *)arg;
914 case KVM_SET_ONE_REG:
915 case KVM_GET_ONE_REG: {
916 struct kvm_one_reg reg;
918 if (copy_from_user(®, argp, sizeof(reg)))
920 if (ioctl == KVM_SET_ONE_REG)
921 return kvm_mips_set_reg(vcpu, ®);
923 return kvm_mips_get_reg(vcpu, ®);
925 case KVM_GET_REG_LIST: {
926 struct kvm_reg_list __user *user_list = argp;
927 u64 __user *reg_dest;
928 struct kvm_reg_list reg_list;
931 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
934 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
935 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
939 reg_dest = user_list->reg;
940 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
941 sizeof(kvm_mips_get_one_regs)))
946 /* Treat the NMI as a CPU reset */
947 r = kvm_mips_reset_vcpu(vcpu);
951 struct kvm_mips_interrupt irq;
954 if (copy_from_user(&irq, argp, sizeof(irq)))
957 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
960 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
963 case KVM_ENABLE_CAP: {
964 struct kvm_enable_cap cap;
967 if (copy_from_user(&cap, argp, sizeof(cap)))
969 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
980 /* Get (and clear) the dirty memory log for a memory slot. */
981 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
983 struct kvm_memslots *slots;
984 struct kvm_memory_slot *memslot;
985 unsigned long ga, ga_end;
990 mutex_lock(&kvm->slots_lock);
992 r = kvm_get_dirty_log(kvm, log, &is_dirty);
996 /* If nothing is dirty, don't bother messing with page tables. */
998 slots = kvm_memslots(kvm);
999 memslot = id_to_memslot(slots, log->slot);
1001 ga = memslot->base_gfn << PAGE_SHIFT;
1002 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1004 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1007 n = kvm_dirty_bitmap_bytes(memslot);
1008 memset(memslot->dirty_bitmap, 0, n);
1013 mutex_unlock(&kvm->slots_lock);
1018 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1030 int kvm_arch_init(void *opaque)
1032 if (kvm_mips_callbacks) {
1033 kvm_err("kvm: module already exists\n");
1037 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1040 void kvm_arch_exit(void)
1042 kvm_mips_callbacks = NULL;
1045 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1046 struct kvm_sregs *sregs)
1048 return -ENOIOCTLCMD;
1051 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1052 struct kvm_sregs *sregs)
1054 return -ENOIOCTLCMD;
1057 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1061 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1063 return -ENOIOCTLCMD;
1066 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1068 return -ENOIOCTLCMD;
1071 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1073 return VM_FAULT_SIGBUS;
1076 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1081 case KVM_CAP_ONE_REG:
1082 case KVM_CAP_ENABLE_CAP:
1085 case KVM_CAP_COALESCED_MMIO:
1086 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1088 case KVM_CAP_MIPS_FPU:
1089 /* We don't handle systems with inconsistent cpu_has_fpu */
1090 r = !!raw_cpu_has_fpu;
1092 case KVM_CAP_MIPS_MSA:
1094 * We don't support MSA vector partitioning yet:
1095 * 1) It would require explicit support which can't be tested
1096 * yet due to lack of support in current hardware.
1097 * 2) It extends the state that would need to be saved/restored
1098 * by e.g. QEMU for migration.
1100 * When vector partitioning hardware becomes available, support
1101 * could be added by requiring a flag when enabling
1102 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1103 * to save/restore the appropriate extra state.
1105 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1114 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1116 return kvm_mips_pending_timer(vcpu);
1119 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1122 struct mips_coproc *cop0;
1127 kvm_debug("VCPU Register Dump:\n");
1128 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1129 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1131 for (i = 0; i < 32; i += 4) {
1132 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1134 vcpu->arch.gprs[i + 1],
1135 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1137 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1138 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1140 cop0 = vcpu->arch.cop0;
1141 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1142 kvm_read_c0_guest_status(cop0),
1143 kvm_read_c0_guest_cause(cop0));
1145 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1150 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1154 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1155 vcpu->arch.gprs[i] = regs->gpr[i];
1156 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1157 vcpu->arch.hi = regs->hi;
1158 vcpu->arch.lo = regs->lo;
1159 vcpu->arch.pc = regs->pc;
1164 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1168 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1169 regs->gpr[i] = vcpu->arch.gprs[i];
1171 regs->hi = vcpu->arch.hi;
1172 regs->lo = vcpu->arch.lo;
1173 regs->pc = vcpu->arch.pc;
1178 static void kvm_mips_comparecount_func(unsigned long data)
1180 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1182 kvm_mips_callbacks->queue_timer_int(vcpu);
1184 vcpu->arch.wait = 0;
1185 if (swait_active(&vcpu->wq))
1186 swake_up(&vcpu->wq);
1189 /* low level hrtimer wake routine */
1190 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1192 struct kvm_vcpu *vcpu;
1194 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1195 kvm_mips_comparecount_func((unsigned long) vcpu);
1196 return kvm_mips_count_timeout(vcpu);
1199 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1201 kvm_mips_callbacks->vcpu_init(vcpu);
1202 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1204 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1208 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1209 struct kvm_translation *tr)
1214 /* Initial guest state */
1215 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1217 return kvm_mips_callbacks->vcpu_setup(vcpu);
1220 static void kvm_mips_set_c0_status(void)
1222 u32 status = read_c0_status();
1227 write_c0_status(status);
1232 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1234 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1236 u32 cause = vcpu->arch.host_cp0_cause;
1237 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1238 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1239 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1240 enum emulation_result er = EMULATE_DONE;
1241 int ret = RESUME_GUEST;
1243 /* re-enable HTW before enabling interrupts */
1246 /* Set a default exit reason */
1247 run->exit_reason = KVM_EXIT_UNKNOWN;
1248 run->ready_for_interrupt_injection = 1;
1251 * Set the appropriate status bits based on host CPU features,
1252 * before we hit the scheduler
1254 kvm_mips_set_c0_status();
1258 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1259 cause, opc, run, vcpu);
1260 trace_kvm_exit(vcpu, exccode);
1263 * Do a privilege check, if in UM most of these exit conditions end up
1264 * causing an exception to be delivered to the Guest Kernel
1266 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1267 if (er == EMULATE_PRIV_FAIL) {
1269 } else if (er == EMULATE_FAIL) {
1270 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1277 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1279 ++vcpu->stat.int_exits;
1288 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1290 ++vcpu->stat.cop_unusable_exits;
1291 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1292 /* XXXKYMA: Might need to return to user space */
1293 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1298 ++vcpu->stat.tlbmod_exits;
1299 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1303 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1304 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1307 ++vcpu->stat.tlbmiss_st_exits;
1308 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1312 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1313 cause, opc, badvaddr);
1315 ++vcpu->stat.tlbmiss_ld_exits;
1316 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1320 ++vcpu->stat.addrerr_st_exits;
1321 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1325 ++vcpu->stat.addrerr_ld_exits;
1326 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1330 ++vcpu->stat.syscall_exits;
1331 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1335 ++vcpu->stat.resvd_inst_exits;
1336 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1340 ++vcpu->stat.break_inst_exits;
1341 ret = kvm_mips_callbacks->handle_break(vcpu);
1345 ++vcpu->stat.trap_inst_exits;
1346 ret = kvm_mips_callbacks->handle_trap(vcpu);
1349 case EXCCODE_MSAFPE:
1350 ++vcpu->stat.msa_fpe_exits;
1351 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1355 ++vcpu->stat.fpe_exits;
1356 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1359 case EXCCODE_MSADIS:
1360 ++vcpu->stat.msa_disabled_exits;
1361 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1365 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1366 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1367 kvm_read_c0_guest_status(vcpu->arch.cop0));
1368 kvm_arch_vcpu_dump_regs(vcpu);
1369 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1376 local_irq_disable();
1378 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1379 kvm_mips_deliver_interrupts(vcpu, cause);
1381 if (!(ret & RESUME_HOST)) {
1382 /* Only check for signals if not already exiting to userspace */
1383 if (signal_pending(current)) {
1384 run->exit_reason = KVM_EXIT_INTR;
1385 ret = (-EINTR << 2) | RESUME_HOST;
1386 ++vcpu->stat.signal_exits;
1387 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1391 if (ret == RESUME_GUEST) {
1393 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1394 * is live), restore FCR31 / MSACSR.
1396 * This should be before returning to the guest exception
1397 * vector, as it may well cause an [MSA] FP exception if there
1398 * are pending exception bits unmasked. (see
1399 * kvm_mips_csr_die_notifier() for how that is handled).
1401 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1402 read_c0_status() & ST0_CU1)
1403 __kvm_restore_fcsr(&vcpu->arch);
1405 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1406 read_c0_config5() & MIPS_CONF5_MSAEN)
1407 __kvm_restore_msacsr(&vcpu->arch);
1410 /* Disable HTW before returning to guest or host */
1416 /* Enable FPU for guest and restore context */
1417 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1419 struct mips_coproc *cop0 = vcpu->arch.cop0;
1420 unsigned int sr, cfg5;
1424 sr = kvm_read_c0_guest_status(cop0);
1427 * If MSA state is already live, it is undefined how it interacts with
1428 * FR=0 FPU state, and we don't want to hit reserved instruction
1429 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1430 * play it safe and save it first.
1432 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1433 * get called when guest CU1 is set, however we can't trust the guest
1434 * not to clobber the status register directly via the commpage.
1436 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1437 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1441 * Enable FPU for guest
1442 * We set FR and FRE according to guest context
1444 change_c0_status(ST0_CU1 | ST0_FR, sr);
1446 cfg5 = kvm_read_c0_guest_config5(cop0);
1447 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1449 enable_fpu_hazard();
1451 /* If guest FPU state not active, restore it now */
1452 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1453 __kvm_restore_fpu(&vcpu->arch);
1454 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1455 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1457 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1463 #ifdef CONFIG_CPU_HAS_MSA
1464 /* Enable MSA for guest and restore context */
1465 void kvm_own_msa(struct kvm_vcpu *vcpu)
1467 struct mips_coproc *cop0 = vcpu->arch.cop0;
1468 unsigned int sr, cfg5;
1473 * Enable FPU if enabled in guest, since we're restoring FPU context
1474 * anyway. We set FR and FRE according to guest context.
1476 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1477 sr = kvm_read_c0_guest_status(cop0);
1480 * If FR=0 FPU state is already live, it is undefined how it
1481 * interacts with MSA state, so play it safe and save it first.
1483 if (!(sr & ST0_FR) &&
1484 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1485 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1488 change_c0_status(ST0_CU1 | ST0_FR, sr);
1489 if (sr & ST0_CU1 && cpu_has_fre) {
1490 cfg5 = kvm_read_c0_guest_config5(cop0);
1491 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1495 /* Enable MSA for guest */
1496 set_c0_config5(MIPS_CONF5_MSAEN);
1497 enable_fpu_hazard();
1499 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1500 case KVM_MIPS_AUX_FPU:
1502 * Guest FPU state already loaded, only restore upper MSA state
1504 __kvm_restore_msa_upper(&vcpu->arch);
1505 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1506 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1509 /* Neither FPU or MSA already active, restore full MSA state */
1510 __kvm_restore_msa(&vcpu->arch);
1511 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1512 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1513 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1514 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1515 KVM_TRACE_AUX_FPU_MSA);
1518 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1526 /* Drop FPU & MSA without saving it */
1527 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1530 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1532 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1533 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1535 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1536 clear_c0_status(ST0_CU1 | ST0_FR);
1537 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1538 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1543 /* Save and disable FPU & MSA */
1544 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1547 * FPU & MSA get disabled in root context (hardware) when it is disabled
1548 * in guest context (software), but the register state in the hardware
1549 * may still be in use. This is why we explicitly re-enable the hardware
1554 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1555 set_c0_config5(MIPS_CONF5_MSAEN);
1556 enable_fpu_hazard();
1558 __kvm_save_msa(&vcpu->arch);
1559 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1561 /* Disable MSA & FPU */
1563 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1564 clear_c0_status(ST0_CU1 | ST0_FR);
1565 disable_fpu_hazard();
1567 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1568 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1569 set_c0_status(ST0_CU1);
1570 enable_fpu_hazard();
1572 __kvm_save_fpu(&vcpu->arch);
1573 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1574 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1577 clear_c0_status(ST0_CU1 | ST0_FR);
1578 disable_fpu_hazard();
1584 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1585 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1586 * exception if cause bits are set in the value being written.
1588 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1589 unsigned long cmd, void *ptr)
1591 struct die_args *args = (struct die_args *)ptr;
1592 struct pt_regs *regs = args->regs;
1595 /* Only interested in FPE and MSAFPE */
1596 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1599 /* Return immediately if guest context isn't active */
1600 if (!(current->flags & PF_VCPU))
1603 /* Should never get here from user mode */
1604 BUG_ON(user_mode(regs));
1606 pc = instruction_pointer(regs);
1609 /* match 2nd instruction in __kvm_restore_fcsr */
1610 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1614 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1616 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1617 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1622 /* Move PC forward a little and continue executing */
1623 instruction_pointer(regs) += 4;
1628 static struct notifier_block kvm_mips_csr_die_notifier = {
1629 .notifier_call = kvm_mips_csr_die_notify,
1632 static int __init kvm_mips_init(void)
1636 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1641 register_die_notifier(&kvm_mips_csr_die_notifier);
1646 static void __exit kvm_mips_exit(void)
1650 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1653 module_init(kvm_mips_init);
1654 module_exit(kvm_mips_exit);
1656 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);