arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/kdebug.h>
  15 #include <linux/module.h>
  16 #include <linux/vmalloc.h>
  17 #include <linux/fs.h>
  18 #include <linux/bootmem.h>
  19 #include <asm/fpu.h>
  20 #include <asm/page.h>
  21 #include <asm/cacheflush.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/pgtable.h>
  24
  25 #include <linux/kvm_host.h>
  26
  27 #include "interrupt.h"
  28 #include "commpage.h"
  29
  30 #define CREATE_TRACE_POINTS
  31 #include "trace.h"
  32
  33 #ifndef VECTORSPACING
  34 #define VECTORSPACING 0x100     /* for EI/VI mode */
  35 #endif
  36
  37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  38 struct kvm_stats_debugfs_item debugfs_entries[] = {
  39         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  40         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  41         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  42         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  43         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  44         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  45         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  46         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  47         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  48         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  49         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  50         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  51         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  52         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  53         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  54         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  55         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  56         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  57         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  58         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  59         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  60         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  61         {NULL}
  62 };
  63
  64 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
  65 {
  66         int i;
  67
  68         for_each_possible_cpu(i) {
  69                 vcpu->arch.guest_kernel_asid[i] = 0;
  70                 vcpu->arch.guest_user_asid[i] = 0;
  71         }
  72
  73         return 0;
  74 }
  75
  76 /*
  77  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  78  * Config7, so we are "runnable" if interrupts are pending
  79  */
  80 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  81 {
  82         return !!(vcpu->arch.pending_exceptions);
  83 }
  84
  85 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  86 {
  87         return 1;
  88 }
  89
  90 int kvm_arch_hardware_enable(void)
  91 {
  92         return 0;
  93 }
  94
  95 int kvm_arch_hardware_setup(void)
  96 {
  97         return 0;
  98 }
  99
 100 void kvm_arch_check_processor_compat(void *rtn)
 101 {
 102         *(int *)rtn = 0;
 103 }
 104
 105 static void kvm_mips_init_tlbs(struct kvm *kvm)
 106 {
 107         unsigned long wired;
 108
 109         /*
 110          * Add a wired entry to the TLB, it is used to map the commpage to
 111          * the Guest kernel
 112          */
 113         wired = read_c0_wired();
 114         write_c0_wired(wired + 1);
 115         mtc0_tlbw_hazard();
 116         kvm->arch.commpage_tlb = wired;
 117
 118         kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
 119                   kvm->arch.commpage_tlb);
 120 }
 121
 122 static void kvm_mips_init_vm_percpu(void *arg)
 123 {
 124         struct kvm *kvm = (struct kvm *)arg;
 125
 126         kvm_mips_init_tlbs(kvm);
 127         kvm_mips_callbacks->vm_init(kvm);
 128
 129 }
 130
 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 132 {
 133         if (atomic_inc_return(&kvm_mips_instance) == 1) {
 134                 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
 135                           __func__);
 136                 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
 137         }
 138
 139         return 0;
 140 }
 141
 142 void kvm_mips_free_vcpus(struct kvm *kvm)
 143 {
 144         unsigned int i;
 145         struct kvm_vcpu *vcpu;
 146
 147         /* Put the pages we reserved for the guest pmap */
 148         for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
 149                 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
 150                         kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
 151         }
 152         kfree(kvm->arch.guest_pmap);
 153
 154         kvm_for_each_vcpu(i, vcpu, kvm) {
 155                 kvm_arch_vcpu_free(vcpu);
 156         }
 157
 158         mutex_lock(&kvm->lock);
 159
 160         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 161                 kvm->vcpus[i] = NULL;
 162
 163         atomic_set(&kvm->online_vcpus, 0);
 164
 165         mutex_unlock(&kvm->lock);
 166 }
 167
 168 static void kvm_mips_uninit_tlbs(void *arg)
 169 {
 170         /* Restore wired count */
 171         write_c0_wired(0);
 172         mtc0_tlbw_hazard();
 173         /* Clear out all the TLBs */
 174         kvm_local_flush_tlb_all();
 175 }
 176
 177 void kvm_arch_destroy_vm(struct kvm *kvm)
 178 {
 179         kvm_mips_free_vcpus(kvm);
 180
 181         /* If this is the last instance, restore wired count */
 182         if (atomic_dec_return(&kvm_mips_instance) == 0) {
 183                 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
 184                           __func__);
 185                 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
 186         }
 187 }
 188
 189 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 190                         unsigned long arg)
 191 {
 192         return -ENOIOCTLCMD;
 193 }
 194
 195 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 196                             unsigned long npages)
 197 {
 198         return 0;
 199 }
 200
 201 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 202                                    struct kvm_memory_slot *memslot,
 203                                    const struct kvm_userspace_memory_region *mem,
 204                                    enum kvm_mr_change change)
 205 {
 206         return 0;
 207 }
 208
 209 void kvm_arch_commit_memory_region(struct kvm *kvm,
 210                                    const struct kvm_userspace_memory_region *mem,
 211                                    const struct kvm_memory_slot *old,
 212                                    const struct kvm_memory_slot *new,
 213                                    enum kvm_mr_change change)
 214 {
 215         unsigned long npages = 0;
 216         int i;
 217
 218         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 219                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 220                   mem->memory_size, mem->userspace_addr);
 221
 222         /* Setup Guest PMAP table */
 223         if (!kvm->arch.guest_pmap) {
 224                 if (mem->slot == 0)
 225                         npages = mem->memory_size >> PAGE_SHIFT;
 226
 227                 if (npages) {
 228                         kvm->arch.guest_pmap_npages = npages;
 229                         kvm->arch.guest_pmap =
 230                             kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
 231
 232                         if (!kvm->arch.guest_pmap) {
 233                                 kvm_err("Failed to allocate guest PMAP\n");
 234                                 return;
 235                         }
 236
 237                         kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
 238                                   npages, kvm->arch.guest_pmap);
 239
 240                         /* Now setup the page table */
 241                         for (i = 0; i < npages; i++)
 242                                 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
 243                 }
 244         }
 245 }
 246
 247 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 248 {
 249         int err, size, offset;
 250         void *gebase;
 251         int i;
 252
 253         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 254
 255         if (!vcpu) {
 256                 err = -ENOMEM;
 257                 goto out;
 258         }
 259
 260         err = kvm_vcpu_init(vcpu, kvm, id);
 261
 262         if (err)
 263                 goto out_free_cpu;
 264
 265         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 266
 267         /*
 268          * Allocate space for host mode exception handlers that handle
 269          * guest mode exits
 270          */
 271         if (cpu_has_veic || cpu_has_vint)
 272                 size = 0x200 + VECTORSPACING * 64;
 273         else
 274                 size = 0x4000;
 275
 276         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 277
 278         if (!gebase) {
 279                 err = -ENOMEM;
 280                 goto out_uninit_cpu;
 281         }
 282         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 283                   ALIGN(size, PAGE_SIZE), gebase);
 284
 285         /* Save new ebase */
 286         vcpu->arch.guest_ebase = gebase;
 287
 288         /* Copy L1 Guest Exception handler to correct offset */
 289
 290         /* TLB Refill, EXL = 0 */
 291         memcpy(gebase, mips32_exception,
 292                mips32_exceptionEnd - mips32_exception);
 293
 294         /* General Exception Entry point */
 295         memcpy(gebase + 0x180, mips32_exception,
 296                mips32_exceptionEnd - mips32_exception);
 297
 298         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 299         for (i = 0; i < 8; i++) {
 300                 kvm_debug("L1 Vectored handler @ %p\n",
 301                           gebase + 0x200 + (i * VECTORSPACING));
 302                 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
 303                        mips32_exceptionEnd - mips32_exception);
 304         }
 305
 306         /* General handler, relocate to unmapped space for sanity's sake */
 307         offset = 0x2000;
 308         kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
 309                   gebase + offset,
 310                   mips32_GuestExceptionEnd - mips32_GuestException);
 311
 312         memcpy(gebase + offset, mips32_GuestException,
 313                mips32_GuestExceptionEnd - mips32_GuestException);
 314
 315 #ifdef MODULE
 316         offset += mips32_GuestExceptionEnd - mips32_GuestException;
 317         memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
 318                __kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
 319         vcpu->arch.vcpu_run = gebase + offset;
 320 #else
 321         vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
 322 #endif
 323
 324         /* Invalidate the icache for these ranges */
 325         local_flush_icache_range((unsigned long)gebase,
 326                                 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 327
 328         /*
 329          * Allocate comm page for guest kernel, a TLB will be reserved for
 330          * mapping GVA @ 0xFFFF8000 to this page
 331          */
 332         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 333
 334         if (!vcpu->arch.kseg0_commpage) {
 335                 err = -ENOMEM;
 336                 goto out_free_gebase;
 337         }
 338
 339         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 340         kvm_mips_commpage_init(vcpu);
 341
 342         /* Init */
 343         vcpu->arch.last_sched_cpu = -1;
 344
 345         /* Start off the timer */
 346         kvm_mips_init_count(vcpu);
 347
 348         return vcpu;
 349
 350 out_free_gebase:
 351         kfree(gebase);
 352
 353 out_uninit_cpu:
 354         kvm_vcpu_uninit(vcpu);
 355
 356 out_free_cpu:
 357         kfree(vcpu);
 358
 359 out:
 360         return ERR_PTR(err);
 361 }
 362
 363 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 364 {
 365         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 366
 367         kvm_vcpu_uninit(vcpu);
 368
 369         kvm_mips_dump_stats(vcpu);
 370
 371         kfree(vcpu->arch.guest_ebase);
 372         kfree(vcpu->arch.kseg0_commpage);
 373         kfree(vcpu);
 374 }
 375
 376 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 377 {
 378         kvm_arch_vcpu_free(vcpu);
 379 }
 380
 381 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 382                                         struct kvm_guest_debug *dbg)
 383 {
 384         return -ENOIOCTLCMD;
 385 }
 386
 387 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 388 {
 389         int r = 0;
 390         sigset_t sigsaved;
 391
 392         if (vcpu->sigset_active)
 393                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 394
 395         if (vcpu->mmio_needed) {
 396                 if (!vcpu->mmio_is_write)
 397                         kvm_mips_complete_mmio_load(vcpu, run);
 398                 vcpu->mmio_needed = 0;
 399         }
 400
 401         lose_fpu(1);
 402
 403         local_irq_disable();
 404         /* Check if we have any exceptions/interrupts pending */
 405         kvm_mips_deliver_interrupts(vcpu,
 406                                     kvm_read_c0_guest_cause(vcpu->arch.cop0));
 407
 408         __kvm_guest_enter();
 409
 410         /* Disable hardware page table walking while in guest */
 411         htw_stop();
 412
 413         r = vcpu->arch.vcpu_run(run, vcpu);
 414
 415         /* Re-enable HTW before enabling interrupts */
 416         htw_start();
 417
 418         __kvm_guest_exit();
 419         local_irq_enable();
 420
 421         if (vcpu->sigset_active)
 422                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 423
 424         return r;
 425 }
 426
 427 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 428                              struct kvm_mips_interrupt *irq)
 429 {
 430         int intr = (int)irq->irq;
 431         struct kvm_vcpu *dvcpu = NULL;
 432
 433         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 434                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 435                           (int)intr);
 436
 437         if (irq->cpu == -1)
 438                 dvcpu = vcpu;
 439         else
 440                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 441
 442         if (intr == 2 || intr == 3 || intr == 4) {
 443                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 444
 445         } else if (intr == -2 || intr == -3 || intr == -4) {
 446                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 447         } else {
 448                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 449                         irq->cpu, irq->irq);
 450                 return -EINVAL;
 451         }
 452
 453         dvcpu->arch.wait = 0;
 454
 455         if (swait_active(&dvcpu->wq))
 456                 swake_up(&dvcpu->wq);
 457
 458         return 0;
 459 }
 460
 461 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 462                                     struct kvm_mp_state *mp_state)
 463 {
 464         return -ENOIOCTLCMD;
 465 }
 466
 467 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 468                                     struct kvm_mp_state *mp_state)
 469 {
 470         return -ENOIOCTLCMD;
 471 }
 472
 473 static u64 kvm_mips_get_one_regs[] = {
 474         KVM_REG_MIPS_R0,
 475         KVM_REG_MIPS_R1,
 476         KVM_REG_MIPS_R2,
 477         KVM_REG_MIPS_R3,
 478         KVM_REG_MIPS_R4,
 479         KVM_REG_MIPS_R5,
 480         KVM_REG_MIPS_R6,
 481         KVM_REG_MIPS_R7,
 482         KVM_REG_MIPS_R8,
 483         KVM_REG_MIPS_R9,
 484         KVM_REG_MIPS_R10,
 485         KVM_REG_MIPS_R11,
 486         KVM_REG_MIPS_R12,
 487         KVM_REG_MIPS_R13,
 488         KVM_REG_MIPS_R14,
 489         KVM_REG_MIPS_R15,
 490         KVM_REG_MIPS_R16,
 491         KVM_REG_MIPS_R17,
 492         KVM_REG_MIPS_R18,
 493         KVM_REG_MIPS_R19,
 494         KVM_REG_MIPS_R20,
 495         KVM_REG_MIPS_R21,
 496         KVM_REG_MIPS_R22,
 497         KVM_REG_MIPS_R23,
 498         KVM_REG_MIPS_R24,
 499         KVM_REG_MIPS_R25,
 500         KVM_REG_MIPS_R26,
 501         KVM_REG_MIPS_R27,
 502         KVM_REG_MIPS_R28,
 503         KVM_REG_MIPS_R29,
 504         KVM_REG_MIPS_R30,
 505         KVM_REG_MIPS_R31,
 506
 507         KVM_REG_MIPS_HI,
 508         KVM_REG_MIPS_LO,
 509         KVM_REG_MIPS_PC,
 510
 511         KVM_REG_MIPS_CP0_INDEX,
 512         KVM_REG_MIPS_CP0_CONTEXT,
 513         KVM_REG_MIPS_CP0_USERLOCAL,
 514         KVM_REG_MIPS_CP0_PAGEMASK,
 515         KVM_REG_MIPS_CP0_WIRED,
 516         KVM_REG_MIPS_CP0_HWRENA,
 517         KVM_REG_MIPS_CP0_BADVADDR,
 518         KVM_REG_MIPS_CP0_COUNT,
 519         KVM_REG_MIPS_CP0_ENTRYHI,
 520         KVM_REG_MIPS_CP0_COMPARE,
 521         KVM_REG_MIPS_CP0_STATUS,
 522         KVM_REG_MIPS_CP0_CAUSE,
 523         KVM_REG_MIPS_CP0_EPC,
 524         KVM_REG_MIPS_CP0_PRID,
 525         KVM_REG_MIPS_CP0_CONFIG,
 526         KVM_REG_MIPS_CP0_CONFIG1,
 527         KVM_REG_MIPS_CP0_CONFIG2,
 528         KVM_REG_MIPS_CP0_CONFIG3,
 529         KVM_REG_MIPS_CP0_CONFIG4,
 530         KVM_REG_MIPS_CP0_CONFIG5,
 531         KVM_REG_MIPS_CP0_CONFIG7,
 532         KVM_REG_MIPS_CP0_ERROREPC,
 533
 534         KVM_REG_MIPS_COUNT_CTL,
 535         KVM_REG_MIPS_COUNT_RESUME,
 536         KVM_REG_MIPS_COUNT_HZ,
 537 };
 538
 539 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 540                             const struct kvm_one_reg *reg)
 541 {
 542         struct mips_coproc *cop0 = vcpu->arch.cop0;
 543         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 544         int ret;
 545         s64 v;
 546         s64 vs[2];
 547         unsigned int idx;
 548
 549         switch (reg->id) {
 550         /* General purpose registers */
 551         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 552                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 553                 break;
 554         case KVM_REG_MIPS_HI:
 555                 v = (long)vcpu->arch.hi;
 556                 break;
 557         case KVM_REG_MIPS_LO:
 558                 v = (long)vcpu->arch.lo;
 559                 break;
 560         case KVM_REG_MIPS_PC:
 561                 v = (long)vcpu->arch.pc;
 562                 break;
 563
 564         /* Floating point registers */
 565         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 566                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 567                         return -EINVAL;
 568                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 569                 /* Odd singles in top of even double when FR=0 */
 570                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 571                         v = get_fpr32(&fpu->fpr[idx], 0);
 572                 else
 573                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 574                 break;
 575         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 576                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 577                         return -EINVAL;
 578                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 579                 /* Can't access odd doubles in FR=0 mode */
 580                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 581                         return -EINVAL;
 582                 v = get_fpr64(&fpu->fpr[idx], 0);
 583                 break;
 584         case KVM_REG_MIPS_FCR_IR:
 585                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 586                         return -EINVAL;
 587                 v = boot_cpu_data.fpu_id;
 588                 break;
 589         case KVM_REG_MIPS_FCR_CSR:
 590                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 591                         return -EINVAL;
 592                 v = fpu->fcr31;
 593                 break;
 594
 595         /* MIPS SIMD Architecture (MSA) registers */
 596         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 597                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 598                         return -EINVAL;
 599                 /* Can't access MSA registers in FR=0 mode */
 600                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 601                         return -EINVAL;
 602                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 603 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 604                 /* least significant byte first */
 605                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 606                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 607 #else
 608                 /* most significant byte first */
 609                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 610                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 611 #endif
 612                 break;
 613         case KVM_REG_MIPS_MSA_IR:
 614                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 615                         return -EINVAL;
 616                 v = boot_cpu_data.msa_id;
 617                 break;
 618         case KVM_REG_MIPS_MSA_CSR:
 619                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 620                         return -EINVAL;
 621                 v = fpu->msacsr;
 622                 break;
 623
 624         /* Co-processor 0 registers */
 625         case KVM_REG_MIPS_CP0_INDEX:
 626                 v = (long)kvm_read_c0_guest_index(cop0);
 627                 break;
 628         case KVM_REG_MIPS_CP0_CONTEXT:
 629                 v = (long)kvm_read_c0_guest_context(cop0);
 630                 break;
 631         case KVM_REG_MIPS_CP0_USERLOCAL:
 632                 v = (long)kvm_read_c0_guest_userlocal(cop0);
 633                 break;
 634         case KVM_REG_MIPS_CP0_PAGEMASK:
 635                 v = (long)kvm_read_c0_guest_pagemask(cop0);
 636                 break;
 637         case KVM_REG_MIPS_CP0_WIRED:
 638                 v = (long)kvm_read_c0_guest_wired(cop0);
 639                 break;
 640         case KVM_REG_MIPS_CP0_HWRENA:
 641                 v = (long)kvm_read_c0_guest_hwrena(cop0);
 642                 break;
 643         case KVM_REG_MIPS_CP0_BADVADDR:
 644                 v = (long)kvm_read_c0_guest_badvaddr(cop0);
 645                 break;
 646         case KVM_REG_MIPS_CP0_ENTRYHI:
 647                 v = (long)kvm_read_c0_guest_entryhi(cop0);
 648                 break;
 649         case KVM_REG_MIPS_CP0_COMPARE:
 650                 v = (long)kvm_read_c0_guest_compare(cop0);
 651                 break;
 652         case KVM_REG_MIPS_CP0_STATUS:
 653                 v = (long)kvm_read_c0_guest_status(cop0);
 654                 break;
 655         case KVM_REG_MIPS_CP0_CAUSE:
 656                 v = (long)kvm_read_c0_guest_cause(cop0);
 657                 break;
 658         case KVM_REG_MIPS_CP0_EPC:
 659                 v = (long)kvm_read_c0_guest_epc(cop0);
 660                 break;
 661         case KVM_REG_MIPS_CP0_PRID:
 662                 v = (long)kvm_read_c0_guest_prid(cop0);
 663                 break;
 664         case KVM_REG_MIPS_CP0_CONFIG:
 665                 v = (long)kvm_read_c0_guest_config(cop0);
 666                 break;
 667         case KVM_REG_MIPS_CP0_CONFIG1:
 668                 v = (long)kvm_read_c0_guest_config1(cop0);
 669                 break;
 670         case KVM_REG_MIPS_CP0_CONFIG2:
 671                 v = (long)kvm_read_c0_guest_config2(cop0);
 672                 break;
 673         case KVM_REG_MIPS_CP0_CONFIG3:
 674                 v = (long)kvm_read_c0_guest_config3(cop0);
 675                 break;
 676         case KVM_REG_MIPS_CP0_CONFIG4:
 677                 v = (long)kvm_read_c0_guest_config4(cop0);
 678                 break;
 679         case KVM_REG_MIPS_CP0_CONFIG5:
 680                 v = (long)kvm_read_c0_guest_config5(cop0);
 681                 break;
 682         case KVM_REG_MIPS_CP0_CONFIG7:
 683                 v = (long)kvm_read_c0_guest_config7(cop0);
 684                 break;
 685         case KVM_REG_MIPS_CP0_ERROREPC:
 686                 v = (long)kvm_read_c0_guest_errorepc(cop0);
 687                 break;
 688         /* registers to be handled specially */
 689         case KVM_REG_MIPS_CP0_COUNT:
 690         case KVM_REG_MIPS_COUNT_CTL:
 691         case KVM_REG_MIPS_COUNT_RESUME:
 692         case KVM_REG_MIPS_COUNT_HZ:
 693                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 694                 if (ret)
 695                         return ret;
 696                 break;
 697         default:
 698                 return -EINVAL;
 699         }
 700         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 701                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 702
 703                 return put_user(v, uaddr64);
 704         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 705                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 706                 u32 v32 = (u32)v;
 707
 708                 return put_user(v32, uaddr32);
 709         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 710                 void __user *uaddr = (void __user *)(long)reg->addr;
 711
 712                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 713         } else {
 714                 return -EINVAL;
 715         }
 716 }
 717
 718 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 719                             const struct kvm_one_reg *reg)
 720 {
 721         struct mips_coproc *cop0 = vcpu->arch.cop0;
 722         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 723         s64 v;
 724         s64 vs[2];
 725         unsigned int idx;
 726
 727         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 728                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 729
 730                 if (get_user(v, uaddr64) != 0)
 731                         return -EFAULT;
 732         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 733                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 734                 s32 v32;
 735
 736                 if (get_user(v32, uaddr32) != 0)
 737                         return -EFAULT;
 738                 v = (s64)v32;
 739         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 740                 void __user *uaddr = (void __user *)(long)reg->addr;
 741
 742                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 743         } else {
 744                 return -EINVAL;
 745         }
 746
 747         switch (reg->id) {
 748         /* General purpose registers */
 749         case KVM_REG_MIPS_R0:
 750                 /* Silently ignore requests to set $0 */
 751                 break;
 752         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 753                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 754                 break;
 755         case KVM_REG_MIPS_HI:
 756                 vcpu->arch.hi = v;
 757                 break;
 758         case KVM_REG_MIPS_LO:
 759                 vcpu->arch.lo = v;
 760                 break;
 761         case KVM_REG_MIPS_PC:
 762                 vcpu->arch.pc = v;
 763                 break;
 764
 765         /* Floating point registers */
 766         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 767                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 768                         return -EINVAL;
 769                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 770                 /* Odd singles in top of even double when FR=0 */
 771                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 772                         set_fpr32(&fpu->fpr[idx], 0, v);
 773                 else
 774                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 775                 break;
 776         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 777                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 778                         return -EINVAL;
 779                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 780                 /* Can't access odd doubles in FR=0 mode */
 781                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 782                         return -EINVAL;
 783                 set_fpr64(&fpu->fpr[idx], 0, v);
 784                 break;
 785         case KVM_REG_MIPS_FCR_IR:
 786                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 787                         return -EINVAL;
 788                 /* Read-only */
 789                 break;
 790         case KVM_REG_MIPS_FCR_CSR:
 791                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 792                         return -EINVAL;
 793                 fpu->fcr31 = v;
 794                 break;
 795
 796         /* MIPS SIMD Architecture (MSA) registers */
 797         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 798                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 799                         return -EINVAL;
 800                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 801 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 802                 /* least significant byte first */
 803                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 804                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 805 #else
 806                 /* most significant byte first */
 807                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 808                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 809 #endif
 810                 break;
 811         case KVM_REG_MIPS_MSA_IR:
 812                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 813                         return -EINVAL;
 814                 /* Read-only */
 815                 break;
 816         case KVM_REG_MIPS_MSA_CSR:
 817                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 818                         return -EINVAL;
 819                 fpu->msacsr = v;
 820                 break;
 821
 822         /* Co-processor 0 registers */
 823         case KVM_REG_MIPS_CP0_INDEX:
 824                 kvm_write_c0_guest_index(cop0, v);
 825                 break;
 826         case KVM_REG_MIPS_CP0_CONTEXT:
 827                 kvm_write_c0_guest_context(cop0, v);
 828                 break;
 829         case KVM_REG_MIPS_CP0_USERLOCAL:
 830                 kvm_write_c0_guest_userlocal(cop0, v);
 831                 break;
 832         case KVM_REG_MIPS_CP0_PAGEMASK:
 833                 kvm_write_c0_guest_pagemask(cop0, v);
 834                 break;
 835         case KVM_REG_MIPS_CP0_WIRED:
 836                 kvm_write_c0_guest_wired(cop0, v);
 837                 break;
 838         case KVM_REG_MIPS_CP0_HWRENA:
 839                 kvm_write_c0_guest_hwrena(cop0, v);
 840                 break;
 841         case KVM_REG_MIPS_CP0_BADVADDR:
 842                 kvm_write_c0_guest_badvaddr(cop0, v);
 843                 break;
 844         case KVM_REG_MIPS_CP0_ENTRYHI:
 845                 kvm_write_c0_guest_entryhi(cop0, v);
 846                 break;
 847         case KVM_REG_MIPS_CP0_STATUS:
 848                 kvm_write_c0_guest_status(cop0, v);
 849                 break;
 850         case KVM_REG_MIPS_CP0_EPC:
 851                 kvm_write_c0_guest_epc(cop0, v);
 852                 break;
 853         case KVM_REG_MIPS_CP0_PRID:
 854                 kvm_write_c0_guest_prid(cop0, v);
 855                 break;
 856         case KVM_REG_MIPS_CP0_ERROREPC:
 857                 kvm_write_c0_guest_errorepc(cop0, v);
 858                 break;
 859         /* registers to be handled specially */
 860         case KVM_REG_MIPS_CP0_COUNT:
 861         case KVM_REG_MIPS_CP0_COMPARE:
 862         case KVM_REG_MIPS_CP0_CAUSE:
 863         case KVM_REG_MIPS_CP0_CONFIG:
 864         case KVM_REG_MIPS_CP0_CONFIG1:
 865         case KVM_REG_MIPS_CP0_CONFIG2:
 866         case KVM_REG_MIPS_CP0_CONFIG3:
 867         case KVM_REG_MIPS_CP0_CONFIG4:
 868         case KVM_REG_MIPS_CP0_CONFIG5:
 869         case KVM_REG_MIPS_COUNT_CTL:
 870         case KVM_REG_MIPS_COUNT_RESUME:
 871         case KVM_REG_MIPS_COUNT_HZ:
 872                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 873         default:
 874                 return -EINVAL;
 875         }
 876         return 0;
 877 }
 878
 879 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 880                                      struct kvm_enable_cap *cap)
 881 {
 882         int r = 0;
 883
 884         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 885                 return -EINVAL;
 886         if (cap->flags)
 887                 return -EINVAL;
 888         if (cap->args[0])
 889                 return -EINVAL;
 890
 891         switch (cap->cap) {
 892         case KVM_CAP_MIPS_FPU:
 893                 vcpu->arch.fpu_enabled = true;
 894                 break;
 895         case KVM_CAP_MIPS_MSA:
 896                 vcpu->arch.msa_enabled = true;
 897                 break;
 898         default:
 899                 r = -EINVAL;
 900                 break;
 901         }
 902
 903         return r;
 904 }
 905
 906 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 907                          unsigned long arg)
 908 {
 909         struct kvm_vcpu *vcpu = filp->private_data;
 910         void __user *argp = (void __user *)arg;
 911         long r;
 912
 913         switch (ioctl) {
 914         case KVM_SET_ONE_REG:
 915         case KVM_GET_ONE_REG: {
 916                 struct kvm_one_reg reg;
 917
 918                 if (copy_from_user(&reg, argp, sizeof(reg)))
 919                         return -EFAULT;
 920                 if (ioctl == KVM_SET_ONE_REG)
 921                         return kvm_mips_set_reg(vcpu, &reg);
 922                 else
 923                         return kvm_mips_get_reg(vcpu, &reg);
 924         }
 925         case KVM_GET_REG_LIST: {
 926                 struct kvm_reg_list __user *user_list = argp;
 927                 u64 __user *reg_dest;
 928                 struct kvm_reg_list reg_list;
 929                 unsigned n;
 930
 931                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 932                         return -EFAULT;
 933                 n = reg_list.n;
 934                 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
 935                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 936                         return -EFAULT;
 937                 if (n < reg_list.n)
 938                         return -E2BIG;
 939                 reg_dest = user_list->reg;
 940                 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
 941                                  sizeof(kvm_mips_get_one_regs)))
 942                         return -EFAULT;
 943                 return 0;
 944         }
 945         case KVM_NMI:
 946                 /* Treat the NMI as a CPU reset */
 947                 r = kvm_mips_reset_vcpu(vcpu);
 948                 break;
 949         case KVM_INTERRUPT:
 950                 {
 951                         struct kvm_mips_interrupt irq;
 952
 953                         r = -EFAULT;
 954                         if (copy_from_user(&irq, argp, sizeof(irq)))
 955                                 goto out;
 956
 957                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 958                                   irq.irq);
 959
 960                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 961                         break;
 962                 }
 963         case KVM_ENABLE_CAP: {
 964                 struct kvm_enable_cap cap;
 965
 966                 r = -EFAULT;
 967                 if (copy_from_user(&cap, argp, sizeof(cap)))
 968                         goto out;
 969                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 970                 break;
 971         }
 972         default:
 973                 r = -ENOIOCTLCMD;
 974         }
 975
 976 out:
 977         return r;
 978 }
 979
 980 /* Get (and clear) the dirty memory log for a memory slot. */
 981 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 982 {
 983         struct kvm_memslots *slots;
 984         struct kvm_memory_slot *memslot;
 985         unsigned long ga, ga_end;
 986         int is_dirty = 0;
 987         int r;
 988         unsigned long n;
 989
 990         mutex_lock(&kvm->slots_lock);
 991
 992         r = kvm_get_dirty_log(kvm, log, &is_dirty);
 993         if (r)
 994                 goto out;
 995
 996         /* If nothing is dirty, don't bother messing with page tables. */
 997         if (is_dirty) {
 998                 slots = kvm_memslots(kvm);
 999                 memslot = id_to_memslot(slots, log->slot);
1000
1001                 ga = memslot->base_gfn << PAGE_SHIFT;
1002                 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1003
1004                 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1005                          ga_end);
1006
1007                 n = kvm_dirty_bitmap_bytes(memslot);
1008                 memset(memslot->dirty_bitmap, 0, n);
1009         }
1010
1011         r = 0;
1012 out:
1013         mutex_unlock(&kvm->slots_lock);
1014         return r;
1015
1016 }
1017
1018 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1019 {
1020         long r;
1021
1022         switch (ioctl) {
1023         default:
1024                 r = -ENOIOCTLCMD;
1025         }
1026
1027         return r;
1028 }
1029
1030 int kvm_arch_init(void *opaque)
1031 {
1032         if (kvm_mips_callbacks) {
1033                 kvm_err("kvm: module already exists\n");
1034                 return -EEXIST;
1035         }
1036
1037         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1038 }
1039
1040 void kvm_arch_exit(void)
1041 {
1042         kvm_mips_callbacks = NULL;
1043 }
1044
1045 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1046                                   struct kvm_sregs *sregs)
1047 {
1048         return -ENOIOCTLCMD;
1049 }
1050
1051 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1052                                   struct kvm_sregs *sregs)
1053 {
1054         return -ENOIOCTLCMD;
1055 }
1056
1057 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1058 {
1059 }
1060
1061 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1062 {
1063         return -ENOIOCTLCMD;
1064 }
1065
1066 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1067 {
1068         return -ENOIOCTLCMD;
1069 }
1070
1071 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1072 {
1073         return VM_FAULT_SIGBUS;
1074 }
1075
1076 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1077 {
1078         int r;
1079
1080         switch (ext) {
1081         case KVM_CAP_ONE_REG:
1082         case KVM_CAP_ENABLE_CAP:
1083                 r = 1;
1084                 break;
1085         case KVM_CAP_COALESCED_MMIO:
1086                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1087                 break;
1088         case KVM_CAP_MIPS_FPU:
1089                 /* We don't handle systems with inconsistent cpu_has_fpu */
1090                 r = !!raw_cpu_has_fpu;
1091                 break;
1092         case KVM_CAP_MIPS_MSA:
1093                 /*
1094                  * We don't support MSA vector partitioning yet:
1095                  * 1) It would require explicit support which can't be tested
1096                  *    yet due to lack of support in current hardware.
1097                  * 2) It extends the state that would need to be saved/restored
1098                  *    by e.g. QEMU for migration.
1099                  *
1100                  * When vector partitioning hardware becomes available, support
1101                  * could be added by requiring a flag when enabling
1102                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1103                  * to save/restore the appropriate extra state.
1104                  */
1105                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1106                 break;
1107         default:
1108                 r = 0;
1109                 break;
1110         }
1111         return r;
1112 }
1113
1114 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1115 {
1116         return kvm_mips_pending_timer(vcpu);
1117 }
1118
1119 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1120 {
1121         int i;
1122         struct mips_coproc *cop0;
1123
1124         if (!vcpu)
1125                 return -1;
1126
1127         kvm_debug("VCPU Register Dump:\n");
1128         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1129         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1130
1131         for (i = 0; i < 32; i += 4) {
1132                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1133                        vcpu->arch.gprs[i],
1134                        vcpu->arch.gprs[i + 1],
1135                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1136         }
1137         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1138         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1139
1140         cop0 = vcpu->arch.cop0;
1141         kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1142                   kvm_read_c0_guest_status(cop0),
1143                   kvm_read_c0_guest_cause(cop0));
1144
1145         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1146
1147         return 0;
1148 }
1149
1150 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1151 {
1152         int i;
1153
1154         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1155                 vcpu->arch.gprs[i] = regs->gpr[i];
1156         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1157         vcpu->arch.hi = regs->hi;
1158         vcpu->arch.lo = regs->lo;
1159         vcpu->arch.pc = regs->pc;
1160
1161         return 0;
1162 }
1163
1164 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1165 {
1166         int i;
1167
1168         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1169                 regs->gpr[i] = vcpu->arch.gprs[i];
1170
1171         regs->hi = vcpu->arch.hi;
1172         regs->lo = vcpu->arch.lo;
1173         regs->pc = vcpu->arch.pc;
1174
1175         return 0;
1176 }
1177
1178 static void kvm_mips_comparecount_func(unsigned long data)
1179 {
1180         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1181
1182         kvm_mips_callbacks->queue_timer_int(vcpu);
1183
1184         vcpu->arch.wait = 0;
1185         if (swait_active(&vcpu->wq))
1186                 swake_up(&vcpu->wq);
1187 }
1188
1189 /* low level hrtimer wake routine */
1190 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1191 {
1192         struct kvm_vcpu *vcpu;
1193
1194         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1195         kvm_mips_comparecount_func((unsigned long) vcpu);
1196         return kvm_mips_count_timeout(vcpu);
1197 }
1198
1199 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1200 {
1201         kvm_mips_callbacks->vcpu_init(vcpu);
1202         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1203                      HRTIMER_MODE_REL);
1204         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1205         return 0;
1206 }
1207
1208 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1209                                   struct kvm_translation *tr)
1210 {
1211         return 0;
1212 }
1213
1214 /* Initial guest state */
1215 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1216 {
1217         return kvm_mips_callbacks->vcpu_setup(vcpu);
1218 }
1219
1220 static void kvm_mips_set_c0_status(void)
1221 {
1222         u32 status = read_c0_status();
1223
1224         if (cpu_has_dsp)
1225                 status |= (ST0_MX);
1226
1227         write_c0_status(status);
1228         ehb();
1229 }
1230
1231 /*
1232  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1233  */
1234 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1235 {
1236         u32 cause = vcpu->arch.host_cp0_cause;
1237         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1238         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1239         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1240         enum emulation_result er = EMULATE_DONE;
1241         int ret = RESUME_GUEST;
1242
1243         /* re-enable HTW before enabling interrupts */
1244         htw_start();
1245
1246         /* Set a default exit reason */
1247         run->exit_reason = KVM_EXIT_UNKNOWN;
1248         run->ready_for_interrupt_injection = 1;
1249
1250         /*
1251          * Set the appropriate status bits based on host CPU features,
1252          * before we hit the scheduler
1253          */
1254         kvm_mips_set_c0_status();
1255
1256         local_irq_enable();
1257
1258         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1259                         cause, opc, run, vcpu);
1260
1261         /*
1262          * Do a privilege check, if in UM most of these exit conditions end up
1263          * causing an exception to be delivered to the Guest Kernel
1264          */
1265         er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1266         if (er == EMULATE_PRIV_FAIL) {
1267                 goto skip_emul;
1268         } else if (er == EMULATE_FAIL) {
1269                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1270                 ret = RESUME_HOST;
1271                 goto skip_emul;
1272         }
1273
1274         switch (exccode) {
1275         case EXCCODE_INT:
1276                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1277
1278                 ++vcpu->stat.int_exits;
1279                 trace_kvm_exit(vcpu, INT_EXITS);
1280
1281                 if (need_resched())
1282                         cond_resched();
1283
1284                 ret = RESUME_GUEST;
1285                 break;
1286
1287         case EXCCODE_CPU:
1288                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1289
1290                 ++vcpu->stat.cop_unusable_exits;
1291                 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1292                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1293                 /* XXXKYMA: Might need to return to user space */
1294                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1295                         ret = RESUME_HOST;
1296                 break;
1297
1298         case EXCCODE_MOD:
1299                 ++vcpu->stat.tlbmod_exits;
1300                 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1301                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1302                 break;
1303
1304         case EXCCODE_TLBS:
1305                 kvm_debug("TLB ST fault:  cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1306                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1307                           badvaddr);
1308
1309                 ++vcpu->stat.tlbmiss_st_exits;
1310                 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1311                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1312                 break;
1313
1314         case EXCCODE_TLBL:
1315                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1316                           cause, opc, badvaddr);
1317
1318                 ++vcpu->stat.tlbmiss_ld_exits;
1319                 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1320                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1321                 break;
1322
1323         case EXCCODE_ADES:
1324                 ++vcpu->stat.addrerr_st_exits;
1325                 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1326                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1327                 break;
1328
1329         case EXCCODE_ADEL:
1330                 ++vcpu->stat.addrerr_ld_exits;
1331                 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1332                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1333                 break;
1334
1335         case EXCCODE_SYS:
1336                 ++vcpu->stat.syscall_exits;
1337                 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1338                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1339                 break;
1340
1341         case EXCCODE_RI:
1342                 ++vcpu->stat.resvd_inst_exits;
1343                 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1344                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1345                 break;
1346
1347         case EXCCODE_BP:
1348                 ++vcpu->stat.break_inst_exits;
1349                 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1350                 ret = kvm_mips_callbacks->handle_break(vcpu);
1351                 break;
1352
1353         case EXCCODE_TR:
1354                 ++vcpu->stat.trap_inst_exits;
1355                 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1356                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1357                 break;
1358
1359         case EXCCODE_MSAFPE:
1360                 ++vcpu->stat.msa_fpe_exits;
1361                 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1362                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1363                 break;
1364
1365         case EXCCODE_FPE:
1366                 ++vcpu->stat.fpe_exits;
1367                 trace_kvm_exit(vcpu, FPE_EXITS);
1368                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1369                 break;
1370
1371         case EXCCODE_MSADIS:
1372                 ++vcpu->stat.msa_disabled_exits;
1373                 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
1374                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1375                 break;
1376
1377         default:
1378                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#lx\n",
1379                         exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1380                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1381                 kvm_arch_vcpu_dump_regs(vcpu);
1382                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1383                 ret = RESUME_HOST;
1384                 break;
1385
1386         }
1387
1388 skip_emul:
1389         local_irq_disable();
1390
1391         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1392                 kvm_mips_deliver_interrupts(vcpu, cause);
1393
1394         if (!(ret & RESUME_HOST)) {
1395                 /* Only check for signals if not already exiting to userspace */
1396                 if (signal_pending(current)) {
1397                         run->exit_reason = KVM_EXIT_INTR;
1398                         ret = (-EINTR << 2) | RESUME_HOST;
1399                         ++vcpu->stat.signal_exits;
1400                         trace_kvm_exit(vcpu, SIGNAL_EXITS);
1401                 }
1402         }
1403
1404         if (ret == RESUME_GUEST) {
1405                 /*
1406                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1407                  * is live), restore FCR31 / MSACSR.
1408                  *
1409                  * This should be before returning to the guest exception
1410                  * vector, as it may well cause an [MSA] FP exception if there
1411                  * are pending exception bits unmasked. (see
1412                  * kvm_mips_csr_die_notifier() for how that is handled).
1413                  */
1414                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1415                     read_c0_status() & ST0_CU1)
1416                         __kvm_restore_fcsr(&vcpu->arch);
1417
1418                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1419                     read_c0_config5() & MIPS_CONF5_MSAEN)
1420                         __kvm_restore_msacsr(&vcpu->arch);
1421         }
1422
1423         /* Disable HTW before returning to guest or host */
1424         htw_stop();
1425
1426         return ret;
1427 }
1428
1429 /* Enable FPU for guest and restore context */
1430 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1431 {
1432         struct mips_coproc *cop0 = vcpu->arch.cop0;
1433         unsigned int sr, cfg5;
1434
1435         preempt_disable();
1436
1437         sr = kvm_read_c0_guest_status(cop0);
1438
1439         /*
1440          * If MSA state is already live, it is undefined how it interacts with
1441          * FR=0 FPU state, and we don't want to hit reserved instruction
1442          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1443          * play it safe and save it first.
1444          *
1445          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1446          * get called when guest CU1 is set, however we can't trust the guest
1447          * not to clobber the status register directly via the commpage.
1448          */
1449         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1450             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1451                 kvm_lose_fpu(vcpu);
1452
1453         /*
1454          * Enable FPU for guest
1455          * We set FR and FRE according to guest context
1456          */
1457         change_c0_status(ST0_CU1 | ST0_FR, sr);
1458         if (cpu_has_fre) {
1459                 cfg5 = kvm_read_c0_guest_config5(cop0);
1460                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1461         }
1462         enable_fpu_hazard();
1463
1464         /* If guest FPU state not active, restore it now */
1465         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1466                 __kvm_restore_fpu(&vcpu->arch);
1467                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1468         }
1469
1470         preempt_enable();
1471 }
1472
1473 #ifdef CONFIG_CPU_HAS_MSA
1474 /* Enable MSA for guest and restore context */
1475 void kvm_own_msa(struct kvm_vcpu *vcpu)
1476 {
1477         struct mips_coproc *cop0 = vcpu->arch.cop0;
1478         unsigned int sr, cfg5;
1479
1480         preempt_disable();
1481
1482         /*
1483          * Enable FPU if enabled in guest, since we're restoring FPU context
1484          * anyway. We set FR and FRE according to guest context.
1485          */
1486         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1487                 sr = kvm_read_c0_guest_status(cop0);
1488
1489                 /*
1490                  * If FR=0 FPU state is already live, it is undefined how it
1491                  * interacts with MSA state, so play it safe and save it first.
1492                  */
1493                 if (!(sr & ST0_FR) &&
1494                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1495                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1496                         kvm_lose_fpu(vcpu);
1497
1498                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1499                 if (sr & ST0_CU1 && cpu_has_fre) {
1500                         cfg5 = kvm_read_c0_guest_config5(cop0);
1501                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1502                 }
1503         }
1504
1505         /* Enable MSA for guest */
1506         set_c0_config5(MIPS_CONF5_MSAEN);
1507         enable_fpu_hazard();
1508
1509         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1510         case KVM_MIPS_AUX_FPU:
1511                 /*
1512                  * Guest FPU state already loaded, only restore upper MSA state
1513                  */
1514                 __kvm_restore_msa_upper(&vcpu->arch);
1515                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1516                 break;
1517         case 0:
1518                 /* Neither FPU or MSA already active, restore full MSA state */
1519                 __kvm_restore_msa(&vcpu->arch);
1520                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1521                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1522                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1523                 break;
1524         default:
1525                 break;
1526         }
1527
1528         preempt_enable();
1529 }
1530 #endif
1531
1532 /* Drop FPU & MSA without saving it */
1533 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1534 {
1535         preempt_disable();
1536         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1537                 disable_msa();
1538                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1539         }
1540         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1541                 clear_c0_status(ST0_CU1 | ST0_FR);
1542                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1543         }
1544         preempt_enable();
1545 }
1546
1547 /* Save and disable FPU & MSA */
1548 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1549 {
1550         /*
1551          * FPU & MSA get disabled in root context (hardware) when it is disabled
1552          * in guest context (software), but the register state in the hardware
1553          * may still be in use. This is why we explicitly re-enable the hardware
1554          * before saving.
1555          */
1556
1557         preempt_disable();
1558         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1559                 set_c0_config5(MIPS_CONF5_MSAEN);
1560                 enable_fpu_hazard();
1561
1562                 __kvm_save_msa(&vcpu->arch);
1563
1564                 /* Disable MSA & FPU */
1565                 disable_msa();
1566                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1567                         clear_c0_status(ST0_CU1 | ST0_FR);
1568                         disable_fpu_hazard();
1569                 }
1570                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1571         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1572                 set_c0_status(ST0_CU1);
1573                 enable_fpu_hazard();
1574
1575                 __kvm_save_fpu(&vcpu->arch);
1576                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1577
1578                 /* Disable FPU */
1579                 clear_c0_status(ST0_CU1 | ST0_FR);
1580                 disable_fpu_hazard();
1581         }
1582         preempt_enable();
1583 }
1584
1585 /*
1586  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1587  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1588  * exception if cause bits are set in the value being written.
1589  */
1590 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1591                                    unsigned long cmd, void *ptr)
1592 {
1593         struct die_args *args = (struct die_args *)ptr;
1594         struct pt_regs *regs = args->regs;
1595         unsigned long pc;
1596
1597         /* Only interested in FPE and MSAFPE */
1598         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1599                 return NOTIFY_DONE;
1600
1601         /* Return immediately if guest context isn't active */
1602         if (!(current->flags & PF_VCPU))
1603                 return NOTIFY_DONE;
1604
1605         /* Should never get here from user mode */
1606         BUG_ON(user_mode(regs));
1607
1608         pc = instruction_pointer(regs);
1609         switch (cmd) {
1610         case DIE_FP:
1611                 /* match 2nd instruction in __kvm_restore_fcsr */
1612                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1613                         return NOTIFY_DONE;
1614                 break;
1615         case DIE_MSAFP:
1616                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1617                 if (!cpu_has_msa ||
1618                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1619                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1620                         return NOTIFY_DONE;
1621                 break;
1622         }
1623
1624         /* Move PC forward a little and continue executing */
1625         instruction_pointer(regs) += 4;
1626
1627         return NOTIFY_STOP;
1628 }
1629
1630 static struct notifier_block kvm_mips_csr_die_notifier = {
1631         .notifier_call = kvm_mips_csr_die_notify,
1632 };
1633
1634 static int __init kvm_mips_init(void)
1635 {
1636         int ret;
1637
1638         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1639
1640         if (ret)
1641                 return ret;
1642
1643         register_die_notifier(&kvm_mips_csr_die_notifier);
1644
1645         return 0;
1646 }
1647
1648 static void __exit kvm_mips_exit(void)
1649 {
1650         kvm_exit();
1651
1652         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1653 }
1654
1655 module_init(kvm_mips_init);
1656 module_exit(kvm_mips_exit);
1657
1658 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);