2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: Support for hardware virtualization extensions
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Yann Le Du <ledu@kymasys.com>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/preempt.h>
16 #include <linux/vmalloc.h>
17 #include <asm/cacheflush.h>
18 #include <asm/cacheops.h>
19 #include <asm/cmpxchg.h>
21 #include <asm/hazards.h>
23 #include <asm/mmu_context.h>
24 #include <asm/r4kcache.h>
27 #include <asm/tlbex.h>
29 #include <linux/kvm_host.h>
31 #include "interrupt.h"
35 /* Pointers to last VCPU loaded on each physical CPU */
36 static struct kvm_vcpu *last_vcpu[NR_CPUS];
37 /* Pointers to last VCPU executed on each physical CPU */
38 static struct kvm_vcpu *last_exec_vcpu[NR_CPUS];
41 * Number of guest VTLB entries to use, so we can catch inconsistency between
44 static unsigned int kvm_vz_guest_vtlb_size;
46 static inline long kvm_vz_read_gc0_ebase(void)
48 if (sizeof(long) == 8 && cpu_has_ebase_wg)
49 return read_gc0_ebase_64();
51 return read_gc0_ebase();
54 static inline void kvm_vz_write_gc0_ebase(long v)
57 * First write with WG=1 to write upper bits, then write again in case
58 * WG should be left at 0.
59 * write_gc0_ebase_64() is no longer UNDEFINED since R6.
61 if (sizeof(long) == 8 &&
62 (cpu_has_mips64r6 || cpu_has_ebase_wg)) {
63 write_gc0_ebase_64(v | MIPS_EBASE_WG);
64 write_gc0_ebase_64(v);
66 write_gc0_ebase(v | MIPS_EBASE_WG);
72 * These Config bits may be writable by the guest:
73 * Config: [K23, KU] (!TLB), K0
75 * Config2: [TU, SU] (impl)
77 * Config4: FTLBPageSize
78 * Config5: K, CV, MSAEn, UFE, FRE, SBRI, UFR
81 static inline unsigned int kvm_vz_config_guest_wrmask(struct kvm_vcpu *vcpu)
86 static inline unsigned int kvm_vz_config1_guest_wrmask(struct kvm_vcpu *vcpu)
91 static inline unsigned int kvm_vz_config2_guest_wrmask(struct kvm_vcpu *vcpu)
96 static inline unsigned int kvm_vz_config3_guest_wrmask(struct kvm_vcpu *vcpu)
98 return MIPS_CONF3_ISA_OE;
101 static inline unsigned int kvm_vz_config4_guest_wrmask(struct kvm_vcpu *vcpu)
103 /* no need to be exact */
104 return MIPS_CONF4_VFTLBPAGESIZE;
107 static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu)
109 unsigned int mask = MIPS_CONF5_K | MIPS_CONF5_CV | MIPS_CONF5_SBRI;
111 /* Permit MSAEn changes if MSA supported and enabled */
112 if (kvm_mips_guest_has_msa(&vcpu->arch))
113 mask |= MIPS_CONF5_MSAEN;
116 * Permit guest FPU mode changes if FPU is enabled and the relevant
117 * feature exists according to FIR register.
119 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
121 mask |= MIPS_CONF5_UFR;
123 mask |= MIPS_CONF5_FRE | MIPS_CONF5_UFE;
130 * VZ optionally allows these additional Config bits to be written by root:
132 * Config1: M, [MMUSize-1, C2, MD, PC, WR, CA], FP
134 * Config3: M, MSAP, [BPG], ULRI, [DSP2P, DSPP], CTXTC, [ITL, LPA, VEIC,
135 * VInt, SP, CDMM, MT, SM, TL]
136 * Config4: M, [VTLBSizeExt, MMUSizeExt]
140 static inline unsigned int kvm_vz_config_user_wrmask(struct kvm_vcpu *vcpu)
142 return kvm_vz_config_guest_wrmask(vcpu) | MIPS_CONF_M;
145 static inline unsigned int kvm_vz_config1_user_wrmask(struct kvm_vcpu *vcpu)
147 unsigned int mask = kvm_vz_config1_guest_wrmask(vcpu) | MIPS_CONF_M;
149 /* Permit FPU to be present if FPU is supported */
150 if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
151 mask |= MIPS_CONF1_FP;
156 static inline unsigned int kvm_vz_config2_user_wrmask(struct kvm_vcpu *vcpu)
158 return kvm_vz_config2_guest_wrmask(vcpu) | MIPS_CONF_M;
161 static inline unsigned int kvm_vz_config3_user_wrmask(struct kvm_vcpu *vcpu)
163 unsigned int mask = kvm_vz_config3_guest_wrmask(vcpu) | MIPS_CONF_M |
164 MIPS_CONF3_ULRI | MIPS_CONF3_CTXTC;
166 /* Permit MSA to be present if MSA is supported */
167 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
168 mask |= MIPS_CONF3_MSA;
173 static inline unsigned int kvm_vz_config4_user_wrmask(struct kvm_vcpu *vcpu)
175 return kvm_vz_config4_guest_wrmask(vcpu) | MIPS_CONF_M;
178 static inline unsigned int kvm_vz_config5_user_wrmask(struct kvm_vcpu *vcpu)
180 return kvm_vz_config5_guest_wrmask(vcpu) | MIPS_CONF5_MRP;
183 static gpa_t kvm_vz_gva_to_gpa_cb(gva_t gva)
185 /* VZ guest has already converted gva to gpa */
189 static void kvm_vz_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
191 set_bit(priority, &vcpu->arch.pending_exceptions);
192 clear_bit(priority, &vcpu->arch.pending_exceptions_clr);
195 static void kvm_vz_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
197 clear_bit(priority, &vcpu->arch.pending_exceptions);
198 set_bit(priority, &vcpu->arch.pending_exceptions_clr);
201 static void kvm_vz_queue_timer_int_cb(struct kvm_vcpu *vcpu)
204 * timer expiry is asynchronous to vcpu execution therefore defer guest
207 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
210 static void kvm_vz_dequeue_timer_int_cb(struct kvm_vcpu *vcpu)
213 * timer expiry is asynchronous to vcpu execution therefore defer guest
216 kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_TIMER);
219 static void kvm_vz_queue_io_int_cb(struct kvm_vcpu *vcpu,
220 struct kvm_mips_interrupt *irq)
222 int intr = (int)irq->irq;
225 * interrupts are asynchronous to vcpu execution therefore defer guest
230 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_IO);
234 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_IPI_1);
238 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_IPI_2);
247 static void kvm_vz_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
248 struct kvm_mips_interrupt *irq)
250 int intr = (int)irq->irq;
253 * interrupts are asynchronous to vcpu execution therefore defer guest
258 kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_IO);
262 kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_1);
266 kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_2);
275 static u32 kvm_vz_priority_to_irq[MIPS_EXC_MAX] = {
276 [MIPS_EXC_INT_TIMER] = C_IRQ5,
277 [MIPS_EXC_INT_IO] = C_IRQ0,
278 [MIPS_EXC_INT_IPI_1] = C_IRQ1,
279 [MIPS_EXC_INT_IPI_2] = C_IRQ2,
282 static int kvm_vz_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
285 u32 irq = (priority < MIPS_EXC_MAX) ?
286 kvm_vz_priority_to_irq[priority] : 0;
289 case MIPS_EXC_INT_TIMER:
293 case MIPS_EXC_INT_IO:
294 case MIPS_EXC_INT_IPI_1:
295 case MIPS_EXC_INT_IPI_2:
296 if (cpu_has_guestctl2)
297 set_c0_guestctl2(irq);
306 clear_bit(priority, &vcpu->arch.pending_exceptions);
310 static int kvm_vz_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
313 u32 irq = (priority < MIPS_EXC_MAX) ?
314 kvm_vz_priority_to_irq[priority] : 0;
317 case MIPS_EXC_INT_TIMER:
319 * Call to kvm_write_c0_guest_compare() clears Cause.TI in
320 * kvm_mips_emulate_CP0(). Explicitly clear irq associated with
321 * Cause.IP[IPTI] if GuestCtl2 virtual interrupt register not
322 * supported or if not using GuestCtl2 Hardware Clear.
324 if (cpu_has_guestctl2) {
325 if (!(read_c0_guestctl2() & (irq << 14)))
326 clear_c0_guestctl2(irq);
328 clear_gc0_cause(irq);
332 case MIPS_EXC_INT_IO:
333 case MIPS_EXC_INT_IPI_1:
334 case MIPS_EXC_INT_IPI_2:
335 /* Clear GuestCtl2.VIP irq if not using Hardware Clear */
336 if (cpu_has_guestctl2) {
337 if (!(read_c0_guestctl2() & (irq << 14)))
338 clear_c0_guestctl2(irq);
340 clear_gc0_cause(irq);
348 clear_bit(priority, &vcpu->arch.pending_exceptions_clr);
353 * VZ guest timer handling.
357 * kvm_vz_should_use_htimer() - Find whether to use the VZ hard guest timer.
358 * @vcpu: Virtual CPU.
360 * Returns: true if the VZ GTOffset & real guest CP0_Count should be used
361 * instead of software emulation of guest timer.
364 static bool kvm_vz_should_use_htimer(struct kvm_vcpu *vcpu)
366 if (kvm_mips_count_disabled(vcpu))
369 /* Chosen frequency must match real frequency */
370 if (mips_hpt_frequency != vcpu->arch.count_hz)
373 /* We don't support a CP0_GTOffset with fewer bits than CP0_Count */
374 if (current_cpu_data.gtoffset_mask != 0xffffffff)
381 * _kvm_vz_restore_stimer() - Restore soft timer state.
382 * @vcpu: Virtual CPU.
383 * @compare: CP0_Compare register value, restored by caller.
384 * @cause: CP0_Cause register to restore.
386 * Restore VZ state relating to the soft timer. The hard timer can be enabled
389 static void _kvm_vz_restore_stimer(struct kvm_vcpu *vcpu, u32 compare,
393 * Avoid spurious counter interrupts by setting Guest CP0_Count to just
394 * after Guest CP0_Compare.
396 write_c0_gtoffset(compare - read_c0_count());
398 back_to_back_c0_hazard();
399 write_gc0_cause(cause);
403 * _kvm_vz_restore_htimer() - Restore hard timer state.
404 * @vcpu: Virtual CPU.
405 * @compare: CP0_Compare register value, restored by caller.
406 * @cause: CP0_Cause register to restore.
408 * Restore hard timer Guest.Count & Guest.Cause taking care to preserve the
409 * value of Guest.CP0_Cause.TI while restoring Guest.CP0_Cause.
411 static void _kvm_vz_restore_htimer(struct kvm_vcpu *vcpu,
412 u32 compare, u32 cause)
414 u32 start_count, after_count;
419 * Freeze the soft-timer and sync the guest CP0_Count with it. We do
420 * this with interrupts disabled to avoid latency.
422 local_irq_save(flags);
423 freeze_time = kvm_mips_freeze_hrtimer(vcpu, &start_count);
424 write_c0_gtoffset(start_count - read_c0_count());
425 local_irq_restore(flags);
427 /* restore guest CP0_Cause, as TI may already be set */
428 back_to_back_c0_hazard();
429 write_gc0_cause(cause);
432 * The above sequence isn't atomic and would result in lost timer
433 * interrupts if we're not careful. Detect if a timer interrupt is due
436 back_to_back_c0_hazard();
437 after_count = read_gc0_count();
438 if (after_count - start_count > compare - start_count - 1)
439 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
443 * kvm_vz_restore_timer() - Restore timer state.
444 * @vcpu: Virtual CPU.
446 * Restore soft timer state from saved context.
448 static void kvm_vz_restore_timer(struct kvm_vcpu *vcpu)
450 struct mips_coproc *cop0 = vcpu->arch.cop0;
453 compare = kvm_read_sw_gc0_compare(cop0);
454 cause = kvm_read_sw_gc0_cause(cop0);
456 write_gc0_compare(compare);
457 _kvm_vz_restore_stimer(vcpu, compare, cause);
461 * kvm_vz_acquire_htimer() - Switch to hard timer state.
462 * @vcpu: Virtual CPU.
464 * Restore hard timer state on top of existing soft timer state if possible.
466 * Since hard timer won't remain active over preemption, preemption should be
467 * disabled by the caller.
469 void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu)
473 gctl0 = read_c0_guestctl0();
474 if (!(gctl0 & MIPS_GCTL0_GT) && kvm_vz_should_use_htimer(vcpu)) {
475 /* enable guest access to hard timer */
476 write_c0_guestctl0(gctl0 | MIPS_GCTL0_GT);
478 _kvm_vz_restore_htimer(vcpu, read_gc0_compare(),
484 * _kvm_vz_save_htimer() - Switch to software emulation of guest timer.
485 * @vcpu: Virtual CPU.
486 * @compare: Pointer to write compare value to.
487 * @cause: Pointer to write cause value to.
489 * Save VZ guest timer state and switch to software emulation of guest CP0
490 * timer. The hard timer must already be in use, so preemption should be
493 static void _kvm_vz_save_htimer(struct kvm_vcpu *vcpu,
494 u32 *out_compare, u32 *out_cause)
496 u32 cause, compare, before_count, end_count;
499 compare = read_gc0_compare();
500 *out_compare = compare;
502 before_time = ktime_get();
505 * Record the CP0_Count *prior* to saving CP0_Cause, so we have a time
506 * at which no pending timer interrupt is missing.
508 before_count = read_gc0_count();
509 back_to_back_c0_hazard();
510 cause = read_gc0_cause();
514 * Record a final CP0_Count which we will transfer to the soft-timer.
515 * This is recorded *after* saving CP0_Cause, so we don't get any timer
516 * interrupts from just after the final CP0_Count point.
518 back_to_back_c0_hazard();
519 end_count = read_gc0_count();
522 * The above sequence isn't atomic, so we could miss a timer interrupt
523 * between reading CP0_Cause and end_count. Detect and record any timer
524 * interrupt due between before_count and end_count.
526 if (end_count - before_count > compare - before_count - 1)
527 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
530 * Restore soft-timer, ignoring a small amount of negative drift due to
531 * delay between freeze_hrtimer and setting CP0_GTOffset.
533 kvm_mips_restore_hrtimer(vcpu, before_time, end_count, -0x10000);
537 * kvm_vz_save_timer() - Save guest timer state.
538 * @vcpu: Virtual CPU.
540 * Save VZ guest timer state and switch to soft guest timer if hard timer was in
543 static void kvm_vz_save_timer(struct kvm_vcpu *vcpu)
545 struct mips_coproc *cop0 = vcpu->arch.cop0;
546 u32 gctl0, compare, cause;
548 gctl0 = read_c0_guestctl0();
549 if (gctl0 & MIPS_GCTL0_GT) {
550 /* disable guest use of hard timer */
551 write_c0_guestctl0(gctl0 & ~MIPS_GCTL0_GT);
553 /* save hard timer state */
554 _kvm_vz_save_htimer(vcpu, &compare, &cause);
556 compare = read_gc0_compare();
557 cause = read_gc0_cause();
560 /* save timer-related state to VCPU context */
561 kvm_write_sw_gc0_cause(cop0, cause);
562 kvm_write_sw_gc0_compare(cop0, compare);
566 * kvm_vz_lose_htimer() - Ensure hard guest timer is not in use.
567 * @vcpu: Virtual CPU.
569 * Transfers the state of the hard guest timer to the soft guest timer, leaving
570 * guest state intact so it can continue to be used with the soft timer.
572 void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu)
574 u32 gctl0, compare, cause;
577 gctl0 = read_c0_guestctl0();
578 if (gctl0 & MIPS_GCTL0_GT) {
579 /* disable guest use of timer */
580 write_c0_guestctl0(gctl0 & ~MIPS_GCTL0_GT);
582 /* switch to soft timer */
583 _kvm_vz_save_htimer(vcpu, &compare, &cause);
585 /* leave soft timer in usable state */
586 _kvm_vz_restore_stimer(vcpu, compare, cause);
592 * is_eva_access() - Find whether an instruction is an EVA memory accessor.
593 * @inst: 32-bit instruction encoding.
595 * Finds whether @inst encodes an EVA memory access instruction, which would
596 * indicate that emulation of it should access the user mode address space
597 * instead of the kernel mode address space. This matters for MUSUK segments
598 * which are TLB mapped for user mode but unmapped for kernel mode.
600 * Returns: Whether @inst encodes an EVA accessor instruction.
602 static bool is_eva_access(union mips_instruction inst)
604 if (inst.spec3_format.opcode != spec3_op)
607 switch (inst.spec3_format.func) {
631 * is_eva_am_mapped() - Find whether an access mode is mapped.
632 * @vcpu: KVM VCPU state.
633 * @am: 3-bit encoded access mode.
634 * @eu: Segment becomes unmapped and uncached when Status.ERL=1.
636 * Decode @am to find whether it encodes a mapped segment for the current VCPU
637 * state. Where necessary @eu and the actual instruction causing the fault are
638 * taken into account to make the decision.
640 * Returns: Whether the VCPU faulted on a TLB mapped address.
642 static bool is_eva_am_mapped(struct kvm_vcpu *vcpu, unsigned int am, bool eu)
648 * Interpret access control mode. We assume address errors will already
649 * have been caught by the guest, leaving us with:
650 * AM UM SM KM 31..24 23..16
653 * MSK 2 010 TLB TLB 1
654 * MUSK 3 011 TLB TLB TLB 1
655 * MUSUK 4 100 TLB TLB Unm 0 1
656 * USK 5 101 Unm Unm 0 0
658 * UUSK 7 111 Unm Unm Unm 0 0
660 * We shift a magic value by AM across the sign bit to find if always
661 * TLB mapped, and if not shift by 8 again to find if it depends on KM.
663 am_lookup = 0x70080000 << am;
664 if ((s32)am_lookup < 0) {
667 * Always TLB mapped, unless SegCtl.EU && ERL
669 if (!eu || !(read_gc0_status() & ST0_ERL))
673 if ((s32)am_lookup < 0) {
674 union mips_instruction inst;
680 * TLB mapped if not in kernel mode
682 status = read_gc0_status();
683 if (!(status & (ST0_EXL | ST0_ERL)) &&
687 * EVA access instructions in kernel
688 * mode access user address space.
690 opc = (u32 *)vcpu->arch.pc;
691 if (vcpu->arch.host_cp0_cause & CAUSEF_BD)
693 err = kvm_get_badinstr(opc, vcpu, &inst.word);
694 if (!err && is_eva_access(inst))
703 * kvm_vz_gva_to_gpa() - Convert valid GVA to GPA.
704 * @vcpu: KVM VCPU state.
705 * @gva: Guest virtual address to convert.
706 * @gpa: Output guest physical address.
708 * Convert a guest virtual address (GVA) which is valid according to the guest
709 * context, to a guest physical address (GPA).
711 * Returns: 0 on success.
714 static int kvm_vz_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
718 unsigned long segctl;
720 if ((long)gva == (s32)gva32) {
721 /* Handle canonical 32-bit virtual address */
722 if (cpu_guest_has_segments) {
723 unsigned long mask, pa;
725 switch (gva32 >> 29) {
727 case 1: /* CFG5 (1GB) */
728 segctl = read_gc0_segctl2() >> 16;
729 mask = (unsigned long)0xfc0000000ull;
732 case 3: /* CFG4 (1GB) */
733 segctl = read_gc0_segctl2();
734 mask = (unsigned long)0xfc0000000ull;
736 case 4: /* CFG3 (512MB) */
737 segctl = read_gc0_segctl1() >> 16;
738 mask = (unsigned long)0xfe0000000ull;
740 case 5: /* CFG2 (512MB) */
741 segctl = read_gc0_segctl1();
742 mask = (unsigned long)0xfe0000000ull;
744 case 6: /* CFG1 (512MB) */
745 segctl = read_gc0_segctl0() >> 16;
746 mask = (unsigned long)0xfe0000000ull;
748 case 7: /* CFG0 (512MB) */
749 segctl = read_gc0_segctl0();
750 mask = (unsigned long)0xfe0000000ull;
754 * GCC 4.9 isn't smart enough to figure out that
755 * segctl and mask are always initialised.
760 if (is_eva_am_mapped(vcpu, (segctl >> 4) & 0x7,
764 /* Unmapped, find guest physical address */
765 pa = (segctl << 20) & mask;
769 } else if ((s32)gva32 < (s32)0xc0000000) {
770 /* legacy unmapped KSeg0 or KSeg1 */
771 *gpa = gva32 & 0x1fffffff;
775 } else if ((gva & 0xc000000000000000) == 0x8000000000000000) {
777 if (cpu_guest_has_segments) {
779 * Each of the 8 regions can be overridden by SegCtl2.XR
780 * to use SegCtl1.XAM.
782 segctl = read_gc0_segctl2();
783 if (segctl & (1ull << (56 + ((gva >> 59) & 0x7)))) {
784 segctl = read_gc0_segctl1();
785 if (is_eva_am_mapped(vcpu, (segctl >> 59) & 0x7,
792 * Traditionally fully unmapped.
793 * Bits 61:59 specify the CCA, which we can just mask off here.
794 * Bits 58:PABITS should be zero, but we shouldn't have got here
797 *gpa = gva & 0x07ffffffffffffff;
803 return kvm_vz_guest_tlb_lookup(vcpu, gva, gpa);
807 * kvm_vz_badvaddr_to_gpa() - Convert GVA BadVAddr from root exception to GPA.
808 * @vcpu: KVM VCPU state.
809 * @badvaddr: Root BadVAddr.
810 * @gpa: Output guest physical address.
812 * VZ implementations are permitted to report guest virtual addresses (GVA) in
813 * BadVAddr on a root exception during guest execution, instead of the more
814 * convenient guest physical addresses (GPA). When we get a GVA, this function
815 * converts it to a GPA, taking into account guest segmentation and guest TLB
818 * Returns: 0 on success.
821 static int kvm_vz_badvaddr_to_gpa(struct kvm_vcpu *vcpu, unsigned long badvaddr,
824 unsigned int gexccode = (vcpu->arch.host_cp0_guestctl0 &
825 MIPS_GCTL0_GEXC) >> MIPS_GCTL0_GEXC_SHIFT;
827 /* If BadVAddr is GPA, then all is well in the world */
828 if (likely(gexccode == MIPS_GCTL0_GEXC_GPA)) {
833 /* Otherwise we'd expect it to be GVA ... */
834 if (WARN(gexccode != MIPS_GCTL0_GEXC_GVA,
835 "Unexpected gexccode %#x\n", gexccode))
838 /* ... and we need to perform the GVA->GPA translation in software */
839 return kvm_vz_gva_to_gpa(vcpu, badvaddr, gpa);
842 static int kvm_trap_vz_no_handler(struct kvm_vcpu *vcpu)
844 u32 *opc = (u32 *) vcpu->arch.pc;
845 u32 cause = vcpu->arch.host_cp0_cause;
846 u32 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
847 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
851 * Fetch the instruction.
853 if (cause & CAUSEF_BD)
855 kvm_get_badinstr(opc, vcpu, &inst);
857 kvm_err("Exception Code: %d not handled @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
858 exccode, opc, inst, badvaddr,
860 kvm_arch_vcpu_dump_regs(vcpu);
861 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
865 static unsigned long mips_process_maar(unsigned int op, unsigned long val)
867 /* Mask off unused bits */
868 unsigned long mask = 0xfffff000 | MIPS_MAAR_S | MIPS_MAAR_VL;
870 if (read_gc0_pagegrain() & PG_ELPA)
871 mask |= 0x00ffffff00000000ull;
872 if (cpu_guest_has_mvh)
873 mask |= MIPS_MAAR_VH;
875 /* Set or clear VH */
878 val &= ~MIPS_MAAR_VH;
879 } else if (op == dmtc_op) {
880 /* set VH to match VL */
881 val &= ~MIPS_MAAR_VH;
882 if (val & MIPS_MAAR_VL)
889 static void kvm_write_maari(struct kvm_vcpu *vcpu, unsigned long val)
891 struct mips_coproc *cop0 = vcpu->arch.cop0;
893 val &= MIPS_MAARI_INDEX;
894 if (val == MIPS_MAARI_INDEX)
895 kvm_write_sw_gc0_maari(cop0, ARRAY_SIZE(vcpu->arch.maar) - 1);
896 else if (val < ARRAY_SIZE(vcpu->arch.maar))
897 kvm_write_sw_gc0_maari(cop0, val);
900 static enum emulation_result kvm_vz_gpsi_cop0(union mips_instruction inst,
903 struct kvm_vcpu *vcpu)
905 struct mips_coproc *cop0 = vcpu->arch.cop0;
906 enum emulation_result er = EMULATE_DONE;
908 unsigned long curr_pc;
912 * Update PC and hold onto current PC in case there is
913 * an error and we want to rollback the PC
915 curr_pc = vcpu->arch.pc;
916 er = update_pc(vcpu, cause);
917 if (er == EMULATE_FAIL)
920 if (inst.co_format.co) {
921 switch (inst.co_format.func) {
923 er = kvm_mips_emul_wait(vcpu);
929 rt = inst.c0r_format.rt;
930 rd = inst.c0r_format.rd;
931 sel = inst.c0r_format.sel;
933 switch (inst.c0r_format.rs) {
936 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
937 cop0->stat[rd][sel]++;
939 if (rd == MIPS_CP0_COUNT &&
940 sel == 0) { /* Count */
941 val = kvm_mips_read_count(vcpu);
942 } else if (rd == MIPS_CP0_COMPARE &&
943 sel == 0) { /* Compare */
944 val = read_gc0_compare();
945 } else if (rd == MIPS_CP0_LLADDR &&
946 sel == 0) { /* LLAddr */
947 if (cpu_guest_has_rw_llb)
948 val = read_gc0_lladdr() &
952 } else if (rd == MIPS_CP0_LLADDR &&
953 sel == 1 && /* MAAR */
954 cpu_guest_has_maar &&
955 !cpu_guest_has_dyn_maar) {
956 /* MAARI must be in range */
957 BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
958 ARRAY_SIZE(vcpu->arch.maar));
959 val = vcpu->arch.maar[
960 kvm_read_sw_gc0_maari(cop0)];
961 } else if ((rd == MIPS_CP0_PRID &&
962 (sel == 0 || /* PRid */
963 sel == 2 || /* CDMMBase */
964 sel == 3)) || /* CMGCRBase */
965 (rd == MIPS_CP0_STATUS &&
966 (sel == 2 || /* SRSCtl */
967 sel == 3)) || /* SRSMap */
968 (rd == MIPS_CP0_CONFIG &&
969 (sel == 7)) || /* Config7 */
970 (rd == MIPS_CP0_LLADDR &&
971 (sel == 2) && /* MAARI */
972 cpu_guest_has_maar &&
973 !cpu_guest_has_dyn_maar) ||
974 (rd == MIPS_CP0_ERRCTL &&
975 (sel == 0))) { /* ErrCtl */
976 val = cop0->reg[rd][sel];
982 if (er != EMULATE_FAIL) {
984 if (inst.c0r_format.rs == mfc_op)
986 vcpu->arch.gprs[rt] = val;
989 trace_kvm_hwr(vcpu, (inst.c0r_format.rs == mfc_op) ?
990 KVM_TRACE_MFC0 : KVM_TRACE_DMFC0,
991 KVM_TRACE_COP0(rd, sel), val);
996 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
997 cop0->stat[rd][sel]++;
999 val = vcpu->arch.gprs[rt];
1000 trace_kvm_hwr(vcpu, (inst.c0r_format.rs == mtc_op) ?
1001 KVM_TRACE_MTC0 : KVM_TRACE_DMTC0,
1002 KVM_TRACE_COP0(rd, sel), val);
1004 if (rd == MIPS_CP0_COUNT &&
1005 sel == 0) { /* Count */
1006 kvm_vz_lose_htimer(vcpu);
1007 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1008 } else if (rd == MIPS_CP0_COMPARE &&
1009 sel == 0) { /* Compare */
1010 kvm_mips_write_compare(vcpu,
1011 vcpu->arch.gprs[rt],
1013 } else if (rd == MIPS_CP0_LLADDR &&
1014 sel == 0) { /* LLAddr */
1016 * P5600 generates GPSI on guest MTC0 LLAddr.
1017 * Only allow the guest to clear LLB.
1019 if (cpu_guest_has_rw_llb &&
1020 !(val & MIPS_LLADDR_LLB))
1021 write_gc0_lladdr(0);
1022 } else if (rd == MIPS_CP0_LLADDR &&
1023 sel == 1 && /* MAAR */
1024 cpu_guest_has_maar &&
1025 !cpu_guest_has_dyn_maar) {
1026 val = mips_process_maar(inst.c0r_format.rs,
1029 /* MAARI must be in range */
1030 BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
1031 ARRAY_SIZE(vcpu->arch.maar));
1032 vcpu->arch.maar[kvm_read_sw_gc0_maari(cop0)] =
1034 } else if (rd == MIPS_CP0_LLADDR &&
1035 (sel == 2) && /* MAARI */
1036 cpu_guest_has_maar &&
1037 !cpu_guest_has_dyn_maar) {
1038 kvm_write_maari(vcpu, val);
1039 } else if (rd == MIPS_CP0_ERRCTL &&
1040 (sel == 0)) { /* ErrCtl */
1041 /* ignore the written value */
1052 /* Rollback PC only if emulation was unsuccessful */
1053 if (er == EMULATE_FAIL) {
1054 kvm_err("[%#lx]%s: unsupported cop0 instruction 0x%08x\n",
1055 curr_pc, __func__, inst.word);
1057 vcpu->arch.pc = curr_pc;
1063 static enum emulation_result kvm_vz_gpsi_cache(union mips_instruction inst,
1064 u32 *opc, u32 cause,
1065 struct kvm_run *run,
1066 struct kvm_vcpu *vcpu)
1068 enum emulation_result er = EMULATE_DONE;
1069 u32 cache, op_inst, op, base;
1071 struct kvm_vcpu_arch *arch = &vcpu->arch;
1072 unsigned long va, curr_pc;
1075 * Update PC and hold onto current PC in case there is
1076 * an error and we want to rollback the PC
1078 curr_pc = vcpu->arch.pc;
1079 er = update_pc(vcpu, cause);
1080 if (er == EMULATE_FAIL)
1083 base = inst.i_format.rs;
1084 op_inst = inst.i_format.rt;
1085 if (cpu_has_mips_r6)
1086 offset = inst.spec3_format.simmediate;
1088 offset = inst.i_format.simmediate;
1089 cache = op_inst & CacheOp_Cache;
1090 op = op_inst & CacheOp_Op;
1092 va = arch->gprs[base] + offset;
1094 kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1095 cache, op, base, arch->gprs[base], offset);
1097 /* Secondary or tirtiary cache ops ignored */
1098 if (cache != Cache_I && cache != Cache_D)
1099 return EMULATE_DONE;
1102 case Index_Invalidate_I:
1103 flush_icache_line_indexed(va);
1104 return EMULATE_DONE;
1105 case Index_Writeback_Inv_D:
1106 flush_dcache_line_indexed(va);
1107 return EMULATE_DONE;
1112 kvm_err("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1113 curr_pc, vcpu->arch.gprs[31], cache, op, base, arch->gprs[base],
1116 vcpu->arch.pc = curr_pc;
1118 return EMULATE_FAIL;
1121 static enum emulation_result kvm_trap_vz_handle_gpsi(u32 cause, u32 *opc,
1122 struct kvm_vcpu *vcpu)
1124 enum emulation_result er = EMULATE_DONE;
1125 struct kvm_vcpu_arch *arch = &vcpu->arch;
1126 struct kvm_run *run = vcpu->run;
1127 union mips_instruction inst;
1132 * Fetch the instruction.
1134 if (cause & CAUSEF_BD)
1136 err = kvm_get_badinstr(opc, vcpu, &inst.word);
1138 return EMULATE_FAIL;
1140 switch (inst.r_format.opcode) {
1142 er = kvm_vz_gpsi_cop0(inst, opc, cause, run, vcpu);
1144 #ifndef CONFIG_CPU_MIPSR6
1146 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
1147 er = kvm_vz_gpsi_cache(inst, opc, cause, run, vcpu);
1151 switch (inst.spec3_format.func) {
1152 #ifdef CONFIG_CPU_MIPSR6
1154 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
1155 er = kvm_vz_gpsi_cache(inst, opc, cause, run, vcpu);
1159 if (inst.r_format.rs || (inst.r_format.re >> 3))
1162 rd = inst.r_format.rd;
1163 rt = inst.r_format.rt;
1164 sel = inst.r_format.re & 0x7;
1167 case MIPS_HWR_CC: /* Read count register */
1169 (long)(int)kvm_mips_read_count(vcpu);
1172 trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR,
1173 KVM_TRACE_HWR(rd, sel), 0);
1177 trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR,
1178 KVM_TRACE_HWR(rd, sel), arch->gprs[rt]);
1180 er = update_pc(vcpu, cause);
1189 kvm_err("GPSI exception not supported (%p/%#x)\n",
1191 kvm_arch_vcpu_dump_regs(vcpu);
1199 static enum emulation_result kvm_trap_vz_handle_gsfc(u32 cause, u32 *opc,
1200 struct kvm_vcpu *vcpu)
1202 enum emulation_result er = EMULATE_DONE;
1203 struct kvm_vcpu_arch *arch = &vcpu->arch;
1204 union mips_instruction inst;
1208 * Fetch the instruction.
1210 if (cause & CAUSEF_BD)
1212 err = kvm_get_badinstr(opc, vcpu, &inst.word);
1214 return EMULATE_FAIL;
1216 /* complete MTC0 on behalf of guest and advance EPC */
1217 if (inst.c0r_format.opcode == cop0_op &&
1218 inst.c0r_format.rs == mtc_op &&
1219 inst.c0r_format.z == 0) {
1220 int rt = inst.c0r_format.rt;
1221 int rd = inst.c0r_format.rd;
1222 int sel = inst.c0r_format.sel;
1223 unsigned int val = arch->gprs[rt];
1224 unsigned int old_val, change;
1226 trace_kvm_hwr(vcpu, KVM_TRACE_MTC0, KVM_TRACE_COP0(rd, sel),
1229 if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1230 /* FR bit should read as zero if no FPU */
1231 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1232 val &= ~(ST0_CU1 | ST0_FR);
1235 * Also don't allow FR to be set if host doesn't support
1238 if (!(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
1241 old_val = read_gc0_status();
1242 change = val ^ old_val;
1244 if (change & ST0_FR) {
1246 * FPU and Vector register state is made
1247 * UNPREDICTABLE by a change of FR, so don't
1248 * even bother saving it.
1254 * If MSA state is already live, it is undefined how it
1255 * interacts with FR=0 FPU state, and we don't want to
1256 * hit reserved instruction exceptions trying to save
1257 * the MSA state later when CU=1 && FR=1, so play it
1258 * safe and save it first.
1260 if (change & ST0_CU1 && !(val & ST0_FR) &&
1261 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1264 write_gc0_status(val);
1265 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1266 u32 old_cause = read_gc0_cause();
1267 u32 change = old_cause ^ val;
1269 /* DC bit enabling/disabling timer? */
1270 if (change & CAUSEF_DC) {
1271 if (val & CAUSEF_DC) {
1272 kvm_vz_lose_htimer(vcpu);
1273 kvm_mips_count_disable_cause(vcpu);
1275 kvm_mips_count_enable_cause(vcpu);
1279 /* Only certain bits are RW to the guest */
1280 change &= (CAUSEF_DC | CAUSEF_IV | CAUSEF_WP |
1281 CAUSEF_IP0 | CAUSEF_IP1);
1283 /* WP can only be cleared */
1284 change &= ~CAUSEF_WP | old_cause;
1286 write_gc0_cause(old_cause ^ change);
1287 } else if ((rd == MIPS_CP0_STATUS) && (sel == 1)) { /* IntCtl */
1288 write_gc0_intctl(val);
1289 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1290 old_val = read_gc0_config5();
1291 change = val ^ old_val;
1292 /* Handle changes in FPU/MSA modes */
1296 * Propagate FRE changes immediately if the FPU
1297 * context is already loaded.
1299 if (change & MIPS_CONF5_FRE &&
1300 vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1301 change_c0_config5(MIPS_CONF5_FRE, val);
1306 (change & kvm_vz_config5_guest_wrmask(vcpu));
1307 write_gc0_config5(val);
1309 kvm_err("Handle GSFC, unsupported field change @ %p: %#x\n",
1314 if (er != EMULATE_FAIL)
1315 er = update_pc(vcpu, cause);
1317 kvm_err("Handle GSFC, unrecognized instruction @ %p: %#x\n",
1325 static enum emulation_result kvm_trap_vz_handle_ghfc(u32 cause, u32 *opc,
1326 struct kvm_vcpu *vcpu)
1329 * Presumably this is due to MC (guest mode change), so lets trace some
1332 trace_kvm_guest_mode_change(vcpu);
1334 return EMULATE_DONE;
1337 static enum emulation_result kvm_trap_vz_handle_hc(u32 cause, u32 *opc,
1338 struct kvm_vcpu *vcpu)
1340 enum emulation_result er;
1341 union mips_instruction inst;
1342 unsigned long curr_pc;
1345 if (cause & CAUSEF_BD)
1347 err = kvm_get_badinstr(opc, vcpu, &inst.word);
1349 return EMULATE_FAIL;
1352 * Update PC and hold onto current PC in case there is
1353 * an error and we want to rollback the PC
1355 curr_pc = vcpu->arch.pc;
1356 er = update_pc(vcpu, cause);
1357 if (er == EMULATE_FAIL)
1360 er = kvm_mips_emul_hypcall(vcpu, inst);
1361 if (er == EMULATE_FAIL)
1362 vcpu->arch.pc = curr_pc;
1367 static enum emulation_result kvm_trap_vz_no_handler_guest_exit(u32 gexccode,
1370 struct kvm_vcpu *vcpu)
1375 * Fetch the instruction.
1377 if (cause & CAUSEF_BD)
1379 kvm_get_badinstr(opc, vcpu, &inst);
1381 kvm_err("Guest Exception Code: %d not yet handled @ PC: %p, inst: 0x%08x Status: %#x\n",
1382 gexccode, opc, inst, read_gc0_status());
1384 return EMULATE_FAIL;
1387 static int kvm_trap_vz_handle_guest_exit(struct kvm_vcpu *vcpu)
1389 u32 *opc = (u32 *) vcpu->arch.pc;
1390 u32 cause = vcpu->arch.host_cp0_cause;
1391 enum emulation_result er = EMULATE_DONE;
1392 u32 gexccode = (vcpu->arch.host_cp0_guestctl0 &
1393 MIPS_GCTL0_GEXC) >> MIPS_GCTL0_GEXC_SHIFT;
1394 int ret = RESUME_GUEST;
1396 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_GEXCCODE_BASE + gexccode);
1398 case MIPS_GCTL0_GEXC_GPSI:
1399 ++vcpu->stat.vz_gpsi_exits;
1400 er = kvm_trap_vz_handle_gpsi(cause, opc, vcpu);
1402 case MIPS_GCTL0_GEXC_GSFC:
1403 ++vcpu->stat.vz_gsfc_exits;
1404 er = kvm_trap_vz_handle_gsfc(cause, opc, vcpu);
1406 case MIPS_GCTL0_GEXC_HC:
1407 ++vcpu->stat.vz_hc_exits;
1408 er = kvm_trap_vz_handle_hc(cause, opc, vcpu);
1410 case MIPS_GCTL0_GEXC_GRR:
1411 ++vcpu->stat.vz_grr_exits;
1412 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1415 case MIPS_GCTL0_GEXC_GVA:
1416 ++vcpu->stat.vz_gva_exits;
1417 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1420 case MIPS_GCTL0_GEXC_GHFC:
1421 ++vcpu->stat.vz_ghfc_exits;
1422 er = kvm_trap_vz_handle_ghfc(cause, opc, vcpu);
1424 case MIPS_GCTL0_GEXC_GPA:
1425 ++vcpu->stat.vz_gpa_exits;
1426 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1430 ++vcpu->stat.vz_resvd_exits;
1431 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1437 if (er == EMULATE_DONE) {
1439 } else if (er == EMULATE_HYPERCALL) {
1440 ret = kvm_mips_handle_hypcall(vcpu);
1442 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1449 * kvm_trap_vz_handle_cop_unusuable() - Guest used unusable coprocessor.
1450 * @vcpu: Virtual CPU context.
1452 * Handle when the guest attempts to use a coprocessor which hasn't been allowed
1453 * by the root context.
1455 static int kvm_trap_vz_handle_cop_unusable(struct kvm_vcpu *vcpu)
1457 struct kvm_run *run = vcpu->run;
1458 u32 cause = vcpu->arch.host_cp0_cause;
1459 enum emulation_result er = EMULATE_FAIL;
1460 int ret = RESUME_GUEST;
1462 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 1) {
1464 * If guest FPU not present, the FPU operation should have been
1465 * treated as a reserved instruction!
1466 * If FPU already in use, we shouldn't get this at all.
1468 if (WARN_ON(!kvm_mips_guest_has_fpu(&vcpu->arch) ||
1469 vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1471 return EMULATE_FAIL;
1477 /* other coprocessors not handled */
1485 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1496 * kvm_trap_vz_handle_msa_disabled() - Guest used MSA while disabled in root.
1497 * @vcpu: Virtual CPU context.
1499 * Handle when the guest attempts to use MSA when it is disabled in the root
1502 static int kvm_trap_vz_handle_msa_disabled(struct kvm_vcpu *vcpu)
1504 struct kvm_run *run = vcpu->run;
1507 * If MSA not present or not exposed to guest or FR=0, the MSA operation
1508 * should have been treated as a reserved instruction!
1509 * Same if CU1=1, FR=0.
1510 * If MSA already in use, we shouldn't get this at all.
1512 if (!kvm_mips_guest_has_msa(&vcpu->arch) ||
1513 (read_gc0_status() & (ST0_CU1 | ST0_FR)) == ST0_CU1 ||
1514 !(read_gc0_config5() & MIPS_CONF5_MSAEN) ||
1515 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1516 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1522 return RESUME_GUEST;
1525 static int kvm_trap_vz_handle_tlb_ld_miss(struct kvm_vcpu *vcpu)
1527 struct kvm_run *run = vcpu->run;
1528 u32 *opc = (u32 *) vcpu->arch.pc;
1529 u32 cause = vcpu->arch.host_cp0_cause;
1530 ulong badvaddr = vcpu->arch.host_cp0_badvaddr;
1531 union mips_instruction inst;
1532 enum emulation_result er = EMULATE_DONE;
1533 int err, ret = RESUME_GUEST;
1535 if (kvm_mips_handle_vz_root_tlb_fault(badvaddr, vcpu, false)) {
1536 /* A code fetch fault doesn't count as an MMIO */
1537 if (kvm_is_ifetch_fault(&vcpu->arch)) {
1538 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1542 /* Fetch the instruction */
1543 if (cause & CAUSEF_BD)
1545 err = kvm_get_badinstr(opc, vcpu, &inst.word);
1547 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1552 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1553 if (er == EMULATE_FAIL) {
1554 kvm_err("Guest Emulate Load from MMIO space failed: PC: %p, BadVaddr: %#lx\n",
1556 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1560 if (er == EMULATE_DONE) {
1562 } else if (er == EMULATE_DO_MMIO) {
1563 run->exit_reason = KVM_EXIT_MMIO;
1566 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1572 static int kvm_trap_vz_handle_tlb_st_miss(struct kvm_vcpu *vcpu)
1574 struct kvm_run *run = vcpu->run;
1575 u32 *opc = (u32 *) vcpu->arch.pc;
1576 u32 cause = vcpu->arch.host_cp0_cause;
1577 ulong badvaddr = vcpu->arch.host_cp0_badvaddr;
1578 union mips_instruction inst;
1579 enum emulation_result er = EMULATE_DONE;
1581 int ret = RESUME_GUEST;
1583 /* Just try the access again if we couldn't do the translation */
1584 if (kvm_vz_badvaddr_to_gpa(vcpu, badvaddr, &badvaddr))
1585 return RESUME_GUEST;
1586 vcpu->arch.host_cp0_badvaddr = badvaddr;
1588 if (kvm_mips_handle_vz_root_tlb_fault(badvaddr, vcpu, true)) {
1589 /* Fetch the instruction */
1590 if (cause & CAUSEF_BD)
1592 err = kvm_get_badinstr(opc, vcpu, &inst.word);
1594 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1599 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1600 if (er == EMULATE_FAIL) {
1601 kvm_err("Guest Emulate Store to MMIO space failed: PC: %p, BadVaddr: %#lx\n",
1603 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1607 if (er == EMULATE_DONE) {
1609 } else if (er == EMULATE_DO_MMIO) {
1610 run->exit_reason = KVM_EXIT_MMIO;
1613 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1619 static u64 kvm_vz_get_one_regs[] = {
1620 KVM_REG_MIPS_CP0_INDEX,
1621 KVM_REG_MIPS_CP0_ENTRYLO0,
1622 KVM_REG_MIPS_CP0_ENTRYLO1,
1623 KVM_REG_MIPS_CP0_CONTEXT,
1624 KVM_REG_MIPS_CP0_PAGEMASK,
1625 KVM_REG_MIPS_CP0_PAGEGRAIN,
1626 KVM_REG_MIPS_CP0_WIRED,
1627 KVM_REG_MIPS_CP0_HWRENA,
1628 KVM_REG_MIPS_CP0_BADVADDR,
1629 KVM_REG_MIPS_CP0_COUNT,
1630 KVM_REG_MIPS_CP0_ENTRYHI,
1631 KVM_REG_MIPS_CP0_COMPARE,
1632 KVM_REG_MIPS_CP0_STATUS,
1633 KVM_REG_MIPS_CP0_INTCTL,
1634 KVM_REG_MIPS_CP0_CAUSE,
1635 KVM_REG_MIPS_CP0_EPC,
1636 KVM_REG_MIPS_CP0_PRID,
1637 KVM_REG_MIPS_CP0_EBASE,
1638 KVM_REG_MIPS_CP0_CONFIG,
1639 KVM_REG_MIPS_CP0_CONFIG1,
1640 KVM_REG_MIPS_CP0_CONFIG2,
1641 KVM_REG_MIPS_CP0_CONFIG3,
1642 KVM_REG_MIPS_CP0_CONFIG4,
1643 KVM_REG_MIPS_CP0_CONFIG5,
1645 KVM_REG_MIPS_CP0_XCONTEXT,
1647 KVM_REG_MIPS_CP0_ERROREPC,
1649 KVM_REG_MIPS_COUNT_CTL,
1650 KVM_REG_MIPS_COUNT_RESUME,
1651 KVM_REG_MIPS_COUNT_HZ,
1654 static u64 kvm_vz_get_one_regs_contextconfig[] = {
1655 KVM_REG_MIPS_CP0_CONTEXTCONFIG,
1657 KVM_REG_MIPS_CP0_XCONTEXTCONFIG,
1661 static u64 kvm_vz_get_one_regs_segments[] = {
1662 KVM_REG_MIPS_CP0_SEGCTL0,
1663 KVM_REG_MIPS_CP0_SEGCTL1,
1664 KVM_REG_MIPS_CP0_SEGCTL2,
1667 static u64 kvm_vz_get_one_regs_htw[] = {
1668 KVM_REG_MIPS_CP0_PWBASE,
1669 KVM_REG_MIPS_CP0_PWFIELD,
1670 KVM_REG_MIPS_CP0_PWSIZE,
1671 KVM_REG_MIPS_CP0_PWCTL,
1674 static u64 kvm_vz_get_one_regs_kscratch[] = {
1675 KVM_REG_MIPS_CP0_KSCRATCH1,
1676 KVM_REG_MIPS_CP0_KSCRATCH2,
1677 KVM_REG_MIPS_CP0_KSCRATCH3,
1678 KVM_REG_MIPS_CP0_KSCRATCH4,
1679 KVM_REG_MIPS_CP0_KSCRATCH5,
1680 KVM_REG_MIPS_CP0_KSCRATCH6,
1683 static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu)
1687 ret = ARRAY_SIZE(kvm_vz_get_one_regs);
1688 if (cpu_guest_has_userlocal)
1690 if (cpu_guest_has_badinstr)
1692 if (cpu_guest_has_badinstrp)
1694 if (cpu_guest_has_contextconfig)
1695 ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
1696 if (cpu_guest_has_segments)
1697 ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
1698 if (cpu_guest_has_htw)
1699 ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
1700 if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar)
1701 ret += 1 + ARRAY_SIZE(vcpu->arch.maar);
1702 ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask);
1707 static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
1712 if (copy_to_user(indices, kvm_vz_get_one_regs,
1713 sizeof(kvm_vz_get_one_regs)))
1715 indices += ARRAY_SIZE(kvm_vz_get_one_regs);
1717 if (cpu_guest_has_userlocal) {
1718 index = KVM_REG_MIPS_CP0_USERLOCAL;
1719 if (copy_to_user(indices, &index, sizeof(index)))
1723 if (cpu_guest_has_badinstr) {
1724 index = KVM_REG_MIPS_CP0_BADINSTR;
1725 if (copy_to_user(indices, &index, sizeof(index)))
1729 if (cpu_guest_has_badinstrp) {
1730 index = KVM_REG_MIPS_CP0_BADINSTRP;
1731 if (copy_to_user(indices, &index, sizeof(index)))
1735 if (cpu_guest_has_contextconfig) {
1736 if (copy_to_user(indices, kvm_vz_get_one_regs_contextconfig,
1737 sizeof(kvm_vz_get_one_regs_contextconfig)))
1739 indices += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
1741 if (cpu_guest_has_segments) {
1742 if (copy_to_user(indices, kvm_vz_get_one_regs_segments,
1743 sizeof(kvm_vz_get_one_regs_segments)))
1745 indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
1747 if (cpu_guest_has_htw) {
1748 if (copy_to_user(indices, kvm_vz_get_one_regs_htw,
1749 sizeof(kvm_vz_get_one_regs_htw)))
1751 indices += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
1753 if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar) {
1754 for (i = 0; i < ARRAY_SIZE(vcpu->arch.maar); ++i) {
1755 index = KVM_REG_MIPS_CP0_MAAR(i);
1756 if (copy_to_user(indices, &index, sizeof(index)))
1761 index = KVM_REG_MIPS_CP0_MAARI;
1762 if (copy_to_user(indices, &index, sizeof(index)))
1766 for (i = 0; i < 6; ++i) {
1767 if (!cpu_guest_has_kscr(i + 2))
1770 if (copy_to_user(indices, &kvm_vz_get_one_regs_kscratch[i],
1771 sizeof(kvm_vz_get_one_regs_kscratch[i])))
1779 static inline s64 entrylo_kvm_to_user(unsigned long v)
1783 if (BITS_PER_LONG == 32) {
1785 * KVM API exposes 64-bit version of the register, so move the
1786 * RI/XI bits up into place.
1788 mask = MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI;
1790 ret |= ((s64)v & mask) << 32;
1795 static inline unsigned long entrylo_user_to_kvm(s64 v)
1797 unsigned long mask, ret = v;
1799 if (BITS_PER_LONG == 32) {
1801 * KVM API exposes 64-bit versiono of the register, so move the
1802 * RI/XI bits down into place.
1804 mask = MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI;
1806 ret |= (v >> 32) & mask;
1811 static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
1812 const struct kvm_one_reg *reg,
1815 struct mips_coproc *cop0 = vcpu->arch.cop0;
1819 case KVM_REG_MIPS_CP0_INDEX:
1820 *v = (long)read_gc0_index();
1822 case KVM_REG_MIPS_CP0_ENTRYLO0:
1823 *v = entrylo_kvm_to_user(read_gc0_entrylo0());
1825 case KVM_REG_MIPS_CP0_ENTRYLO1:
1826 *v = entrylo_kvm_to_user(read_gc0_entrylo1());
1828 case KVM_REG_MIPS_CP0_CONTEXT:
1829 *v = (long)read_gc0_context();
1831 case KVM_REG_MIPS_CP0_CONTEXTCONFIG:
1832 if (!cpu_guest_has_contextconfig)
1834 *v = read_gc0_contextconfig();
1836 case KVM_REG_MIPS_CP0_USERLOCAL:
1837 if (!cpu_guest_has_userlocal)
1839 *v = read_gc0_userlocal();
1842 case KVM_REG_MIPS_CP0_XCONTEXTCONFIG:
1843 if (!cpu_guest_has_contextconfig)
1845 *v = read_gc0_xcontextconfig();
1848 case KVM_REG_MIPS_CP0_PAGEMASK:
1849 *v = (long)read_gc0_pagemask();
1851 case KVM_REG_MIPS_CP0_PAGEGRAIN:
1852 *v = (long)read_gc0_pagegrain();
1854 case KVM_REG_MIPS_CP0_SEGCTL0:
1855 if (!cpu_guest_has_segments)
1857 *v = read_gc0_segctl0();
1859 case KVM_REG_MIPS_CP0_SEGCTL1:
1860 if (!cpu_guest_has_segments)
1862 *v = read_gc0_segctl1();
1864 case KVM_REG_MIPS_CP0_SEGCTL2:
1865 if (!cpu_guest_has_segments)
1867 *v = read_gc0_segctl2();
1869 case KVM_REG_MIPS_CP0_PWBASE:
1870 if (!cpu_guest_has_htw)
1872 *v = read_gc0_pwbase();
1874 case KVM_REG_MIPS_CP0_PWFIELD:
1875 if (!cpu_guest_has_htw)
1877 *v = read_gc0_pwfield();
1879 case KVM_REG_MIPS_CP0_PWSIZE:
1880 if (!cpu_guest_has_htw)
1882 *v = read_gc0_pwsize();
1884 case KVM_REG_MIPS_CP0_WIRED:
1885 *v = (long)read_gc0_wired();
1887 case KVM_REG_MIPS_CP0_PWCTL:
1888 if (!cpu_guest_has_htw)
1890 *v = read_gc0_pwctl();
1892 case KVM_REG_MIPS_CP0_HWRENA:
1893 *v = (long)read_gc0_hwrena();
1895 case KVM_REG_MIPS_CP0_BADVADDR:
1896 *v = (long)read_gc0_badvaddr();
1898 case KVM_REG_MIPS_CP0_BADINSTR:
1899 if (!cpu_guest_has_badinstr)
1901 *v = read_gc0_badinstr();
1903 case KVM_REG_MIPS_CP0_BADINSTRP:
1904 if (!cpu_guest_has_badinstrp)
1906 *v = read_gc0_badinstrp();
1908 case KVM_REG_MIPS_CP0_COUNT:
1909 *v = kvm_mips_read_count(vcpu);
1911 case KVM_REG_MIPS_CP0_ENTRYHI:
1912 *v = (long)read_gc0_entryhi();
1914 case KVM_REG_MIPS_CP0_COMPARE:
1915 *v = (long)read_gc0_compare();
1917 case KVM_REG_MIPS_CP0_STATUS:
1918 *v = (long)read_gc0_status();
1920 case KVM_REG_MIPS_CP0_INTCTL:
1921 *v = read_gc0_intctl();
1923 case KVM_REG_MIPS_CP0_CAUSE:
1924 *v = (long)read_gc0_cause();
1926 case KVM_REG_MIPS_CP0_EPC:
1927 *v = (long)read_gc0_epc();
1929 case KVM_REG_MIPS_CP0_PRID:
1930 *v = (long)kvm_read_c0_guest_prid(cop0);
1932 case KVM_REG_MIPS_CP0_EBASE:
1933 *v = kvm_vz_read_gc0_ebase();
1935 case KVM_REG_MIPS_CP0_CONFIG:
1936 *v = read_gc0_config();
1938 case KVM_REG_MIPS_CP0_CONFIG1:
1939 if (!cpu_guest_has_conf1)
1941 *v = read_gc0_config1();
1943 case KVM_REG_MIPS_CP0_CONFIG2:
1944 if (!cpu_guest_has_conf2)
1946 *v = read_gc0_config2();
1948 case KVM_REG_MIPS_CP0_CONFIG3:
1949 if (!cpu_guest_has_conf3)
1951 *v = read_gc0_config3();
1953 case KVM_REG_MIPS_CP0_CONFIG4:
1954 if (!cpu_guest_has_conf4)
1956 *v = read_gc0_config4();
1958 case KVM_REG_MIPS_CP0_CONFIG5:
1959 if (!cpu_guest_has_conf5)
1961 *v = read_gc0_config5();
1963 case KVM_REG_MIPS_CP0_MAAR(0) ... KVM_REG_MIPS_CP0_MAAR(0x3f):
1964 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
1966 idx = reg->id - KVM_REG_MIPS_CP0_MAAR(0);
1967 if (idx >= ARRAY_SIZE(vcpu->arch.maar))
1969 *v = vcpu->arch.maar[idx];
1971 case KVM_REG_MIPS_CP0_MAARI:
1972 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
1974 *v = kvm_read_sw_gc0_maari(vcpu->arch.cop0);
1977 case KVM_REG_MIPS_CP0_XCONTEXT:
1978 *v = read_gc0_xcontext();
1981 case KVM_REG_MIPS_CP0_ERROREPC:
1982 *v = (long)read_gc0_errorepc();
1984 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
1985 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
1986 if (!cpu_guest_has_kscr(idx))
1990 *v = (long)read_gc0_kscratch1();
1993 *v = (long)read_gc0_kscratch2();
1996 *v = (long)read_gc0_kscratch3();
1999 *v = (long)read_gc0_kscratch4();
2002 *v = (long)read_gc0_kscratch5();
2005 *v = (long)read_gc0_kscratch6();
2009 case KVM_REG_MIPS_COUNT_CTL:
2010 *v = vcpu->arch.count_ctl;
2012 case KVM_REG_MIPS_COUNT_RESUME:
2013 *v = ktime_to_ns(vcpu->arch.count_resume);
2015 case KVM_REG_MIPS_COUNT_HZ:
2016 *v = vcpu->arch.count_hz;
2024 static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
2025 const struct kvm_one_reg *reg,
2028 struct mips_coproc *cop0 = vcpu->arch.cop0;
2031 unsigned int cur, change;
2034 case KVM_REG_MIPS_CP0_INDEX:
2037 case KVM_REG_MIPS_CP0_ENTRYLO0:
2038 write_gc0_entrylo0(entrylo_user_to_kvm(v));
2040 case KVM_REG_MIPS_CP0_ENTRYLO1:
2041 write_gc0_entrylo1(entrylo_user_to_kvm(v));
2043 case KVM_REG_MIPS_CP0_CONTEXT:
2044 write_gc0_context(v);
2046 case KVM_REG_MIPS_CP0_CONTEXTCONFIG:
2047 if (!cpu_guest_has_contextconfig)
2049 write_gc0_contextconfig(v);
2051 case KVM_REG_MIPS_CP0_USERLOCAL:
2052 if (!cpu_guest_has_userlocal)
2054 write_gc0_userlocal(v);
2057 case KVM_REG_MIPS_CP0_XCONTEXTCONFIG:
2058 if (!cpu_guest_has_contextconfig)
2060 write_gc0_xcontextconfig(v);
2063 case KVM_REG_MIPS_CP0_PAGEMASK:
2064 write_gc0_pagemask(v);
2066 case KVM_REG_MIPS_CP0_PAGEGRAIN:
2067 write_gc0_pagegrain(v);
2069 case KVM_REG_MIPS_CP0_SEGCTL0:
2070 if (!cpu_guest_has_segments)
2072 write_gc0_segctl0(v);
2074 case KVM_REG_MIPS_CP0_SEGCTL1:
2075 if (!cpu_guest_has_segments)
2077 write_gc0_segctl1(v);
2079 case KVM_REG_MIPS_CP0_SEGCTL2:
2080 if (!cpu_guest_has_segments)
2082 write_gc0_segctl2(v);
2084 case KVM_REG_MIPS_CP0_PWBASE:
2085 if (!cpu_guest_has_htw)
2087 write_gc0_pwbase(v);
2089 case KVM_REG_MIPS_CP0_PWFIELD:
2090 if (!cpu_guest_has_htw)
2092 write_gc0_pwfield(v);
2094 case KVM_REG_MIPS_CP0_PWSIZE:
2095 if (!cpu_guest_has_htw)
2097 write_gc0_pwsize(v);
2099 case KVM_REG_MIPS_CP0_WIRED:
2100 change_gc0_wired(MIPSR6_WIRED_WIRED, v);
2102 case KVM_REG_MIPS_CP0_PWCTL:
2103 if (!cpu_guest_has_htw)
2107 case KVM_REG_MIPS_CP0_HWRENA:
2108 write_gc0_hwrena(v);
2110 case KVM_REG_MIPS_CP0_BADVADDR:
2111 write_gc0_badvaddr(v);
2113 case KVM_REG_MIPS_CP0_BADINSTR:
2114 if (!cpu_guest_has_badinstr)
2116 write_gc0_badinstr(v);
2118 case KVM_REG_MIPS_CP0_BADINSTRP:
2119 if (!cpu_guest_has_badinstrp)
2121 write_gc0_badinstrp(v);
2123 case KVM_REG_MIPS_CP0_COUNT:
2124 kvm_mips_write_count(vcpu, v);
2126 case KVM_REG_MIPS_CP0_ENTRYHI:
2127 write_gc0_entryhi(v);
2129 case KVM_REG_MIPS_CP0_COMPARE:
2130 kvm_mips_write_compare(vcpu, v, false);
2132 case KVM_REG_MIPS_CP0_STATUS:
2133 write_gc0_status(v);
2135 case KVM_REG_MIPS_CP0_INTCTL:
2136 write_gc0_intctl(v);
2138 case KVM_REG_MIPS_CP0_CAUSE:
2140 * If the timer is stopped or started (DC bit) it must look
2141 * atomic with changes to the timer interrupt pending bit (TI).
2142 * A timer interrupt should not happen in between.
2144 if ((read_gc0_cause() ^ v) & CAUSEF_DC) {
2145 if (v & CAUSEF_DC) {
2146 /* disable timer first */
2147 kvm_mips_count_disable_cause(vcpu);
2148 change_gc0_cause((u32)~CAUSEF_DC, v);
2150 /* enable timer last */
2151 change_gc0_cause((u32)~CAUSEF_DC, v);
2152 kvm_mips_count_enable_cause(vcpu);
2158 case KVM_REG_MIPS_CP0_EPC:
2161 case KVM_REG_MIPS_CP0_PRID:
2162 kvm_write_c0_guest_prid(cop0, v);
2164 case KVM_REG_MIPS_CP0_EBASE:
2165 kvm_vz_write_gc0_ebase(v);
2167 case KVM_REG_MIPS_CP0_CONFIG:
2168 cur = read_gc0_config();
2169 change = (cur ^ v) & kvm_vz_config_user_wrmask(vcpu);
2172 write_gc0_config(v);
2175 case KVM_REG_MIPS_CP0_CONFIG1:
2176 if (!cpu_guest_has_conf1)
2178 cur = read_gc0_config1();
2179 change = (cur ^ v) & kvm_vz_config1_user_wrmask(vcpu);
2182 write_gc0_config1(v);
2185 case KVM_REG_MIPS_CP0_CONFIG2:
2186 if (!cpu_guest_has_conf2)
2188 cur = read_gc0_config2();
2189 change = (cur ^ v) & kvm_vz_config2_user_wrmask(vcpu);
2192 write_gc0_config2(v);
2195 case KVM_REG_MIPS_CP0_CONFIG3:
2196 if (!cpu_guest_has_conf3)
2198 cur = read_gc0_config3();
2199 change = (cur ^ v) & kvm_vz_config3_user_wrmask(vcpu);
2202 write_gc0_config3(v);
2205 case KVM_REG_MIPS_CP0_CONFIG4:
2206 if (!cpu_guest_has_conf4)
2208 cur = read_gc0_config4();
2209 change = (cur ^ v) & kvm_vz_config4_user_wrmask(vcpu);
2212 write_gc0_config4(v);
2215 case KVM_REG_MIPS_CP0_CONFIG5:
2216 if (!cpu_guest_has_conf5)
2218 cur = read_gc0_config5();
2219 change = (cur ^ v) & kvm_vz_config5_user_wrmask(vcpu);
2222 write_gc0_config5(v);
2225 case KVM_REG_MIPS_CP0_MAAR(0) ... KVM_REG_MIPS_CP0_MAAR(0x3f):
2226 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
2228 idx = reg->id - KVM_REG_MIPS_CP0_MAAR(0);
2229 if (idx >= ARRAY_SIZE(vcpu->arch.maar))
2231 vcpu->arch.maar[idx] = mips_process_maar(dmtc_op, v);
2233 case KVM_REG_MIPS_CP0_MAARI:
2234 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
2236 kvm_write_maari(vcpu, v);
2239 case KVM_REG_MIPS_CP0_XCONTEXT:
2240 write_gc0_xcontext(v);
2243 case KVM_REG_MIPS_CP0_ERROREPC:
2244 write_gc0_errorepc(v);
2246 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
2247 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
2248 if (!cpu_guest_has_kscr(idx))
2252 write_gc0_kscratch1(v);
2255 write_gc0_kscratch2(v);
2258 write_gc0_kscratch3(v);
2261 write_gc0_kscratch4(v);
2264 write_gc0_kscratch5(v);
2267 write_gc0_kscratch6(v);
2271 case KVM_REG_MIPS_COUNT_CTL:
2272 ret = kvm_mips_set_count_ctl(vcpu, v);
2274 case KVM_REG_MIPS_COUNT_RESUME:
2275 ret = kvm_mips_set_count_resume(vcpu, v);
2277 case KVM_REG_MIPS_COUNT_HZ:
2278 ret = kvm_mips_set_count_hz(vcpu, v);
2286 #define guestid_cache(cpu) (cpu_data[cpu].guestid_cache)
2287 static void kvm_vz_get_new_guestid(unsigned long cpu, struct kvm_vcpu *vcpu)
2289 unsigned long guestid = guestid_cache(cpu);
2291 if (!(++guestid & GUESTID_MASK)) {
2292 if (cpu_has_vtag_icache)
2295 if (!guestid) /* fix version if needed */
2296 guestid = GUESTID_FIRST_VERSION;
2298 ++guestid; /* guestid 0 reserved for root */
2300 /* start new guestid cycle */
2301 kvm_vz_local_flush_roottlb_all_guests();
2302 kvm_vz_local_flush_guesttlb_all();
2305 guestid_cache(cpu) = guestid;
2308 /* Returns 1 if the guest TLB may be clobbered */
2309 static int kvm_vz_check_requests(struct kvm_vcpu *vcpu, int cpu)
2314 if (!vcpu->requests)
2317 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
2318 if (cpu_has_guestid) {
2319 /* Drop all GuestIDs for this VCPU */
2320 for_each_possible_cpu(i)
2321 vcpu->arch.vzguestid[i] = 0;
2322 /* This will clobber guest TLB contents too */
2326 * For Root ASID Dealias (RAD) we don't do anything here, but we
2327 * still need the request to ensure we recheck asid_flush_mask.
2328 * We can still return 0 as only the root TLB will be affected
2329 * by a root ASID flush.
2336 static void kvm_vz_vcpu_save_wired(struct kvm_vcpu *vcpu)
2338 unsigned int wired = read_gc0_wired();
2339 struct kvm_mips_tlb *tlbs;
2342 /* Expand the wired TLB array if necessary */
2343 wired &= MIPSR6_WIRED_WIRED;
2344 if (wired > vcpu->arch.wired_tlb_limit) {
2345 tlbs = krealloc(vcpu->arch.wired_tlb, wired *
2346 sizeof(*vcpu->arch.wired_tlb), GFP_ATOMIC);
2347 if (WARN_ON(!tlbs)) {
2348 /* Save whatever we can */
2349 wired = vcpu->arch.wired_tlb_limit;
2351 vcpu->arch.wired_tlb = tlbs;
2352 vcpu->arch.wired_tlb_limit = wired;
2357 /* Save wired entries from the guest TLB */
2358 kvm_vz_save_guesttlb(vcpu->arch.wired_tlb, 0, wired);
2359 /* Invalidate any dropped entries since last time */
2360 for (i = wired; i < vcpu->arch.wired_tlb_used; ++i) {
2361 vcpu->arch.wired_tlb[i].tlb_hi = UNIQUE_GUEST_ENTRYHI(i);
2362 vcpu->arch.wired_tlb[i].tlb_lo[0] = 0;
2363 vcpu->arch.wired_tlb[i].tlb_lo[1] = 0;
2364 vcpu->arch.wired_tlb[i].tlb_mask = 0;
2366 vcpu->arch.wired_tlb_used = wired;
2369 static void kvm_vz_vcpu_load_wired(struct kvm_vcpu *vcpu)
2371 /* Load wired entries into the guest TLB */
2372 if (vcpu->arch.wired_tlb)
2373 kvm_vz_load_guesttlb(vcpu->arch.wired_tlb, 0,
2374 vcpu->arch.wired_tlb_used);
2377 static void kvm_vz_vcpu_load_tlb(struct kvm_vcpu *vcpu, int cpu)
2379 struct kvm *kvm = vcpu->kvm;
2380 struct mm_struct *gpa_mm = &kvm->arch.gpa_mm;
2384 * Are we entering guest context on a different CPU to last time?
2385 * If so, the VCPU's guest TLB state on this CPU may be stale.
2387 migrated = (vcpu->arch.last_exec_cpu != cpu);
2388 vcpu->arch.last_exec_cpu = cpu;
2391 * A vcpu's GuestID is set in GuestCtl1.ID when the vcpu is loaded and
2392 * remains set until another vcpu is loaded in. As a rule GuestRID
2393 * remains zeroed when in root context unless the kernel is busy
2394 * manipulating guest tlb entries.
2396 if (cpu_has_guestid) {
2398 * Check if our GuestID is of an older version and thus invalid.
2400 * We also discard the stored GuestID if we've executed on
2401 * another CPU, as the guest mappings may have changed without
2402 * hypervisor knowledge.
2405 (vcpu->arch.vzguestid[cpu] ^ guestid_cache(cpu)) &
2406 GUESTID_VERSION_MASK) {
2407 kvm_vz_get_new_guestid(cpu, vcpu);
2408 vcpu->arch.vzguestid[cpu] = guestid_cache(cpu);
2409 trace_kvm_guestid_change(vcpu,
2410 vcpu->arch.vzguestid[cpu]);
2413 /* Restore GuestID */
2414 change_c0_guestctl1(GUESTID_MASK, vcpu->arch.vzguestid[cpu]);
2417 * The Guest TLB only stores a single guest's TLB state, so
2418 * flush it if another VCPU has executed on this CPU.
2420 * We also flush if we've executed on another CPU, as the guest
2421 * mappings may have changed without hypervisor knowledge.
2423 if (migrated || last_exec_vcpu[cpu] != vcpu)
2424 kvm_vz_local_flush_guesttlb_all();
2425 last_exec_vcpu[cpu] = vcpu;
2428 * Root ASID dealiases guest GPA mappings in the root TLB.
2429 * Allocate new root ASID if needed.
2431 if (cpumask_test_and_clear_cpu(cpu, &kvm->arch.asid_flush_mask)
2432 || (cpu_context(cpu, gpa_mm) ^ asid_cache(cpu)) &
2433 asid_version_mask(cpu))
2434 get_new_mmu_context(gpa_mm, cpu);
2438 static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2440 struct mips_coproc *cop0 = vcpu->arch.cop0;
2444 * Have we migrated to a different CPU?
2445 * If so, any old guest TLB state may be stale.
2447 migrated = (vcpu->arch.last_sched_cpu != cpu);
2450 * Was this the last VCPU to run on this CPU?
2451 * If not, any old guest state from this VCPU will have been clobbered.
2453 all = migrated || (last_vcpu[cpu] != vcpu);
2454 last_vcpu[cpu] = vcpu;
2457 * Restore CP0_Wired unconditionally as we clear it after use, and
2458 * restore wired guest TLB entries (while in guest context).
2460 kvm_restore_gc0_wired(cop0);
2461 if (current->flags & PF_VCPU) {
2463 kvm_vz_vcpu_load_tlb(vcpu, cpu);
2464 kvm_vz_vcpu_load_wired(vcpu);
2468 * Restore timer state regardless, as e.g. Cause.TI can change over time
2469 * if left unmaintained.
2471 kvm_vz_restore_timer(vcpu);
2473 /* Set MC bit if we want to trace guest mode changes */
2474 if (kvm_trace_guest_mode_change)
2475 set_c0_guestctl0(MIPS_GCTL0_MC);
2477 clear_c0_guestctl0(MIPS_GCTL0_MC);
2479 /* Don't bother restoring registers multiple times unless necessary */
2484 * Restore config registers first, as some implementations restrict
2485 * writes to other registers when the corresponding feature bits aren't
2486 * set. For example Status.CU1 cannot be set unless Config1.FP is set.
2488 kvm_restore_gc0_config(cop0);
2489 if (cpu_guest_has_conf1)
2490 kvm_restore_gc0_config1(cop0);
2491 if (cpu_guest_has_conf2)
2492 kvm_restore_gc0_config2(cop0);
2493 if (cpu_guest_has_conf3)
2494 kvm_restore_gc0_config3(cop0);
2495 if (cpu_guest_has_conf4)
2496 kvm_restore_gc0_config4(cop0);
2497 if (cpu_guest_has_conf5)
2498 kvm_restore_gc0_config5(cop0);
2499 if (cpu_guest_has_conf6)
2500 kvm_restore_gc0_config6(cop0);
2501 if (cpu_guest_has_conf7)
2502 kvm_restore_gc0_config7(cop0);
2504 kvm_restore_gc0_index(cop0);
2505 kvm_restore_gc0_entrylo0(cop0);
2506 kvm_restore_gc0_entrylo1(cop0);
2507 kvm_restore_gc0_context(cop0);
2508 if (cpu_guest_has_contextconfig)
2509 kvm_restore_gc0_contextconfig(cop0);
2511 kvm_restore_gc0_xcontext(cop0);
2512 if (cpu_guest_has_contextconfig)
2513 kvm_restore_gc0_xcontextconfig(cop0);
2515 kvm_restore_gc0_pagemask(cop0);
2516 kvm_restore_gc0_pagegrain(cop0);
2517 kvm_restore_gc0_hwrena(cop0);
2518 kvm_restore_gc0_badvaddr(cop0);
2519 kvm_restore_gc0_entryhi(cop0);
2520 kvm_restore_gc0_status(cop0);
2521 kvm_restore_gc0_intctl(cop0);
2522 kvm_restore_gc0_epc(cop0);
2523 kvm_vz_write_gc0_ebase(kvm_read_sw_gc0_ebase(cop0));
2524 if (cpu_guest_has_userlocal)
2525 kvm_restore_gc0_userlocal(cop0);
2527 kvm_restore_gc0_errorepc(cop0);
2529 /* restore KScratch registers if enabled in guest */
2530 if (cpu_guest_has_conf4) {
2531 if (cpu_guest_has_kscr(2))
2532 kvm_restore_gc0_kscratch1(cop0);
2533 if (cpu_guest_has_kscr(3))
2534 kvm_restore_gc0_kscratch2(cop0);
2535 if (cpu_guest_has_kscr(4))
2536 kvm_restore_gc0_kscratch3(cop0);
2537 if (cpu_guest_has_kscr(5))
2538 kvm_restore_gc0_kscratch4(cop0);
2539 if (cpu_guest_has_kscr(6))
2540 kvm_restore_gc0_kscratch5(cop0);
2541 if (cpu_guest_has_kscr(7))
2542 kvm_restore_gc0_kscratch6(cop0);
2545 if (cpu_guest_has_badinstr)
2546 kvm_restore_gc0_badinstr(cop0);
2547 if (cpu_guest_has_badinstrp)
2548 kvm_restore_gc0_badinstrp(cop0);
2550 if (cpu_guest_has_segments) {
2551 kvm_restore_gc0_segctl0(cop0);
2552 kvm_restore_gc0_segctl1(cop0);
2553 kvm_restore_gc0_segctl2(cop0);
2556 /* restore HTW registers */
2557 if (cpu_guest_has_htw) {
2558 kvm_restore_gc0_pwbase(cop0);
2559 kvm_restore_gc0_pwfield(cop0);
2560 kvm_restore_gc0_pwsize(cop0);
2561 kvm_restore_gc0_pwctl(cop0);
2564 /* restore Root.GuestCtl2 from unused Guest guestctl2 register */
2565 if (cpu_has_guestctl2)
2567 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL]);
2570 * We should clear linked load bit to break interrupted atomics. This
2571 * prevents a SC on the next VCPU from succeeding by matching a LL on
2572 * the previous VCPU.
2574 if (cpu_guest_has_rw_llb)
2575 write_gc0_lladdr(0);
2580 static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu)
2582 struct mips_coproc *cop0 = vcpu->arch.cop0;
2584 if (current->flags & PF_VCPU)
2585 kvm_vz_vcpu_save_wired(vcpu);
2589 kvm_save_gc0_index(cop0);
2590 kvm_save_gc0_entrylo0(cop0);
2591 kvm_save_gc0_entrylo1(cop0);
2592 kvm_save_gc0_context(cop0);
2593 if (cpu_guest_has_contextconfig)
2594 kvm_save_gc0_contextconfig(cop0);
2596 kvm_save_gc0_xcontext(cop0);
2597 if (cpu_guest_has_contextconfig)
2598 kvm_save_gc0_xcontextconfig(cop0);
2600 kvm_save_gc0_pagemask(cop0);
2601 kvm_save_gc0_pagegrain(cop0);
2602 kvm_save_gc0_wired(cop0);
2603 /* allow wired TLB entries to be overwritten */
2604 clear_gc0_wired(MIPSR6_WIRED_WIRED);
2605 kvm_save_gc0_hwrena(cop0);
2606 kvm_save_gc0_badvaddr(cop0);
2607 kvm_save_gc0_entryhi(cop0);
2608 kvm_save_gc0_status(cop0);
2609 kvm_save_gc0_intctl(cop0);
2610 kvm_save_gc0_epc(cop0);
2611 kvm_write_sw_gc0_ebase(cop0, kvm_vz_read_gc0_ebase());
2612 if (cpu_guest_has_userlocal)
2613 kvm_save_gc0_userlocal(cop0);
2615 /* only save implemented config registers */
2616 kvm_save_gc0_config(cop0);
2617 if (cpu_guest_has_conf1)
2618 kvm_save_gc0_config1(cop0);
2619 if (cpu_guest_has_conf2)
2620 kvm_save_gc0_config2(cop0);
2621 if (cpu_guest_has_conf3)
2622 kvm_save_gc0_config3(cop0);
2623 if (cpu_guest_has_conf4)
2624 kvm_save_gc0_config4(cop0);
2625 if (cpu_guest_has_conf5)
2626 kvm_save_gc0_config5(cop0);
2627 if (cpu_guest_has_conf6)
2628 kvm_save_gc0_config6(cop0);
2629 if (cpu_guest_has_conf7)
2630 kvm_save_gc0_config7(cop0);
2632 kvm_save_gc0_errorepc(cop0);
2634 /* save KScratch registers if enabled in guest */
2635 if (cpu_guest_has_conf4) {
2636 if (cpu_guest_has_kscr(2))
2637 kvm_save_gc0_kscratch1(cop0);
2638 if (cpu_guest_has_kscr(3))
2639 kvm_save_gc0_kscratch2(cop0);
2640 if (cpu_guest_has_kscr(4))
2641 kvm_save_gc0_kscratch3(cop0);
2642 if (cpu_guest_has_kscr(5))
2643 kvm_save_gc0_kscratch4(cop0);
2644 if (cpu_guest_has_kscr(6))
2645 kvm_save_gc0_kscratch5(cop0);
2646 if (cpu_guest_has_kscr(7))
2647 kvm_save_gc0_kscratch6(cop0);
2650 if (cpu_guest_has_badinstr)
2651 kvm_save_gc0_badinstr(cop0);
2652 if (cpu_guest_has_badinstrp)
2653 kvm_save_gc0_badinstrp(cop0);
2655 if (cpu_guest_has_segments) {
2656 kvm_save_gc0_segctl0(cop0);
2657 kvm_save_gc0_segctl1(cop0);
2658 kvm_save_gc0_segctl2(cop0);
2661 /* save HTW registers if enabled in guest */
2662 if (cpu_guest_has_htw &&
2663 kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) {
2664 kvm_save_gc0_pwbase(cop0);
2665 kvm_save_gc0_pwfield(cop0);
2666 kvm_save_gc0_pwsize(cop0);
2667 kvm_save_gc0_pwctl(cop0);
2670 kvm_vz_save_timer(vcpu);
2672 /* save Root.GuestCtl2 in unused Guest guestctl2 register */
2673 if (cpu_has_guestctl2)
2674 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] =
2675 read_c0_guestctl2();
2681 * kvm_vz_resize_guest_vtlb() - Attempt to resize guest VTLB.
2682 * @size: Number of guest VTLB entries (0 < @size <= root VTLB entries).
2684 * Attempt to resize the guest VTLB by writing guest Config registers. This is
2685 * necessary for cores with a shared root/guest TLB to avoid overlap with wired
2686 * entries in the root VTLB.
2688 * Returns: The resulting guest VTLB size.
2690 static unsigned int kvm_vz_resize_guest_vtlb(unsigned int size)
2692 unsigned int config4 = 0, ret = 0, limit;
2694 /* Write MMUSize - 1 into guest Config registers */
2695 if (cpu_guest_has_conf1)
2696 change_gc0_config1(MIPS_CONF1_TLBS,
2697 (size - 1) << MIPS_CONF1_TLBS_SHIFT);
2698 if (cpu_guest_has_conf4) {
2699 config4 = read_gc0_config4();
2700 if (cpu_has_mips_r6 || (config4 & MIPS_CONF4_MMUEXTDEF) ==
2701 MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT) {
2702 config4 &= ~MIPS_CONF4_VTLBSIZEEXT;
2703 config4 |= ((size - 1) >> MIPS_CONF1_TLBS_SIZE) <<
2704 MIPS_CONF4_VTLBSIZEEXT_SHIFT;
2705 } else if ((config4 & MIPS_CONF4_MMUEXTDEF) ==
2706 MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT) {
2707 config4 &= ~MIPS_CONF4_MMUSIZEEXT;
2708 config4 |= ((size - 1) >> MIPS_CONF1_TLBS_SIZE) <<
2709 MIPS_CONF4_MMUSIZEEXT_SHIFT;
2711 write_gc0_config4(config4);
2715 * Set Guest.Wired.Limit = 0 (no limit up to Guest.MMUSize-1), unless it
2716 * would exceed Root.Wired.Limit (clearing Guest.Wired.Wired so write
2719 if (cpu_has_mips_r6) {
2720 limit = (read_c0_wired() & MIPSR6_WIRED_LIMIT) >>
2721 MIPSR6_WIRED_LIMIT_SHIFT;
2722 if (size - 1 <= limit)
2724 write_gc0_wired(limit << MIPSR6_WIRED_LIMIT_SHIFT);
2727 /* Read back MMUSize - 1 */
2728 back_to_back_c0_hazard();
2729 if (cpu_guest_has_conf1)
2730 ret = (read_gc0_config1() & MIPS_CONF1_TLBS) >>
2731 MIPS_CONF1_TLBS_SHIFT;
2733 if (cpu_has_mips_r6 || (config4 & MIPS_CONF4_MMUEXTDEF) ==
2734 MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT)
2735 ret |= ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
2736 MIPS_CONF4_VTLBSIZEEXT_SHIFT) <<
2737 MIPS_CONF1_TLBS_SIZE;
2738 else if ((config4 & MIPS_CONF4_MMUEXTDEF) ==
2739 MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT)
2740 ret |= ((config4 & MIPS_CONF4_MMUSIZEEXT) >>
2741 MIPS_CONF4_MMUSIZEEXT_SHIFT) <<
2742 MIPS_CONF1_TLBS_SIZE;
2747 static int kvm_vz_hardware_enable(void)
2749 unsigned int mmu_size, guest_mmu_size, ftlb_size;
2752 * ImgTec cores tend to use a shared root/guest TLB. To avoid overlap of
2753 * root wired and guest entries, the guest TLB may need resizing.
2755 mmu_size = current_cpu_data.tlbsizevtlb;
2756 ftlb_size = current_cpu_data.tlbsize - mmu_size;
2758 /* Try switching to maximum guest VTLB size for flush */
2759 guest_mmu_size = kvm_vz_resize_guest_vtlb(mmu_size);
2760 current_cpu_data.guest.tlbsize = guest_mmu_size + ftlb_size;
2761 kvm_vz_local_flush_guesttlb_all();
2764 * Reduce to make space for root wired entries and at least 2 root
2765 * non-wired entries. This does assume that long-term wired entries
2766 * won't be added later.
2768 guest_mmu_size = mmu_size - num_wired_entries() - 2;
2769 guest_mmu_size = kvm_vz_resize_guest_vtlb(guest_mmu_size);
2770 current_cpu_data.guest.tlbsize = guest_mmu_size + ftlb_size;
2773 * Write the VTLB size, but if another CPU has already written, check it
2774 * matches or we won't provide a consistent view to the guest. If this
2775 * ever happens it suggests an asymmetric number of wired entries.
2777 if (cmpxchg(&kvm_vz_guest_vtlb_size, 0, guest_mmu_size) &&
2778 WARN(guest_mmu_size != kvm_vz_guest_vtlb_size,
2779 "Available guest VTLB size mismatch"))
2783 * Enable virtualization features granting guest direct control of
2785 * CP0=1: Guest coprocessor 0 context.
2786 * AT=Guest: Guest MMU.
2787 * CG=1: Hit (virtual address) CACHE operations (optional).
2788 * CF=1: Guest Config registers.
2789 * CGI=1: Indexed flush CACHE operations (optional).
2791 write_c0_guestctl0(MIPS_GCTL0_CP0 |
2792 (MIPS_GCTL0_AT_GUEST << MIPS_GCTL0_AT_SHIFT) |
2793 MIPS_GCTL0_CG | MIPS_GCTL0_CF);
2794 if (cpu_has_guestctl0ext)
2795 set_c0_guestctl0ext(MIPS_GCTL0EXT_CGI);
2797 if (cpu_has_guestid) {
2798 write_c0_guestctl1(0);
2799 kvm_vz_local_flush_roottlb_all_guests();
2801 GUESTID_MASK = current_cpu_data.guestid_mask;
2802 GUESTID_FIRST_VERSION = GUESTID_MASK + 1;
2803 GUESTID_VERSION_MASK = ~GUESTID_MASK;
2805 current_cpu_data.guestid_cache = GUESTID_FIRST_VERSION;
2808 /* clear any pending injected virtual guest interrupts */
2809 if (cpu_has_guestctl2)
2810 clear_c0_guestctl2(0x3f << 10);
2815 static void kvm_vz_hardware_disable(void)
2817 kvm_vz_local_flush_guesttlb_all();
2819 if (cpu_has_guestid) {
2820 write_c0_guestctl1(0);
2821 kvm_vz_local_flush_roottlb_all_guests();
2825 static int kvm_vz_check_extension(struct kvm *kvm, long ext)
2830 case KVM_CAP_MIPS_VZ:
2831 /* we wouldn't be here unless cpu_has_vz */
2835 case KVM_CAP_MIPS_64BIT:
2836 /* We support 64-bit registers/operations and addresses */
2848 static int kvm_vz_vcpu_init(struct kvm_vcpu *vcpu)
2852 for_each_possible_cpu(i)
2853 vcpu->arch.vzguestid[i] = 0;
2858 static void kvm_vz_vcpu_uninit(struct kvm_vcpu *vcpu)
2863 * If the VCPU is freed and reused as another VCPU, we don't want the
2864 * matching pointer wrongly hanging around in last_vcpu[] or
2867 for_each_possible_cpu(cpu) {
2868 if (last_vcpu[cpu] == vcpu)
2869 last_vcpu[cpu] = NULL;
2870 if (last_exec_vcpu[cpu] == vcpu)
2871 last_exec_vcpu[cpu] = NULL;
2875 static int kvm_vz_vcpu_setup(struct kvm_vcpu *vcpu)
2877 struct mips_coproc *cop0 = vcpu->arch.cop0;
2878 unsigned long count_hz = 100*1000*1000; /* default to 100 MHz */
2881 * Start off the timer at the same frequency as the host timer, but the
2882 * soft timer doesn't handle frequencies greater than 1GHz yet.
2884 if (mips_hpt_frequency && mips_hpt_frequency <= NSEC_PER_SEC)
2885 count_hz = mips_hpt_frequency;
2886 kvm_mips_init_count(vcpu, count_hz);
2889 * Initialize guest register state to valid architectural reset state.
2893 if (cpu_has_mips_r6)
2894 kvm_write_sw_gc0_pagegrain(cop0, PG_RIE | PG_XIE | PG_IEC);
2896 if (cpu_has_mips_r6)
2897 kvm_write_sw_gc0_wired(cop0,
2898 read_gc0_wired() & MIPSR6_WIRED_LIMIT);
2900 kvm_write_sw_gc0_status(cop0, ST0_BEV | ST0_ERL);
2901 if (cpu_has_mips_r6)
2902 kvm_change_sw_gc0_status(cop0, ST0_FR, read_gc0_status());
2904 kvm_write_sw_gc0_intctl(cop0, read_gc0_intctl() &
2905 (INTCTLF_IPFDC | INTCTLF_IPPCI | INTCTLF_IPTI));
2907 kvm_write_sw_gc0_prid(cop0, boot_cpu_data.processor_id);
2909 kvm_write_sw_gc0_ebase(cop0, (s32)0x80000000 | vcpu->vcpu_id);
2911 kvm_save_gc0_config(cop0);
2912 /* architecturally writable (e.g. from guest) */
2913 kvm_change_sw_gc0_config(cop0, CONF_CM_CMASK,
2914 _page_cachable_default >> _CACHE_SHIFT);
2915 /* architecturally read only, but maybe writable from root */
2916 kvm_change_sw_gc0_config(cop0, MIPS_CONF_MT, read_c0_config());
2917 if (cpu_guest_has_conf1) {
2918 kvm_set_sw_gc0_config(cop0, MIPS_CONF_M);
2920 kvm_save_gc0_config1(cop0);
2921 /* architecturally read only, but maybe writable from root */
2922 kvm_clear_sw_gc0_config1(cop0, MIPS_CONF1_C2 |
2929 if (cpu_guest_has_conf2) {
2930 kvm_set_sw_gc0_config1(cop0, MIPS_CONF_M);
2932 kvm_save_gc0_config2(cop0);
2934 if (cpu_guest_has_conf3) {
2935 kvm_set_sw_gc0_config2(cop0, MIPS_CONF_M);
2937 kvm_save_gc0_config3(cop0);
2938 /* architecturally writable (e.g. from guest) */
2939 kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_ISA_OE);
2940 /* architecturally read only, but maybe writable from root */
2941 kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_MSA |
2956 if (cpu_guest_has_conf4) {
2957 kvm_set_sw_gc0_config3(cop0, MIPS_CONF_M);
2959 kvm_save_gc0_config4(cop0);
2961 if (cpu_guest_has_conf5) {
2962 kvm_set_sw_gc0_config4(cop0, MIPS_CONF_M);
2964 kvm_save_gc0_config5(cop0);
2965 /* architecturally writable (e.g. from guest) */
2966 kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_K |
2973 /* architecturally read only, but maybe writable from root */
2974 kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP);
2977 if (cpu_guest_has_contextconfig) {
2979 kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0);
2981 /* XContextConfig */
2982 /* bits SEGBITS-13+3:4 set */
2983 kvm_write_sw_gc0_xcontextconfig(cop0,
2984 ((1ull << (cpu_vmbits - 13)) - 1) << 4);
2988 /* Implementation dependent, use the legacy layout */
2989 if (cpu_guest_has_segments) {
2990 /* SegCtl0, SegCtl1, SegCtl2 */
2991 kvm_write_sw_gc0_segctl0(cop0, 0x00200010);
2992 kvm_write_sw_gc0_segctl1(cop0, 0x00000002 |
2993 (_page_cachable_default >> _CACHE_SHIFT) <<
2994 (16 + MIPS_SEGCFG_C_SHIFT));
2995 kvm_write_sw_gc0_segctl2(cop0, 0x00380438);
2998 /* reset HTW registers */
2999 if (cpu_guest_has_htw && cpu_has_mips_r6) {
3001 kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302);
3003 kvm_write_sw_gc0_pwsize(cop0, 1 << MIPS_PWSIZE_PTW_SHIFT);
3006 /* start with no pending virtual guest interrupts */
3007 if (cpu_has_guestctl2)
3008 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0;
3010 /* Put PC at reset vector */
3011 vcpu->arch.pc = CKSEG1ADDR(0x1fc00000);
3016 static void kvm_vz_flush_shadow_all(struct kvm *kvm)
3018 if (cpu_has_guestid) {
3019 /* Flush GuestID for each VCPU individually */
3020 kvm_flush_remote_tlbs(kvm);
3023 * For each CPU there is a single GPA ASID used by all VCPUs in
3024 * the VM, so it doesn't make sense for the VCPUs to handle
3025 * invalidation of these ASIDs individually.
3027 * Instead mark all CPUs as needing ASID invalidation in
3028 * asid_flush_mask, and just use kvm_flush_remote_tlbs(kvm) to
3029 * kick any running VCPUs so they check asid_flush_mask.
3031 cpumask_setall(&kvm->arch.asid_flush_mask);
3032 kvm_flush_remote_tlbs(kvm);
3036 static void kvm_vz_flush_shadow_memslot(struct kvm *kvm,
3037 const struct kvm_memory_slot *slot)
3039 kvm_vz_flush_shadow_all(kvm);
3042 static void kvm_vz_vcpu_reenter(struct kvm_run *run, struct kvm_vcpu *vcpu)
3044 int cpu = smp_processor_id();
3045 int preserve_guest_tlb;
3047 preserve_guest_tlb = kvm_vz_check_requests(vcpu, cpu);
3049 if (preserve_guest_tlb)
3050 kvm_vz_vcpu_save_wired(vcpu);
3052 kvm_vz_vcpu_load_tlb(vcpu, cpu);
3054 if (preserve_guest_tlb)
3055 kvm_vz_vcpu_load_wired(vcpu);
3058 static int kvm_vz_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu)
3060 int cpu = smp_processor_id();
3063 kvm_vz_acquire_htimer(vcpu);
3064 /* Check if we have any exceptions/interrupts pending */
3065 kvm_mips_deliver_interrupts(vcpu, read_gc0_cause());
3067 kvm_vz_check_requests(vcpu, cpu);
3068 kvm_vz_vcpu_load_tlb(vcpu, cpu);
3069 kvm_vz_vcpu_load_wired(vcpu);
3071 r = vcpu->arch.vcpu_run(run, vcpu);
3073 kvm_vz_vcpu_save_wired(vcpu);
3078 static struct kvm_mips_callbacks kvm_vz_callbacks = {
3079 .handle_cop_unusable = kvm_trap_vz_handle_cop_unusable,
3080 .handle_tlb_mod = kvm_trap_vz_handle_tlb_st_miss,
3081 .handle_tlb_ld_miss = kvm_trap_vz_handle_tlb_ld_miss,
3082 .handle_tlb_st_miss = kvm_trap_vz_handle_tlb_st_miss,
3083 .handle_addr_err_st = kvm_trap_vz_no_handler,
3084 .handle_addr_err_ld = kvm_trap_vz_no_handler,
3085 .handle_syscall = kvm_trap_vz_no_handler,
3086 .handle_res_inst = kvm_trap_vz_no_handler,
3087 .handle_break = kvm_trap_vz_no_handler,
3088 .handle_msa_disabled = kvm_trap_vz_handle_msa_disabled,
3089 .handle_guest_exit = kvm_trap_vz_handle_guest_exit,
3091 .hardware_enable = kvm_vz_hardware_enable,
3092 .hardware_disable = kvm_vz_hardware_disable,
3093 .check_extension = kvm_vz_check_extension,
3094 .vcpu_init = kvm_vz_vcpu_init,
3095 .vcpu_uninit = kvm_vz_vcpu_uninit,
3096 .vcpu_setup = kvm_vz_vcpu_setup,
3097 .flush_shadow_all = kvm_vz_flush_shadow_all,
3098 .flush_shadow_memslot = kvm_vz_flush_shadow_memslot,
3099 .gva_to_gpa = kvm_vz_gva_to_gpa_cb,
3100 .queue_timer_int = kvm_vz_queue_timer_int_cb,
3101 .dequeue_timer_int = kvm_vz_dequeue_timer_int_cb,
3102 .queue_io_int = kvm_vz_queue_io_int_cb,
3103 .dequeue_io_int = kvm_vz_dequeue_io_int_cb,
3104 .irq_deliver = kvm_vz_irq_deliver_cb,
3105 .irq_clear = kvm_vz_irq_clear_cb,
3106 .num_regs = kvm_vz_num_regs,
3107 .copy_reg_indices = kvm_vz_copy_reg_indices,
3108 .get_one_reg = kvm_vz_get_one_reg,
3109 .set_one_reg = kvm_vz_set_one_reg,
3110 .vcpu_load = kvm_vz_vcpu_load,
3111 .vcpu_put = kvm_vz_vcpu_put,
3112 .vcpu_run = kvm_vz_vcpu_run,
3113 .vcpu_reenter = kvm_vz_vcpu_reenter,
3116 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks)
3122 * VZ requires at least 2 KScratch registers, so it should have been
3123 * possible to allocate pgd_reg.
3125 if (WARN(pgd_reg == -1,
3126 "pgd_reg not allocated even though cpu_has_vz\n"))
3129 pr_info("Starting KVM with MIPS VZ extensions\n");
3131 *install_callbacks = &kvm_vz_callbacks;