arch/mips/lantiq/xway/sysctrl.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
   7  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
   8  */
   9
  10 #include <linux/ioport.h>
  11 #include <linux/export.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/of_address.h>
  17
  18 #include <lantiq_soc.h>
  19
  20 #include "../clk.h"
  21 #include "../prom.h"
  22
  23 /* clock control register for legacy */
  24 #define CGU_IFCCR       0x0018
  25 #define CGU_IFCCR_VR9   0x0024
  26 /* system clock register for legacy */
  27 #define CGU_SYS         0x0010
  28 /* pci control register */
  29 #define CGU_PCICR       0x0034
  30 #define CGU_PCICR_VR9   0x0038
  31 /* ephy configuration register */
  32 #define CGU_EPHY        0x10
  33
  34 /* Legacy PMU register for ar9, ase, danube */
  35 /* power control register */
  36 #define PMU_PWDCR       0x1C
  37 /* power status register */
  38 #define PMU_PWDSR       0x20
  39 /* power control register */
  40 #define PMU_PWDCR1      0x24
  41 /* power status register */
  42 #define PMU_PWDSR1      0x28
  43 /* power control register */
  44 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  45 /* power status register */
  46 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  47
  48
  49 /* PMU register for ar10 and grx390 */
  50
  51 /* First register set */
  52 #define PMU_CLK_SR      0x20 /* status */
  53 #define PMU_CLK_CR_A    0x24 /* Enable */
  54 #define PMU_CLK_CR_B    0x28 /* Disable */
  55 /* Second register set */
  56 #define PMU_CLK_SR1     0x30 /* status */
  57 #define PMU_CLK_CR1_A   0x34 /* Enable */
  58 #define PMU_CLK_CR1_B   0x38 /* Disable */
  59 /* Third register set */
  60 #define PMU_ANA_SR      0x40 /* status */
  61 #define PMU_ANA_CR_A    0x44 /* Enable */
  62 #define PMU_ANA_CR_B    0x48 /* Disable */
  63
  64 /* Status */
  65 static u32 pmu_clk_sr[] = {
  66         PMU_CLK_SR,
  67         PMU_CLK_SR1,
  68         PMU_ANA_SR,
  69 };
  70
  71 /* Enable */
  72 static u32 pmu_clk_cr_a[] = {
  73         PMU_CLK_CR_A,
  74         PMU_CLK_CR1_A,
  75         PMU_ANA_CR_A,
  76 };
  77
  78 /* Disable */
  79 static u32 pmu_clk_cr_b[] = {
  80         PMU_CLK_CR_B,
  81         PMU_CLK_CR1_B,
  82         PMU_ANA_CR_B,
  83 };
  84
  85 #define PWDCR_EN_XRX(x)         (pmu_clk_cr_a[(x)])
  86 #define PWDCR_DIS_XRX(x)        (pmu_clk_cr_b[(x)])
  87 #define PWDSR_XRX(x)            (pmu_clk_sr[(x)])
  88
  89 /* clock gates that we can en/disable */
  90 #define PMU_USB0_P      BIT(0)
  91 #define PMU_ASE_SDIO    BIT(2) /* ASE special */
  92 #define PMU_PCI         BIT(4)
  93 #define PMU_DMA         BIT(5)
  94 #define PMU_USB0        BIT(6)
  95 #define PMU_ASC0        BIT(7)
  96 #define PMU_EPHY        BIT(7)  /* ase */
  97 #define PMU_USIF        BIT(7) /* from vr9 until grx390 */
  98 #define PMU_SPI         BIT(8)
  99 #define PMU_DFE         BIT(9)
 100 #define PMU_EBU         BIT(10)
 101 #define PMU_STP         BIT(11)
 102 #define PMU_GPT         BIT(12)
 103 #define PMU_AHBS        BIT(13) /* vr9 */
 104 #define PMU_FPI         BIT(14)
 105 #define PMU_AHBM        BIT(15)
 106 #define PMU_SDIO        BIT(16) /* danube, ar9, vr9 */
 107 #define PMU_ASC1        BIT(17)
 108 #define PMU_PPE_QSB     BIT(18)
 109 #define PMU_PPE_SLL01   BIT(19)
 110 #define PMU_PPE_TC      BIT(21)
 111 #define PMU_PPE_EMA     BIT(22)
 112 #define PMU_PPE_DPLUM   BIT(23)
 113 #define PMU_PPE_DPLUS   BIT(24)
 114 #define PMU_USB1_P      BIT(26)
 115 #define PMU_USB1        BIT(27)
 116 #define PMU_SWITCH      BIT(28)
 117 #define PMU_PPE_TOP     BIT(29)
 118 #define PMU_GPHY        BIT(30)
 119 #define PMU_PCIE_CLK    BIT(31)
 120
 121 #define PMU1_PCIE_PHY   BIT(0)
 122 #define PMU1_PCIE_CTL   BIT(1)
 123 #define PMU1_PCIE_PDI   BIT(4)
 124 #define PMU1_PCIE_MSI   BIT(5)
 125
 126 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
 127 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
 128
 129 static void __iomem *pmu_membase;
 130 void __iomem *ltq_cgu_membase;
 131 void __iomem *ltq_ebu_membase;
 132
 133 static u32 ifccr = CGU_IFCCR;
 134 static u32 pcicr = CGU_PCICR;
 135
 136 static DEFINE_SPINLOCK(g_pmu_lock);
 137
 138 /* legacy function kept alive to ease clkdev transition */
 139 void ltq_pmu_enable(unsigned int module)
 140 {
 141         int retry = 1000000;
 142
 143         spin_lock(&g_pmu_lock);
 144         pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
 145         do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
 146         spin_unlock(&g_pmu_lock);
 147
 148         if (!retry)
 149                 panic("activating PMU module failed!");
 150 }
 151 EXPORT_SYMBOL(ltq_pmu_enable);
 152
 153 /* legacy function kept alive to ease clkdev transition */
 154 void ltq_pmu_disable(unsigned int module)
 155 {
 156         int retry = 1000000;
 157
 158         spin_lock(&g_pmu_lock);
 159         pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
 160         do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
 161         spin_unlock(&g_pmu_lock);
 162
 163         if (!retry)
 164                 pr_warn("deactivating PMU module failed!");
 165 }
 166 EXPORT_SYMBOL(ltq_pmu_disable);
 167
 168 /* enable a hw clock */
 169 static int cgu_enable(struct clk *clk)
 170 {
 171         ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
 172         return 0;
 173 }
 174
 175 /* disable a hw clock */
 176 static void cgu_disable(struct clk *clk)
 177 {
 178         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 179 }
 180
 181 /* enable a clock gate */
 182 static int pmu_enable(struct clk *clk)
 183 {
 184         int retry = 1000000;
 185
 186         if (of_machine_is_compatible("lantiq,ar10")
 187             || of_machine_is_compatible("lantiq,grx390")) {
 188                 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
 189                 do {} while (--retry &&
 190                              (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
 191
 192         } else {
 193                 spin_lock(&g_pmu_lock);
 194                 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
 195                                 PWDCR(clk->module));
 196                 do {} while (--retry &&
 197                              (pmu_r32(PWDSR(clk->module)) & clk->bits));
 198                 spin_unlock(&g_pmu_lock);
 199         }
 200
 201         if (!retry)
 202                 panic("activating PMU module failed!");
 203
 204         return 0;
 205 }
 206
 207 /* disable a clock gate */
 208 static void pmu_disable(struct clk *clk)
 209 {
 210         int retry = 1000000;
 211
 212         if (of_machine_is_compatible("lantiq,ar10")
 213             || of_machine_is_compatible("lantiq,grx390")) {
 214                 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
 215                 do {} while (--retry &&
 216                              (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
 217         } else {
 218                 spin_lock(&g_pmu_lock);
 219                 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
 220                                 PWDCR(clk->module));
 221                 do {} while (--retry &&
 222                              (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
 223                 spin_unlock(&g_pmu_lock);
 224         }
 225
 226         if (!retry)
 227                 pr_warn("deactivating PMU module failed!");
 228 }
 229
 230 /* the pci enable helper */
 231 static int pci_enable(struct clk *clk)
 232 {
 233         unsigned int val = ltq_cgu_r32(ifccr);
 234         /* set bus clock speed */
 235         if (of_machine_is_compatible("lantiq,ar9") ||
 236                         of_machine_is_compatible("lantiq,vr9")) {
 237                 val &= ~0x1f00000;
 238                 if (clk->rate == CLOCK_33M)
 239                         val |= 0xe00000;
 240                 else
 241                         val |= 0x700000; /* 62.5M */
 242         } else {
 243                 val &= ~0xf00000;
 244                 if (clk->rate == CLOCK_33M)
 245                         val |= 0x800000;
 246                 else
 247                         val |= 0x400000; /* 62.5M */
 248         }
 249         ltq_cgu_w32(val, ifccr);
 250         pmu_enable(clk);
 251         return 0;
 252 }
 253
 254 /* enable the external clock as a source */
 255 static int pci_ext_enable(struct clk *clk)
 256 {
 257         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
 258         ltq_cgu_w32((1 << 30), pcicr);
 259         return 0;
 260 }
 261
 262 /* disable the external clock as a source */
 263 static void pci_ext_disable(struct clk *clk)
 264 {
 265         ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
 266         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 267 }
 268
 269 /* enable a clockout source */
 270 static int clkout_enable(struct clk *clk)
 271 {
 272         int i;
 273
 274         /* get the correct rate */
 275         for (i = 0; i < 4; i++) {
 276                 if (clk->rates[i] == clk->rate) {
 277                         int shift = 14 - (2 * clk->module);
 278                         int enable = 7 - clk->module;
 279                         unsigned int val = ltq_cgu_r32(ifccr);
 280
 281                         val &= ~(3 << shift);
 282                         val |= i << shift;
 283                         val |= enable;
 284                         ltq_cgu_w32(val, ifccr);
 285                         return 0;
 286                 }
 287         }
 288         return -1;
 289 }
 290
 291 /* manage the clock gates via PMU */
 292 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
 293                            unsigned int module, unsigned int bits)
 294 {
 295         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 296
 297         clk->cl.dev_id = dev;
 298         clk->cl.con_id = con;
 299         clk->cl.clk = clk;
 300         clk->enable = pmu_enable;
 301         clk->disable = pmu_disable;
 302         clk->module = module;
 303         clk->bits = bits;
 304         if (deactivate) {
 305                 /*
 306                  * Disable it during the initialization. Module should enable
 307                  * when used
 308                  */
 309                 pmu_disable(clk);
 310         }
 311         clkdev_add(&clk->cl);
 312 }
 313
 314 /* manage the clock generator */
 315 static void clkdev_add_cgu(const char *dev, const char *con,
 316                                         unsigned int bits)
 317 {
 318         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 319
 320         clk->cl.dev_id = dev;
 321         clk->cl.con_id = con;
 322         clk->cl.clk = clk;
 323         clk->enable = cgu_enable;
 324         clk->disable = cgu_disable;
 325         clk->bits = bits;
 326         clkdev_add(&clk->cl);
 327 }
 328
 329 /* pci needs its own enable function as the setup is a bit more complex */
 330 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
 331
 332 static void clkdev_add_pci(void)
 333 {
 334         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 335         struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 336
 337         /* main pci clock */
 338         clk->cl.dev_id = "17000000.pci";
 339         clk->cl.con_id = NULL;
 340         clk->cl.clk = clk;
 341         clk->rate = CLOCK_33M;
 342         clk->rates = valid_pci_rates;
 343         clk->enable = pci_enable;
 344         clk->disable = pmu_disable;
 345         clk->module = 0;
 346         clk->bits = PMU_PCI;
 347         clkdev_add(&clk->cl);
 348
 349         /* use internal/external bus clock */
 350         clk_ext->cl.dev_id = "17000000.pci";
 351         clk_ext->cl.con_id = "external";
 352         clk_ext->cl.clk = clk_ext;
 353         clk_ext->enable = pci_ext_enable;
 354         clk_ext->disable = pci_ext_disable;
 355         clkdev_add(&clk_ext->cl);
 356 }
 357
 358 /* xway socs can generate clocks on gpio pins */
 359 static unsigned long valid_clkout_rates[4][5] = {
 360         {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
 361         {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
 362         {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
 363         {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
 364 };
 365
 366 static void clkdev_add_clkout(void)
 367 {
 368         int i;
 369
 370         for (i = 0; i < 4; i++) {
 371                 struct clk *clk;
 372                 char *name;
 373
 374                 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
 375                 sprintf(name, "clkout%d", i);
 376
 377                 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 378                 clk->cl.dev_id = "1f103000.cgu";
 379                 clk->cl.con_id = name;
 380                 clk->cl.clk = clk;
 381                 clk->rate = 0;
 382                 clk->rates = valid_clkout_rates[i];
 383                 clk->enable = clkout_enable;
 384                 clk->module = i;
 385                 clkdev_add(&clk->cl);
 386         }
 387 }
 388
 389 /* bring up all register ranges that we need for basic system control */
 390 void __init ltq_soc_init(void)
 391 {
 392         struct resource res_pmu, res_cgu, res_ebu;
 393         struct device_node *np_pmu =
 394                         of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
 395         struct device_node *np_cgu =
 396                         of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
 397         struct device_node *np_ebu =
 398                         of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
 399
 400         /* check if all the core register ranges are available */
 401         if (!np_pmu || !np_cgu || !np_ebu)
 402                 panic("Failed to load core nodes from devicetree");
 403
 404         if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
 405                         of_address_to_resource(np_cgu, 0, &res_cgu) ||
 406                         of_address_to_resource(np_ebu, 0, &res_ebu))
 407                 panic("Failed to get core resources");
 408
 409         if ((request_mem_region(res_pmu.start, resource_size(&res_pmu),
 410                                 res_pmu.name) < 0) ||
 411                 (request_mem_region(res_cgu.start, resource_size(&res_cgu),
 412                                 res_cgu.name) < 0) ||
 413                 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
 414                                 res_ebu.name) < 0))
 415                 pr_err("Failed to request core resources");
 416
 417         pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
 418         ltq_cgu_membase = ioremap_nocache(res_cgu.start,
 419                                                 resource_size(&res_cgu));
 420         ltq_ebu_membase = ioremap_nocache(res_ebu.start,
 421                                                 resource_size(&res_ebu));
 422         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 423                 panic("Failed to remap core resources");
 424
 425         /* make sure to unprotect the memory region where flash is located */
 426         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 427
 428         /* add our generic xway clocks */
 429         clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
 430         clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
 431         clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
 432         clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
 433         clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
 434         clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
 435         clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
 436         clkdev_add_clkout();
 437
 438         /* add the soc dependent clocks */
 439         if (of_machine_is_compatible("lantiq,vr9")) {
 440                 ifccr = CGU_IFCCR_VR9;
 441                 pcicr = CGU_PCICR_VR9;
 442         } else {
 443                 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
 444         }
 445
 446         if (!of_machine_is_compatible("lantiq,ase")) {
 447                 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
 448                 clkdev_add_pci();
 449         }
 450
 451         if (of_machine_is_compatible("lantiq,ase")) {
 452                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 453                         clkdev_add_static(CLOCK_266M, CLOCK_133M,
 454                                                 CLOCK_133M, CLOCK_266M);
 455                 else
 456                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
 457                                                 CLOCK_133M, CLOCK_133M);
 458                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 459                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 460                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
 461                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
 462                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
 463                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
 464         } else if (of_machine_is_compatible("lantiq,vr9")) {
 465                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 466                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
 467                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 468                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
 469                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 470                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
 471                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
 472                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
 473                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 474                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
 475                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 476                 clkdev_add_pmu("1d900000.pcie", "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
 477
 478                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 479                 clkdev_add_pmu("1e108000.eth", NULL, 1, 0,
 480                                 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 481                                 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 482                                 PMU_PPE_QSB | PMU_PPE_TOP);
 483                 clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
 484                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 485         } else if (of_machine_is_compatible("lantiq,ar9")) {
 486                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 487                                 ltq_ar9_fpi_hz(), CLOCK_250M);
 488                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 489                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 490                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 491                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 492                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
 493                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 494         } else {
 495                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 496                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
 497                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 498                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 499                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 500         }
 501 }