2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39 #include <linux/perf_event.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
48 #include <asm/uaccess.h>
49 #include <asm/branch.h>
53 /* Strap kernel emulator for full MIPS IV emulation */
60 /* Function which emulates a floating point instruction. */
62 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
65 #if __mips >= 4 && __mips != 32
66 static int fpux_emu(struct pt_regs *,
67 struct mips_fpu_struct *, mips_instruction);
70 /* Further private data for which no space exists in mips_fpu_struct */
72 #ifdef CONFIG_DEBUG_FS
73 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
76 /* Control registers */
78 #define FPCREG_RID 0 /* $0 = revision id */
79 #define FPCREG_CSR 31 /* $31 = csr */
81 /* Determine rounding mode from the RM bits of the FCSR */
82 #define modeindex(v) ((v) & FPU_CSR_RM)
84 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
85 static const unsigned char ieee_rm[4] = {
86 [FPU_CSR_RN] = IEEE754_RN,
87 [FPU_CSR_RZ] = IEEE754_RZ,
88 [FPU_CSR_RU] = IEEE754_RU,
89 [FPU_CSR_RD] = IEEE754_RD,
91 /* Convert IEEE library modes to Mips rounding mode (0..3). */
92 static const unsigned char mips_rm[4] = {
93 [IEEE754_RN] = FPU_CSR_RN,
94 [IEEE754_RZ] = FPU_CSR_RZ,
95 [IEEE754_RD] = FPU_CSR_RD,
96 [IEEE754_RU] = FPU_CSR_RU,
100 /* convert condition code register number to csr bit */
101 static const unsigned int fpucondbit[8] = {
115 * Redundant with logic already in kernel/branch.c,
116 * embedded in compute_return_epc. At some point,
117 * a single subroutine should be used across both
120 static int isBranchInstr(mips_instruction * i)
122 switch (MIPSInst_OPCODE(*i)) {
124 switch (MIPSInst_FUNC(*i)) {
132 switch (MIPSInst_RT(*i)) {
162 if (MIPSInst_RS(*i) == bc_op)
171 * In the Linux kernel, we support selection of FPR format on the
172 * basis of the Status.FR bit. If an FPU is not present, the FR bit
173 * is hardwired to zero, which would imply a 32-bit FPU even for
174 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
175 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
176 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
177 * even FPRs are used (Status.FR = 0).
179 static inline int cop1_64bit(struct pt_regs *xcp)
182 return xcp->cp0_status & ST0_FR;
184 return !test_thread_flag(TIF_32BIT_REGS);
190 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
191 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
193 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
194 cop1_64bit(xcp) || !(x & 1) ? \
195 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
196 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
198 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
199 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
201 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
202 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
203 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
204 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
207 * Emulate the single floating point instruction pointed at by EPC.
208 * Two instructions if the instruction is in a branch delay slot.
211 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
214 unsigned long emulpc, contpc;
217 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
218 MIPS_FPU_EMU_INC_STATS(errors);
222 /* XXX NEC Vr54xx bug workaround */
223 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
224 xcp->cp0_cause &= ~CAUSEF_BD;
226 if (xcp->cp0_cause & CAUSEF_BD) {
228 * The instruction to be emulated is in a branch delay slot
229 * which means that we have to emulate the branch instruction
230 * BEFORE we do the cop1 instruction.
232 * This branch could be a COP1 branch, but in that case we
233 * would have had a trap for that instruction, and would not
234 * come through this route.
236 * Linux MIPS branch emulator operates on context, updating the
239 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
241 if (__compute_return_epc(xcp)) {
243 printk("failed to emulate branch at %p\n",
244 (void *) (xcp->cp0_epc));
248 if (get_user(ir, (mips_instruction __user *) emulpc)) {
249 MIPS_FPU_EMU_INC_STATS(errors);
252 /* __compute_return_epc() will have updated cp0_epc */
253 contpc = xcp->cp0_epc;
254 /* In order not to confuse ptrace() et al, tweak context */
255 xcp->cp0_epc = emulpc - 4;
257 emulpc = xcp->cp0_epc;
258 contpc = xcp->cp0_epc + 4;
262 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
264 MIPS_FPU_EMU_INC_STATS(emulated);
265 switch (MIPSInst_OPCODE(ir)) {
267 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
271 MIPS_FPU_EMU_INC_STATS(loads);
272 if (get_user(val, va)) {
273 MIPS_FPU_EMU_INC_STATS(errors);
276 DITOREG(val, MIPSInst_RT(ir));
281 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
285 MIPS_FPU_EMU_INC_STATS(stores);
286 DIFROMREG(val, MIPSInst_RT(ir));
287 if (put_user(val, va)) {
288 MIPS_FPU_EMU_INC_STATS(errors);
295 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
299 MIPS_FPU_EMU_INC_STATS(loads);
300 if (get_user(val, va)) {
301 MIPS_FPU_EMU_INC_STATS(errors);
304 SITOREG(val, MIPSInst_RT(ir));
309 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
313 MIPS_FPU_EMU_INC_STATS(stores);
314 SIFROMREG(val, MIPSInst_RT(ir));
315 if (put_user(val, va)) {
316 MIPS_FPU_EMU_INC_STATS(errors);
323 switch (MIPSInst_RS(ir)) {
325 #if defined(__mips64)
327 /* copregister fs -> gpr[rt] */
328 if (MIPSInst_RT(ir) != 0) {
329 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
335 /* copregister fs <- rt */
336 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
341 /* copregister rd -> gpr[rt] */
342 if (MIPSInst_RT(ir) != 0) {
343 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
349 /* copregister rd <- rt */
350 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
354 /* cop control register rd -> gpr[rt] */
357 if (MIPSInst_RD(ir) == FPCREG_CSR) {
359 value = (value & ~FPU_CSR_RM) |
360 mips_rm[modeindex(value)];
362 printk("%p gpr[%d]<-csr=%08x\n",
363 (void *) (xcp->cp0_epc),
364 MIPSInst_RT(ir), value);
367 else if (MIPSInst_RD(ir) == FPCREG_RID)
372 xcp->regs[MIPSInst_RT(ir)] = value;
377 /* copregister rd <- rt */
380 if (MIPSInst_RT(ir) == 0)
383 value = xcp->regs[MIPSInst_RT(ir)];
385 /* we only have one writable control reg
387 if (MIPSInst_RD(ir) == FPCREG_CSR) {
389 printk("%p gpr[%d]->csr=%08x\n",
390 (void *) (xcp->cp0_epc),
391 MIPSInst_RT(ir), value);
395 * Don't write reserved bits,
396 * and convert to ieee library modes
398 ctx->fcr31 = (value &
399 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
400 ieee_rm[modeindex(value)];
402 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
411 if (xcp->cp0_cause & CAUSEF_BD)
415 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
417 cond = ctx->fcr31 & FPU_CSR_COND;
419 switch (MIPSInst_RT(ir) & 3) {
430 /* thats an illegal instruction */
434 xcp->cp0_cause |= CAUSEF_BD;
436 /* branch taken: emulate dslot
440 contpc = (xcp->cp0_epc +
441 (MIPSInst_SIMM(ir) << 2));
444 (mips_instruction __user *) xcp->cp0_epc)) {
445 MIPS_FPU_EMU_INC_STATS(errors);
449 switch (MIPSInst_OPCODE(ir)) {
452 #if (__mips >= 2 || defined(__mips64))
457 #if __mips >= 4 && __mips != 32
460 /* its one of ours */
464 if (MIPSInst_FUNC(ir) == movc_op)
471 * Single step the non-cp1
472 * instruction in the dslot
474 return mips_dsemul(xcp, ir, contpc);
477 /* branch not taken */
480 * branch likely nullifies
486 * else continue & execute
487 * dslot as normal insn
495 if (!(MIPSInst_RS(ir) & 0x10))
500 /* a real fpu computation instruction */
501 if ((sig = fpu_emu(xcp, ctx, ir)))
507 #if __mips >= 4 && __mips != 32
511 if ((sig = fpux_emu(xcp, ctx, ir)))
519 if (MIPSInst_FUNC(ir) != movc_op)
521 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
522 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
523 xcp->regs[MIPSInst_RD(ir)] =
524 xcp->regs[MIPSInst_RS(ir)];
533 xcp->cp0_epc = contpc;
534 xcp->cp0_cause &= ~CAUSEF_BD;
540 * Conversion table from MIPS compare ops 48-63
541 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
543 static const unsigned char cmptab[8] = {
544 0, /* cmp_0 (sig) cmp_sf */
545 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
546 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
547 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
548 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
549 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
550 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
551 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
555 #if __mips >= 4 && __mips != 32
558 * Additional MIPS4 instructions
561 #define DEF3OP(name, p, f1, f2, f3) \
562 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
565 struct _ieee754_csr ieee754_csr_save; \
567 ieee754_csr_save = ieee754_csr; \
569 ieee754_csr_save.cx |= ieee754_csr.cx; \
570 ieee754_csr_save.sx |= ieee754_csr.sx; \
572 ieee754_csr.cx |= ieee754_csr_save.cx; \
573 ieee754_csr.sx |= ieee754_csr_save.sx; \
577 static ieee754dp fpemu_dp_recip(ieee754dp d)
579 return ieee754dp_div(ieee754dp_one(0), d);
582 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
584 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
587 static ieee754sp fpemu_sp_recip(ieee754sp s)
589 return ieee754sp_div(ieee754sp_one(0), s);
592 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
594 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
597 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
598 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
599 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
600 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
601 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
602 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
603 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
604 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
606 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
609 unsigned rcsr = 0; /* resulting csr */
611 MIPS_FPU_EMU_INC_STATS(cp1xops);
613 switch (MIPSInst_FMA_FFMT(ir)) {
616 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
617 ieee754sp fd, fr, fs, ft;
621 switch (MIPSInst_FUNC(ir)) {
623 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
624 xcp->regs[MIPSInst_FT(ir)]);
626 MIPS_FPU_EMU_INC_STATS(loads);
627 if (get_user(val, va)) {
628 MIPS_FPU_EMU_INC_STATS(errors);
631 SITOREG(val, MIPSInst_FD(ir));
635 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
636 xcp->regs[MIPSInst_FT(ir)]);
638 MIPS_FPU_EMU_INC_STATS(stores);
640 SIFROMREG(val, MIPSInst_FS(ir));
641 if (put_user(val, va)) {
642 MIPS_FPU_EMU_INC_STATS(errors);
648 handler = fpemu_sp_madd;
651 handler = fpemu_sp_msub;
654 handler = fpemu_sp_nmadd;
657 handler = fpemu_sp_nmsub;
661 SPFROMREG(fr, MIPSInst_FR(ir));
662 SPFROMREG(fs, MIPSInst_FS(ir));
663 SPFROMREG(ft, MIPSInst_FT(ir));
664 fd = (*handler) (fr, fs, ft);
665 SPTOREG(fd, MIPSInst_FD(ir));
668 if (ieee754_cxtest(IEEE754_INEXACT))
669 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
670 if (ieee754_cxtest(IEEE754_UNDERFLOW))
671 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
672 if (ieee754_cxtest(IEEE754_OVERFLOW))
673 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
674 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
675 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
677 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
678 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
679 /*printk ("SIGFPE: fpu csr = %08x\n",
693 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
694 ieee754dp fd, fr, fs, ft;
698 switch (MIPSInst_FUNC(ir)) {
700 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
701 xcp->regs[MIPSInst_FT(ir)]);
703 MIPS_FPU_EMU_INC_STATS(loads);
704 if (get_user(val, va)) {
705 MIPS_FPU_EMU_INC_STATS(errors);
708 DITOREG(val, MIPSInst_FD(ir));
712 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
713 xcp->regs[MIPSInst_FT(ir)]);
715 MIPS_FPU_EMU_INC_STATS(stores);
716 DIFROMREG(val, MIPSInst_FS(ir));
717 if (put_user(val, va)) {
718 MIPS_FPU_EMU_INC_STATS(errors);
724 handler = fpemu_dp_madd;
727 handler = fpemu_dp_msub;
730 handler = fpemu_dp_nmadd;
733 handler = fpemu_dp_nmsub;
737 DPFROMREG(fr, MIPSInst_FR(ir));
738 DPFROMREG(fs, MIPSInst_FS(ir));
739 DPFROMREG(ft, MIPSInst_FT(ir));
740 fd = (*handler) (fr, fs, ft);
741 DPTOREG(fd, MIPSInst_FD(ir));
751 if (MIPSInst_FUNC(ir) != pfetch_op) {
754 /* ignore prefx operation */
768 * Emulate a single COP1 arithmetic instruction.
770 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
773 int rfmt; /* resulting format */
774 unsigned rcsr = 0; /* resulting csr */
783 } rv; /* resulting value */
785 MIPS_FPU_EMU_INC_STATS(cp1ops);
786 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
789 ieee754sp(*b) (ieee754sp, ieee754sp);
790 ieee754sp(*u) (ieee754sp);
793 switch (MIPSInst_FUNC(ir)) {
796 handler.b = ieee754sp_add;
799 handler.b = ieee754sp_sub;
802 handler.b = ieee754sp_mul;
805 handler.b = ieee754sp_div;
809 #if __mips >= 2 || defined(__mips64)
811 handler.u = ieee754sp_sqrt;
814 #if __mips >= 4 && __mips != 32
816 handler.u = fpemu_sp_rsqrt;
819 handler.u = fpemu_sp_recip;
824 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
825 if (((ctx->fcr31 & cond) != 0) !=
826 ((MIPSInst_FT(ir) & 1) != 0))
828 SPFROMREG(rv.s, MIPSInst_FS(ir));
831 if (xcp->regs[MIPSInst_FT(ir)] != 0)
833 SPFROMREG(rv.s, MIPSInst_FS(ir));
836 if (xcp->regs[MIPSInst_FT(ir)] == 0)
838 SPFROMREG(rv.s, MIPSInst_FS(ir));
842 handler.u = ieee754sp_abs;
845 handler.u = ieee754sp_neg;
849 SPFROMREG(rv.s, MIPSInst_FS(ir));
852 /* binary op on handler */
857 SPFROMREG(fs, MIPSInst_FS(ir));
858 SPFROMREG(ft, MIPSInst_FT(ir));
860 rv.s = (*handler.b) (fs, ft);
867 SPFROMREG(fs, MIPSInst_FS(ir));
868 rv.s = (*handler.u) (fs);
872 if (ieee754_cxtest(IEEE754_INEXACT))
873 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
874 if (ieee754_cxtest(IEEE754_UNDERFLOW))
875 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
876 if (ieee754_cxtest(IEEE754_OVERFLOW))
877 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
878 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
879 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
880 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
881 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
886 return SIGILL; /* not defined */
890 SPFROMREG(fs, MIPSInst_FS(ir));
891 rv.d = ieee754dp_fsp(fs);
898 SPFROMREG(fs, MIPSInst_FS(ir));
899 rv.w = ieee754sp_tint(fs);
904 #if __mips >= 2 || defined(__mips64)
909 unsigned int oldrm = ieee754_csr.rm;
912 SPFROMREG(fs, MIPSInst_FS(ir));
913 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
914 rv.w = ieee754sp_tint(fs);
915 ieee754_csr.rm = oldrm;
919 #endif /* __mips >= 2 */
921 #if defined(__mips64)
925 SPFROMREG(fs, MIPSInst_FS(ir));
926 rv.l = ieee754sp_tlong(fs);
935 unsigned int oldrm = ieee754_csr.rm;
938 SPFROMREG(fs, MIPSInst_FS(ir));
939 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
940 rv.l = ieee754sp_tlong(fs);
941 ieee754_csr.rm = oldrm;
945 #endif /* defined(__mips64) */
948 if (MIPSInst_FUNC(ir) >= fcmp_op) {
949 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
952 SPFROMREG(fs, MIPSInst_FS(ir));
953 SPFROMREG(ft, MIPSInst_FT(ir));
954 rv.w = ieee754sp_cmp(fs, ft,
955 cmptab[cmpop & 0x7], cmpop & 0x8);
957 if ((cmpop & 0x8) && ieee754_cxtest
958 (IEEE754_INVALID_OPERATION))
959 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
974 ieee754dp(*b) (ieee754dp, ieee754dp);
975 ieee754dp(*u) (ieee754dp);
978 switch (MIPSInst_FUNC(ir)) {
981 handler.b = ieee754dp_add;
984 handler.b = ieee754dp_sub;
987 handler.b = ieee754dp_mul;
990 handler.b = ieee754dp_div;
994 #if __mips >= 2 || defined(__mips64)
996 handler.u = ieee754dp_sqrt;
999 #if __mips >= 4 && __mips != 32
1001 handler.u = fpemu_dp_rsqrt;
1004 handler.u = fpemu_dp_recip;
1009 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1010 if (((ctx->fcr31 & cond) != 0) !=
1011 ((MIPSInst_FT(ir) & 1) != 0))
1013 DPFROMREG(rv.d, MIPSInst_FS(ir));
1016 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1018 DPFROMREG(rv.d, MIPSInst_FS(ir));
1021 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1023 DPFROMREG(rv.d, MIPSInst_FS(ir));
1027 handler.u = ieee754dp_abs;
1031 handler.u = ieee754dp_neg;
1036 DPFROMREG(rv.d, MIPSInst_FS(ir));
1039 /* binary op on handler */
1043 DPFROMREG(fs, MIPSInst_FS(ir));
1044 DPFROMREG(ft, MIPSInst_FT(ir));
1046 rv.d = (*handler.b) (fs, ft);
1052 DPFROMREG(fs, MIPSInst_FS(ir));
1053 rv.d = (*handler.u) (fs);
1057 /* unary conv ops */
1061 DPFROMREG(fs, MIPSInst_FS(ir));
1062 rv.s = ieee754sp_fdp(fs);
1067 return SIGILL; /* not defined */
1072 DPFROMREG(fs, MIPSInst_FS(ir));
1073 rv.w = ieee754dp_tint(fs); /* wrong */
1078 #if __mips >= 2 || defined(__mips64)
1083 unsigned int oldrm = ieee754_csr.rm;
1086 DPFROMREG(fs, MIPSInst_FS(ir));
1087 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1088 rv.w = ieee754dp_tint(fs);
1089 ieee754_csr.rm = oldrm;
1095 #if defined(__mips64)
1099 DPFROMREG(fs, MIPSInst_FS(ir));
1100 rv.l = ieee754dp_tlong(fs);
1109 unsigned int oldrm = ieee754_csr.rm;
1112 DPFROMREG(fs, MIPSInst_FS(ir));
1113 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1114 rv.l = ieee754dp_tlong(fs);
1115 ieee754_csr.rm = oldrm;
1119 #endif /* __mips >= 3 */
1122 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1123 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1126 DPFROMREG(fs, MIPSInst_FS(ir));
1127 DPFROMREG(ft, MIPSInst_FT(ir));
1128 rv.w = ieee754dp_cmp(fs, ft,
1129 cmptab[cmpop & 0x7], cmpop & 0x8);
1134 (IEEE754_INVALID_OPERATION))
1135 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1151 switch (MIPSInst_FUNC(ir)) {
1153 /* convert word to single precision real */
1154 SPFROMREG(fs, MIPSInst_FS(ir));
1155 rv.s = ieee754sp_fint(fs.bits);
1159 /* convert word to double precision real */
1160 SPFROMREG(fs, MIPSInst_FS(ir));
1161 rv.d = ieee754dp_fint(fs.bits);
1170 #if defined(__mips64)
1172 switch (MIPSInst_FUNC(ir)) {
1174 /* convert long to single precision real */
1175 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1179 /* convert long to double precision real */
1180 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1195 * Update the fpu CSR register for this operation.
1196 * If an exception is required, generate a tidy SIGFPE exception,
1197 * without updating the result register.
1198 * Note: cause exception bits do not accumulate, they are rewritten
1199 * for each op; only the flag/sticky bits accumulate.
1201 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1202 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1203 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1208 * Now we can safely write the result back to the register file.
1213 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1215 cond = FPU_CSR_COND;
1220 ctx->fcr31 &= ~cond;
1224 DPTOREG(rv.d, MIPSInst_FD(ir));
1227 SPTOREG(rv.s, MIPSInst_FD(ir));
1230 SITOREG(rv.w, MIPSInst_FD(ir));
1232 #if defined(__mips64)
1234 DITOREG(rv.l, MIPSInst_FD(ir));
1244 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1247 unsigned long oldepc, prevepc;
1248 mips_instruction insn;
1251 oldepc = xcp->cp0_epc;
1253 prevepc = xcp->cp0_epc;
1255 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1256 MIPS_FPU_EMU_INC_STATS(errors);
1260 xcp->cp0_epc += 4; /* skip nops */
1263 * The 'ieee754_csr' is an alias of
1264 * ctx->fcr31. No need to copy ctx->fcr31 to
1265 * ieee754_csr. But ieee754_csr.rm is ieee
1266 * library modes. (not mips rounding mode)
1268 /* convert to ieee library modes */
1269 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1270 sig = cop1Emulate(xcp, ctx);
1271 /* revert to mips rounding mode */
1272 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1281 } while (xcp->cp0_epc > prevepc);
1283 /* SIGILL indicates a non-fpu instruction */
1284 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1285 /* but if epc has advanced, then ignore it */
1291 #ifdef CONFIG_DEBUG_FS
1293 static int fpuemu_stat_get(void *data, u64 *val)
1296 unsigned long sum = 0;
1297 for_each_online_cpu(cpu) {
1298 struct mips_fpu_emulator_stats *ps;
1300 ps = &per_cpu(fpuemustats, cpu);
1301 pv = (void *)ps + (unsigned long)data;
1302 sum += local_read(pv);
1307 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1309 extern struct dentry *mips_debugfs_dir;
1310 static int __init debugfs_fpuemu(void)
1312 struct dentry *d, *dir;
1314 if (!mips_debugfs_dir)
1316 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1320 #define FPU_STAT_CREATE(M) \
1322 d = debugfs_create_file(#M , S_IRUGO, dir, \
1323 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1324 &fops_fpuemu_stat); \
1329 FPU_STAT_CREATE(emulated);
1330 FPU_STAT_CREATE(loads);
1331 FPU_STAT_CREATE(stores);
1332 FPU_STAT_CREATE(cp1ops);
1333 FPU_STAT_CREATE(cp1xops);
1334 FPU_STAT_CREATE(errors);
1338 __initcall(debugfs_fpuemu);