2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39 #include <linux/perf_event.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
48 #include <asm/uaccess.h>
49 #include <asm/branch.h>
53 /* Strap kernel emulator for full MIPS IV emulation */
60 /* Function which emulates a floating point instruction. */
62 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
65 #if __mips >= 4 && __mips != 32
66 static int fpux_emu(struct pt_regs *,
67 struct mips_fpu_struct *, mips_instruction, void *__user *);
70 /* Further private data for which no space exists in mips_fpu_struct */
72 #ifdef CONFIG_DEBUG_FS
73 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
76 /* Control registers */
78 #define FPCREG_RID 0 /* $0 = revision id */
79 #define FPCREG_CSR 31 /* $31 = csr */
81 /* Determine rounding mode from the RM bits of the FCSR */
82 #define modeindex(v) ((v) & FPU_CSR_RM)
84 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
85 static const unsigned char ieee_rm[4] = {
86 [FPU_CSR_RN] = IEEE754_RN,
87 [FPU_CSR_RZ] = IEEE754_RZ,
88 [FPU_CSR_RU] = IEEE754_RU,
89 [FPU_CSR_RD] = IEEE754_RD,
91 /* Convert IEEE library modes to Mips rounding mode (0..3). */
92 static const unsigned char mips_rm[4] = {
93 [IEEE754_RN] = FPU_CSR_RN,
94 [IEEE754_RZ] = FPU_CSR_RZ,
95 [IEEE754_RD] = FPU_CSR_RD,
96 [IEEE754_RU] = FPU_CSR_RU,
100 /* convert condition code register number to csr bit */
101 static const unsigned int fpucondbit[8] = {
115 * Redundant with logic already in kernel/branch.c,
116 * embedded in compute_return_epc. At some point,
117 * a single subroutine should be used across both
120 static int isBranchInstr(mips_instruction * i)
122 switch (MIPSInst_OPCODE(*i)) {
124 switch (MIPSInst_FUNC(*i)) {
132 switch (MIPSInst_RT(*i)) {
162 if (MIPSInst_RS(*i) == bc_op)
171 * In the Linux kernel, we support selection of FPR format on the
172 * basis of the Status.FR bit. If an FPU is not present, the FR bit
173 * is hardwired to zero, which would imply a 32-bit FPU even for
174 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
175 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
176 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
177 * even FPRs are used (Status.FR = 0).
179 static inline int cop1_64bit(struct pt_regs *xcp)
182 return xcp->cp0_status & ST0_FR;
184 return !test_thread_flag(TIF_32BIT_REGS);
190 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
191 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
193 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
194 cop1_64bit(xcp) || !(x & 1) ? \
195 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
196 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
198 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
199 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
201 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
202 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
203 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
204 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
207 * Emulate the single floating point instruction pointed at by EPC.
208 * Two instructions if the instruction is in a branch delay slot.
211 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
212 void *__user *fault_addr)
215 unsigned long emulpc, contpc;
218 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
219 MIPS_FPU_EMU_INC_STATS(errors);
220 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
223 if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
224 MIPS_FPU_EMU_INC_STATS(errors);
225 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
229 /* XXX NEC Vr54xx bug workaround */
230 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
231 xcp->cp0_cause &= ~CAUSEF_BD;
233 if (xcp->cp0_cause & CAUSEF_BD) {
235 * The instruction to be emulated is in a branch delay slot
236 * which means that we have to emulate the branch instruction
237 * BEFORE we do the cop1 instruction.
239 * This branch could be a COP1 branch, but in that case we
240 * would have had a trap for that instruction, and would not
241 * come through this route.
243 * Linux MIPS branch emulator operates on context, updating the
246 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
248 if (__compute_return_epc(xcp)) {
250 printk("failed to emulate branch at %p\n",
251 (void *) (xcp->cp0_epc));
255 if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) {
256 MIPS_FPU_EMU_INC_STATS(errors);
257 *fault_addr = (mips_instruction __user *)emulpc;
260 if (__get_user(ir, (mips_instruction __user *) emulpc)) {
261 MIPS_FPU_EMU_INC_STATS(errors);
262 *fault_addr = (mips_instruction __user *)emulpc;
265 /* __compute_return_epc() will have updated cp0_epc */
266 contpc = xcp->cp0_epc;
267 /* In order not to confuse ptrace() et al, tweak context */
268 xcp->cp0_epc = emulpc - 4;
270 emulpc = xcp->cp0_epc;
271 contpc = xcp->cp0_epc + 4;
275 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
276 MIPS_FPU_EMU_INC_STATS(emulated);
277 switch (MIPSInst_OPCODE(ir)) {
279 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
283 MIPS_FPU_EMU_INC_STATS(loads);
285 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
286 MIPS_FPU_EMU_INC_STATS(errors);
290 if (__get_user(val, va)) {
291 MIPS_FPU_EMU_INC_STATS(errors);
295 DITOREG(val, MIPSInst_RT(ir));
300 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
304 MIPS_FPU_EMU_INC_STATS(stores);
305 DIFROMREG(val, MIPSInst_RT(ir));
306 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
307 MIPS_FPU_EMU_INC_STATS(errors);
311 if (__put_user(val, va)) {
312 MIPS_FPU_EMU_INC_STATS(errors);
320 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
324 MIPS_FPU_EMU_INC_STATS(loads);
325 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
326 MIPS_FPU_EMU_INC_STATS(errors);
330 if (__get_user(val, va)) {
331 MIPS_FPU_EMU_INC_STATS(errors);
335 SITOREG(val, MIPSInst_RT(ir));
340 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
344 MIPS_FPU_EMU_INC_STATS(stores);
345 SIFROMREG(val, MIPSInst_RT(ir));
346 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
347 MIPS_FPU_EMU_INC_STATS(errors);
351 if (__put_user(val, va)) {
352 MIPS_FPU_EMU_INC_STATS(errors);
360 switch (MIPSInst_RS(ir)) {
362 #if defined(__mips64)
364 /* copregister fs -> gpr[rt] */
365 if (MIPSInst_RT(ir) != 0) {
366 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
372 /* copregister fs <- rt */
373 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
378 /* copregister rd -> gpr[rt] */
379 if (MIPSInst_RT(ir) != 0) {
380 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
386 /* copregister rd <- rt */
387 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
391 /* cop control register rd -> gpr[rt] */
394 if (MIPSInst_RD(ir) == FPCREG_CSR) {
396 value = (value & ~FPU_CSR_RM) |
397 mips_rm[modeindex(value)];
399 printk("%p gpr[%d]<-csr=%08x\n",
400 (void *) (xcp->cp0_epc),
401 MIPSInst_RT(ir), value);
404 else if (MIPSInst_RD(ir) == FPCREG_RID)
409 xcp->regs[MIPSInst_RT(ir)] = value;
414 /* copregister rd <- rt */
417 if (MIPSInst_RT(ir) == 0)
420 value = xcp->regs[MIPSInst_RT(ir)];
422 /* we only have one writable control reg
424 if (MIPSInst_RD(ir) == FPCREG_CSR) {
426 printk("%p gpr[%d]->csr=%08x\n",
427 (void *) (xcp->cp0_epc),
428 MIPSInst_RT(ir), value);
432 * Don't write reserved bits,
433 * and convert to ieee library modes
435 ctx->fcr31 = (value &
436 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
437 ieee_rm[modeindex(value)];
439 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
448 if (xcp->cp0_cause & CAUSEF_BD)
452 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
454 cond = ctx->fcr31 & FPU_CSR_COND;
456 switch (MIPSInst_RT(ir) & 3) {
467 /* thats an illegal instruction */
471 xcp->cp0_cause |= CAUSEF_BD;
473 /* branch taken: emulate dslot
477 contpc = (xcp->cp0_epc +
478 (MIPSInst_SIMM(ir) << 2));
480 if (!access_ok(VERIFY_READ, xcp->cp0_epc,
481 sizeof(mips_instruction))) {
482 MIPS_FPU_EMU_INC_STATS(errors);
483 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
487 (mips_instruction __user *) xcp->cp0_epc)) {
488 MIPS_FPU_EMU_INC_STATS(errors);
489 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
493 switch (MIPSInst_OPCODE(ir)) {
496 #if (__mips >= 2 || defined(__mips64))
501 #if __mips >= 4 && __mips != 32
504 /* its one of ours */
508 if (MIPSInst_FUNC(ir) == movc_op)
515 * Single step the non-cp1
516 * instruction in the dslot
518 return mips_dsemul(xcp, ir, contpc);
521 /* branch not taken */
524 * branch likely nullifies
530 * else continue & execute
531 * dslot as normal insn
539 if (!(MIPSInst_RS(ir) & 0x10))
544 /* a real fpu computation instruction */
545 if ((sig = fpu_emu(xcp, ctx, ir)))
551 #if __mips >= 4 && __mips != 32
553 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
562 if (MIPSInst_FUNC(ir) != movc_op)
564 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
565 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
566 xcp->regs[MIPSInst_RD(ir)] =
567 xcp->regs[MIPSInst_RS(ir)];
576 xcp->cp0_epc = contpc;
577 xcp->cp0_cause &= ~CAUSEF_BD;
583 * Conversion table from MIPS compare ops 48-63
584 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
586 static const unsigned char cmptab[8] = {
587 0, /* cmp_0 (sig) cmp_sf */
588 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
589 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
590 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
591 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
592 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
593 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
594 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
598 #if __mips >= 4 && __mips != 32
601 * Additional MIPS4 instructions
604 #define DEF3OP(name, p, f1, f2, f3) \
605 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
608 struct _ieee754_csr ieee754_csr_save; \
610 ieee754_csr_save = ieee754_csr; \
612 ieee754_csr_save.cx |= ieee754_csr.cx; \
613 ieee754_csr_save.sx |= ieee754_csr.sx; \
615 ieee754_csr.cx |= ieee754_csr_save.cx; \
616 ieee754_csr.sx |= ieee754_csr_save.sx; \
620 static ieee754dp fpemu_dp_recip(ieee754dp d)
622 return ieee754dp_div(ieee754dp_one(0), d);
625 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
627 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
630 static ieee754sp fpemu_sp_recip(ieee754sp s)
632 return ieee754sp_div(ieee754sp_one(0), s);
635 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
637 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
640 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
641 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
642 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
643 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
644 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
645 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
646 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
647 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
649 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
650 mips_instruction ir, void *__user *fault_addr)
652 unsigned rcsr = 0; /* resulting csr */
654 MIPS_FPU_EMU_INC_STATS(cp1xops);
656 switch (MIPSInst_FMA_FFMT(ir)) {
659 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
660 ieee754sp fd, fr, fs, ft;
664 switch (MIPSInst_FUNC(ir)) {
666 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
667 xcp->regs[MIPSInst_FT(ir)]);
669 MIPS_FPU_EMU_INC_STATS(loads);
670 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
671 MIPS_FPU_EMU_INC_STATS(errors);
675 if (__get_user(val, va)) {
676 MIPS_FPU_EMU_INC_STATS(errors);
680 SITOREG(val, MIPSInst_FD(ir));
684 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
685 xcp->regs[MIPSInst_FT(ir)]);
687 MIPS_FPU_EMU_INC_STATS(stores);
689 SIFROMREG(val, MIPSInst_FS(ir));
690 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
691 MIPS_FPU_EMU_INC_STATS(errors);
695 if (put_user(val, va)) {
696 MIPS_FPU_EMU_INC_STATS(errors);
703 handler = fpemu_sp_madd;
706 handler = fpemu_sp_msub;
709 handler = fpemu_sp_nmadd;
712 handler = fpemu_sp_nmsub;
716 SPFROMREG(fr, MIPSInst_FR(ir));
717 SPFROMREG(fs, MIPSInst_FS(ir));
718 SPFROMREG(ft, MIPSInst_FT(ir));
719 fd = (*handler) (fr, fs, ft);
720 SPTOREG(fd, MIPSInst_FD(ir));
723 if (ieee754_cxtest(IEEE754_INEXACT))
724 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
725 if (ieee754_cxtest(IEEE754_UNDERFLOW))
726 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
727 if (ieee754_cxtest(IEEE754_OVERFLOW))
728 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
729 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
730 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
732 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
733 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
734 /*printk ("SIGFPE: fpu csr = %08x\n",
748 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
749 ieee754dp fd, fr, fs, ft;
753 switch (MIPSInst_FUNC(ir)) {
755 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
756 xcp->regs[MIPSInst_FT(ir)]);
758 MIPS_FPU_EMU_INC_STATS(loads);
759 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
760 MIPS_FPU_EMU_INC_STATS(errors);
764 if (__get_user(val, va)) {
765 MIPS_FPU_EMU_INC_STATS(errors);
769 DITOREG(val, MIPSInst_FD(ir));
773 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
774 xcp->regs[MIPSInst_FT(ir)]);
776 MIPS_FPU_EMU_INC_STATS(stores);
777 DIFROMREG(val, MIPSInst_FS(ir));
778 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
779 MIPS_FPU_EMU_INC_STATS(errors);
783 if (__put_user(val, va)) {
784 MIPS_FPU_EMU_INC_STATS(errors);
791 handler = fpemu_dp_madd;
794 handler = fpemu_dp_msub;
797 handler = fpemu_dp_nmadd;
800 handler = fpemu_dp_nmsub;
804 DPFROMREG(fr, MIPSInst_FR(ir));
805 DPFROMREG(fs, MIPSInst_FS(ir));
806 DPFROMREG(ft, MIPSInst_FT(ir));
807 fd = (*handler) (fr, fs, ft);
808 DPTOREG(fd, MIPSInst_FD(ir));
818 if (MIPSInst_FUNC(ir) != pfetch_op) {
821 /* ignore prefx operation */
835 * Emulate a single COP1 arithmetic instruction.
837 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
840 int rfmt; /* resulting format */
841 unsigned rcsr = 0; /* resulting csr */
850 } rv; /* resulting value */
852 MIPS_FPU_EMU_INC_STATS(cp1ops);
853 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
856 ieee754sp(*b) (ieee754sp, ieee754sp);
857 ieee754sp(*u) (ieee754sp);
860 switch (MIPSInst_FUNC(ir)) {
863 handler.b = ieee754sp_add;
866 handler.b = ieee754sp_sub;
869 handler.b = ieee754sp_mul;
872 handler.b = ieee754sp_div;
876 #if __mips >= 2 || defined(__mips64)
878 handler.u = ieee754sp_sqrt;
881 #if __mips >= 4 && __mips != 32
883 handler.u = fpemu_sp_rsqrt;
886 handler.u = fpemu_sp_recip;
891 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
892 if (((ctx->fcr31 & cond) != 0) !=
893 ((MIPSInst_FT(ir) & 1) != 0))
895 SPFROMREG(rv.s, MIPSInst_FS(ir));
898 if (xcp->regs[MIPSInst_FT(ir)] != 0)
900 SPFROMREG(rv.s, MIPSInst_FS(ir));
903 if (xcp->regs[MIPSInst_FT(ir)] == 0)
905 SPFROMREG(rv.s, MIPSInst_FS(ir));
909 handler.u = ieee754sp_abs;
912 handler.u = ieee754sp_neg;
916 SPFROMREG(rv.s, MIPSInst_FS(ir));
919 /* binary op on handler */
924 SPFROMREG(fs, MIPSInst_FS(ir));
925 SPFROMREG(ft, MIPSInst_FT(ir));
927 rv.s = (*handler.b) (fs, ft);
934 SPFROMREG(fs, MIPSInst_FS(ir));
935 rv.s = (*handler.u) (fs);
939 if (ieee754_cxtest(IEEE754_INEXACT))
940 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
941 if (ieee754_cxtest(IEEE754_UNDERFLOW))
942 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
943 if (ieee754_cxtest(IEEE754_OVERFLOW))
944 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
945 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
946 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
947 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
948 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
953 return SIGILL; /* not defined */
957 SPFROMREG(fs, MIPSInst_FS(ir));
958 rv.d = ieee754dp_fsp(fs);
965 SPFROMREG(fs, MIPSInst_FS(ir));
966 rv.w = ieee754sp_tint(fs);
971 #if __mips >= 2 || defined(__mips64)
976 unsigned int oldrm = ieee754_csr.rm;
979 SPFROMREG(fs, MIPSInst_FS(ir));
980 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
981 rv.w = ieee754sp_tint(fs);
982 ieee754_csr.rm = oldrm;
986 #endif /* __mips >= 2 */
988 #if defined(__mips64)
992 SPFROMREG(fs, MIPSInst_FS(ir));
993 rv.l = ieee754sp_tlong(fs);
1002 unsigned int oldrm = ieee754_csr.rm;
1005 SPFROMREG(fs, MIPSInst_FS(ir));
1006 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1007 rv.l = ieee754sp_tlong(fs);
1008 ieee754_csr.rm = oldrm;
1012 #endif /* defined(__mips64) */
1015 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1016 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1019 SPFROMREG(fs, MIPSInst_FS(ir));
1020 SPFROMREG(ft, MIPSInst_FT(ir));
1021 rv.w = ieee754sp_cmp(fs, ft,
1022 cmptab[cmpop & 0x7], cmpop & 0x8);
1024 if ((cmpop & 0x8) && ieee754_cxtest
1025 (IEEE754_INVALID_OPERATION))
1026 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1041 ieee754dp(*b) (ieee754dp, ieee754dp);
1042 ieee754dp(*u) (ieee754dp);
1045 switch (MIPSInst_FUNC(ir)) {
1048 handler.b = ieee754dp_add;
1051 handler.b = ieee754dp_sub;
1054 handler.b = ieee754dp_mul;
1057 handler.b = ieee754dp_div;
1061 #if __mips >= 2 || defined(__mips64)
1063 handler.u = ieee754dp_sqrt;
1066 #if __mips >= 4 && __mips != 32
1068 handler.u = fpemu_dp_rsqrt;
1071 handler.u = fpemu_dp_recip;
1076 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1077 if (((ctx->fcr31 & cond) != 0) !=
1078 ((MIPSInst_FT(ir) & 1) != 0))
1080 DPFROMREG(rv.d, MIPSInst_FS(ir));
1083 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1085 DPFROMREG(rv.d, MIPSInst_FS(ir));
1088 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1090 DPFROMREG(rv.d, MIPSInst_FS(ir));
1094 handler.u = ieee754dp_abs;
1098 handler.u = ieee754dp_neg;
1103 DPFROMREG(rv.d, MIPSInst_FS(ir));
1106 /* binary op on handler */
1110 DPFROMREG(fs, MIPSInst_FS(ir));
1111 DPFROMREG(ft, MIPSInst_FT(ir));
1113 rv.d = (*handler.b) (fs, ft);
1119 DPFROMREG(fs, MIPSInst_FS(ir));
1120 rv.d = (*handler.u) (fs);
1124 /* unary conv ops */
1128 DPFROMREG(fs, MIPSInst_FS(ir));
1129 rv.s = ieee754sp_fdp(fs);
1134 return SIGILL; /* not defined */
1139 DPFROMREG(fs, MIPSInst_FS(ir));
1140 rv.w = ieee754dp_tint(fs); /* wrong */
1145 #if __mips >= 2 || defined(__mips64)
1150 unsigned int oldrm = ieee754_csr.rm;
1153 DPFROMREG(fs, MIPSInst_FS(ir));
1154 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1155 rv.w = ieee754dp_tint(fs);
1156 ieee754_csr.rm = oldrm;
1162 #if defined(__mips64)
1166 DPFROMREG(fs, MIPSInst_FS(ir));
1167 rv.l = ieee754dp_tlong(fs);
1176 unsigned int oldrm = ieee754_csr.rm;
1179 DPFROMREG(fs, MIPSInst_FS(ir));
1180 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1181 rv.l = ieee754dp_tlong(fs);
1182 ieee754_csr.rm = oldrm;
1186 #endif /* __mips >= 3 */
1189 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1190 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1193 DPFROMREG(fs, MIPSInst_FS(ir));
1194 DPFROMREG(ft, MIPSInst_FT(ir));
1195 rv.w = ieee754dp_cmp(fs, ft,
1196 cmptab[cmpop & 0x7], cmpop & 0x8);
1201 (IEEE754_INVALID_OPERATION))
1202 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1218 switch (MIPSInst_FUNC(ir)) {
1220 /* convert word to single precision real */
1221 SPFROMREG(fs, MIPSInst_FS(ir));
1222 rv.s = ieee754sp_fint(fs.bits);
1226 /* convert word to double precision real */
1227 SPFROMREG(fs, MIPSInst_FS(ir));
1228 rv.d = ieee754dp_fint(fs.bits);
1237 #if defined(__mips64)
1239 switch (MIPSInst_FUNC(ir)) {
1241 /* convert long to single precision real */
1242 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1246 /* convert long to double precision real */
1247 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1262 * Update the fpu CSR register for this operation.
1263 * If an exception is required, generate a tidy SIGFPE exception,
1264 * without updating the result register.
1265 * Note: cause exception bits do not accumulate, they are rewritten
1266 * for each op; only the flag/sticky bits accumulate.
1268 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1269 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1270 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1275 * Now we can safely write the result back to the register file.
1280 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1282 cond = FPU_CSR_COND;
1287 ctx->fcr31 &= ~cond;
1291 DPTOREG(rv.d, MIPSInst_FD(ir));
1294 SPTOREG(rv.s, MIPSInst_FD(ir));
1297 SITOREG(rv.w, MIPSInst_FD(ir));
1299 #if defined(__mips64)
1301 DITOREG(rv.l, MIPSInst_FD(ir));
1311 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1312 int has_fpu, void *__user *fault_addr)
1314 unsigned long oldepc, prevepc;
1315 mips_instruction insn;
1318 oldepc = xcp->cp0_epc;
1320 prevepc = xcp->cp0_epc;
1322 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
1323 MIPS_FPU_EMU_INC_STATS(errors);
1324 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1327 if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1328 MIPS_FPU_EMU_INC_STATS(errors);
1329 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1333 xcp->cp0_epc += 4; /* skip nops */
1336 * The 'ieee754_csr' is an alias of
1337 * ctx->fcr31. No need to copy ctx->fcr31 to
1338 * ieee754_csr. But ieee754_csr.rm is ieee
1339 * library modes. (not mips rounding mode)
1341 /* convert to ieee library modes */
1342 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1343 sig = cop1Emulate(xcp, ctx, fault_addr);
1344 /* revert to mips rounding mode */
1345 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1354 } while (xcp->cp0_epc > prevepc);
1356 /* SIGILL indicates a non-fpu instruction */
1357 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1358 /* but if epc has advanced, then ignore it */
1364 #ifdef CONFIG_DEBUG_FS
1366 static int fpuemu_stat_get(void *data, u64 *val)
1369 unsigned long sum = 0;
1370 for_each_online_cpu(cpu) {
1371 struct mips_fpu_emulator_stats *ps;
1373 ps = &per_cpu(fpuemustats, cpu);
1374 pv = (void *)ps + (unsigned long)data;
1375 sum += local_read(pv);
1380 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1382 extern struct dentry *mips_debugfs_dir;
1383 static int __init debugfs_fpuemu(void)
1385 struct dentry *d, *dir;
1387 if (!mips_debugfs_dir)
1389 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1393 #define FPU_STAT_CREATE(M) \
1395 d = debugfs_create_file(#M , S_IRUGO, dir, \
1396 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1397 &fops_fpuemu_stat); \
1402 FPU_STAT_CREATE(emulated);
1403 FPU_STAT_CREATE(loads);
1404 FPU_STAT_CREATE(stores);
1405 FPU_STAT_CREATE(cp1ops);
1406 FPU_STAT_CREATE(cp1xops);
1407 FPU_STAT_CREATE(errors);
1411 __initcall(debugfs_fpuemu);