2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39 #include <linux/perf_event.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
49 #include <asm/uaccess.h>
50 #include <asm/branch.h>
54 /* Strap kernel emulator for full MIPS IV emulation */
61 /* Function which emulates a floating point instruction. */
63 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
66 #if __mips >= 4 && __mips != 32
67 static int fpux_emu(struct pt_regs *,
68 struct mips_fpu_struct *, mips_instruction, void *__user *);
71 /* Further private data for which no space exists in mips_fpu_struct */
73 #ifdef CONFIG_DEBUG_FS
74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
77 /* Control registers */
79 #define FPCREG_RID 0 /* $0 = revision id */
80 #define FPCREG_CSR 31 /* $31 = csr */
82 /* Determine rounding mode from the RM bits of the FCSR */
83 #define modeindex(v) ((v) & FPU_CSR_RM)
85 /* microMIPS bitfields */
86 #define MM_POOL32A_MINOR_MASK 0x3f
87 #define MM_POOL32A_MINOR_SHIFT 0x6
88 #define MM_MIPS32_COND_FC 0x30
90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
91 static const unsigned char ieee_rm[4] = {
92 [FPU_CSR_RN] = IEEE754_RN,
93 [FPU_CSR_RZ] = IEEE754_RZ,
94 [FPU_CSR_RU] = IEEE754_RU,
95 [FPU_CSR_RD] = IEEE754_RD,
97 /* Convert IEEE library modes to Mips rounding mode (0..3). */
98 static const unsigned char mips_rm[4] = {
99 [IEEE754_RN] = FPU_CSR_RN,
100 [IEEE754_RZ] = FPU_CSR_RZ,
101 [IEEE754_RD] = FPU_CSR_RD,
102 [IEEE754_RU] = FPU_CSR_RU,
106 /* convert condition code register number to csr bit */
107 static const unsigned int fpucondbit[8] = {
119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
120 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
123 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
124 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
125 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
126 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
129 * This functions translates a 32-bit microMIPS instruction
130 * into a 32-bit MIPS32 instruction. Returns 0 on success
131 * and SIGILL otherwise.
133 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
135 union mips_instruction insn = *insn_ptr;
136 union mips_instruction mips32_insn = insn;
139 switch (insn.mm_i_format.opcode) {
141 mips32_insn.mm_i_format.opcode = ldc1_op;
142 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
143 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
146 mips32_insn.mm_i_format.opcode = lwc1_op;
147 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
148 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
151 mips32_insn.mm_i_format.opcode = sdc1_op;
152 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
153 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
156 mips32_insn.mm_i_format.opcode = swc1_op;
157 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
158 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
161 /* NOTE: offset is << by 1 if in microMIPS mode. */
162 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
163 (insn.mm_i_format.rt == mm_bc1t_op)) {
164 mips32_insn.fb_format.opcode = cop1_op;
165 mips32_insn.fb_format.bc = bc_op;
166 mips32_insn.fb_format.flag =
167 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
172 switch (insn.mm_fp0_format.func) {
181 op = insn.mm_fp0_format.func;
182 if (op == mm_32f_01_op)
184 else if (op == mm_32f_11_op)
186 else if (op == mm_32f_02_op)
188 else if (op == mm_32f_12_op)
190 else if (op == mm_32f_41_op)
192 else if (op == mm_32f_51_op)
194 else if (op == mm_32f_42_op)
198 mips32_insn.fp6_format.opcode = cop1x_op;
199 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
200 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
201 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
202 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
203 mips32_insn.fp6_format.func = func;
206 func = -1; /* Invalid */
207 op = insn.mm_fp5_format.op & 0x7;
208 if (op == mm_ldxc1_op)
210 else if (op == mm_sdxc1_op)
212 else if (op == mm_lwxc1_op)
214 else if (op == mm_swxc1_op)
218 mips32_insn.r_format.opcode = cop1x_op;
219 mips32_insn.r_format.rs =
220 insn.mm_fp5_format.base;
221 mips32_insn.r_format.rt =
222 insn.mm_fp5_format.index;
223 mips32_insn.r_format.rd = 0;
224 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
225 mips32_insn.r_format.func = func;
230 op = -1; /* Invalid */
231 if (insn.mm_fp2_format.op == mm_fmovt_op)
233 else if (insn.mm_fp2_format.op == mm_fmovf_op)
236 mips32_insn.fp0_format.opcode = cop1_op;
237 mips32_insn.fp0_format.fmt =
238 sdps_format[insn.mm_fp2_format.fmt];
239 mips32_insn.fp0_format.ft =
240 (insn.mm_fp2_format.cc<<2) + op;
241 mips32_insn.fp0_format.fs =
242 insn.mm_fp2_format.fs;
243 mips32_insn.fp0_format.fd =
244 insn.mm_fp2_format.fd;
245 mips32_insn.fp0_format.func = fmovc_op;
250 func = -1; /* Invalid */
251 if (insn.mm_fp0_format.op == mm_fadd_op)
253 else if (insn.mm_fp0_format.op == mm_fsub_op)
255 else if (insn.mm_fp0_format.op == mm_fmul_op)
257 else if (insn.mm_fp0_format.op == mm_fdiv_op)
260 mips32_insn.fp0_format.opcode = cop1_op;
261 mips32_insn.fp0_format.fmt =
262 sdps_format[insn.mm_fp0_format.fmt];
263 mips32_insn.fp0_format.ft =
264 insn.mm_fp0_format.ft;
265 mips32_insn.fp0_format.fs =
266 insn.mm_fp0_format.fs;
267 mips32_insn.fp0_format.fd =
268 insn.mm_fp0_format.fd;
269 mips32_insn.fp0_format.func = func;
274 func = -1; /* Invalid */
275 if (insn.mm_fp0_format.op == mm_fmovn_op)
277 else if (insn.mm_fp0_format.op == mm_fmovz_op)
280 mips32_insn.fp0_format.opcode = cop1_op;
281 mips32_insn.fp0_format.fmt =
282 sdps_format[insn.mm_fp0_format.fmt];
283 mips32_insn.fp0_format.ft =
284 insn.mm_fp0_format.ft;
285 mips32_insn.fp0_format.fs =
286 insn.mm_fp0_format.fs;
287 mips32_insn.fp0_format.fd =
288 insn.mm_fp0_format.fd;
289 mips32_insn.fp0_format.func = func;
293 case mm_32f_73_op: /* POOL32FXF */
294 switch (insn.mm_fp1_format.op) {
299 if ((insn.mm_fp1_format.op & 0x7f) ==
304 mips32_insn.r_format.opcode = spec_op;
305 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
306 mips32_insn.r_format.rt =
307 (insn.mm_fp4_format.cc << 2) + op;
308 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
309 mips32_insn.r_format.re = 0;
310 mips32_insn.r_format.func = movc_op;
316 if ((insn.mm_fp1_format.op & 0x7f) ==
319 fmt = swl_format[insn.mm_fp3_format.fmt];
322 fmt = dwl_format[insn.mm_fp3_format.fmt];
324 mips32_insn.fp0_format.opcode = cop1_op;
325 mips32_insn.fp0_format.fmt = fmt;
326 mips32_insn.fp0_format.ft = 0;
327 mips32_insn.fp0_format.fs =
328 insn.mm_fp3_format.fs;
329 mips32_insn.fp0_format.fd =
330 insn.mm_fp3_format.rt;
331 mips32_insn.fp0_format.func = func;
339 if ((insn.mm_fp1_format.op & 0x7f) ==
342 else if ((insn.mm_fp1_format.op & 0x7f) ==
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sdps_format[insn.mm_fp3_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp3_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp3_format.rt;
355 mips32_insn.fp0_format.func = func;
367 if (insn.mm_fp1_format.op == mm_ffloorl_op)
369 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
371 else if (insn.mm_fp1_format.op == mm_fceill_op)
373 else if (insn.mm_fp1_format.op == mm_fceilw_op)
375 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
377 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
379 else if (insn.mm_fp1_format.op == mm_froundl_op)
381 else if (insn.mm_fp1_format.op == mm_froundw_op)
383 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
387 mips32_insn.fp0_format.opcode = cop1_op;
388 mips32_insn.fp0_format.fmt =
389 sd_format[insn.mm_fp1_format.fmt];
390 mips32_insn.fp0_format.ft = 0;
391 mips32_insn.fp0_format.fs =
392 insn.mm_fp1_format.fs;
393 mips32_insn.fp0_format.fd =
394 insn.mm_fp1_format.rt;
395 mips32_insn.fp0_format.func = func;
400 if (insn.mm_fp1_format.op == mm_frsqrt_op)
402 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
406 mips32_insn.fp0_format.opcode = cop1_op;
407 mips32_insn.fp0_format.fmt =
408 sdps_format[insn.mm_fp1_format.fmt];
409 mips32_insn.fp0_format.ft = 0;
410 mips32_insn.fp0_format.fs =
411 insn.mm_fp1_format.fs;
412 mips32_insn.fp0_format.fd =
413 insn.mm_fp1_format.rt;
414 mips32_insn.fp0_format.func = func;
420 if (insn.mm_fp1_format.op == mm_mfc1_op)
422 else if (insn.mm_fp1_format.op == mm_mtc1_op)
424 else if (insn.mm_fp1_format.op == mm_cfc1_op)
428 mips32_insn.fp1_format.opcode = cop1_op;
429 mips32_insn.fp1_format.op = op;
430 mips32_insn.fp1_format.rt =
431 insn.mm_fp1_format.rt;
432 mips32_insn.fp1_format.fs =
433 insn.mm_fp1_format.fs;
434 mips32_insn.fp1_format.fd = 0;
435 mips32_insn.fp1_format.func = 0;
442 case mm_32f_74_op: /* c.cond.fmt */
443 mips32_insn.fp0_format.opcode = cop1_op;
444 mips32_insn.fp0_format.fmt =
445 sdps_format[insn.mm_fp4_format.fmt];
446 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
447 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
448 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
449 mips32_insn.fp0_format.func =
450 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
462 *insn_ptr = mips32_insn;
466 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
467 unsigned long *contpc)
469 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
477 switch (insn.mm_i_format.opcode) {
479 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
481 switch (insn.mm_i_format.simmediate >>
482 MM_POOL32A_MINOR_SHIFT) {
487 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
488 regs->regs[insn.mm_i_format.rt] =
491 dec_insn.next_pc_inc;
492 *contpc = regs->regs[insn.mm_i_format.rs];
499 switch (insn.mm_i_format.rt) {
502 regs->regs[31] = regs->cp0_epc +
504 dec_insn.next_pc_inc;
507 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
508 *contpc = regs->cp0_epc +
510 (insn.mm_i_format.simmediate << 1);
512 *contpc = regs->cp0_epc +
514 dec_insn.next_pc_inc;
519 regs->regs[31] = regs->cp0_epc +
521 dec_insn.next_pc_inc;
524 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
525 *contpc = regs->cp0_epc +
527 (insn.mm_i_format.simmediate << 1);
529 *contpc = regs->cp0_epc +
531 dec_insn.next_pc_inc;
535 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
536 *contpc = regs->cp0_epc +
538 (insn.mm_i_format.simmediate << 1);
540 *contpc = regs->cp0_epc +
542 dec_insn.next_pc_inc;
546 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
547 *contpc = regs->cp0_epc +
549 (insn.mm_i_format.simmediate << 1);
551 *contpc = regs->cp0_epc +
553 dec_insn.next_pc_inc;
564 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
566 fcr31 = current->thread.fpu.fcr31;
572 bit = (insn.mm_i_format.rs >> 2);
575 if (fcr31 & (1 << bit))
576 *contpc = regs->cp0_epc +
578 (insn.mm_i_format.simmediate << 1);
580 *contpc = regs->cp0_epc +
581 dec_insn.pc_inc + dec_insn.next_pc_inc;
587 switch (insn.mm_i_format.rt) {
590 regs->regs[31] = regs->cp0_epc +
591 dec_insn.pc_inc + dec_insn.next_pc_inc;
594 *contpc = regs->regs[insn.mm_i_format.rs];
600 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
601 *contpc = regs->cp0_epc +
603 (insn.mm_b1_format.simmediate << 1);
605 *contpc = regs->cp0_epc +
606 dec_insn.pc_inc + dec_insn.next_pc_inc;
610 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
611 *contpc = regs->cp0_epc +
613 (insn.mm_b1_format.simmediate << 1);
615 *contpc = regs->cp0_epc +
616 dec_insn.pc_inc + dec_insn.next_pc_inc;
620 *contpc = regs->cp0_epc + dec_insn.pc_inc +
621 (insn.mm_b0_format.simmediate << 1);
625 if (regs->regs[insn.mm_i_format.rs] ==
626 regs->regs[insn.mm_i_format.rt])
627 *contpc = regs->cp0_epc +
629 (insn.mm_i_format.simmediate << 1);
631 *contpc = regs->cp0_epc +
633 dec_insn.next_pc_inc;
637 if (regs->regs[insn.mm_i_format.rs] !=
638 regs->regs[insn.mm_i_format.rt])
639 *contpc = regs->cp0_epc +
641 (insn.mm_i_format.simmediate << 1);
643 *contpc = regs->cp0_epc +
644 dec_insn.pc_inc + dec_insn.next_pc_inc;
648 regs->regs[31] = regs->cp0_epc +
649 dec_insn.pc_inc + dec_insn.next_pc_inc;
650 *contpc = regs->cp0_epc + dec_insn.pc_inc;
653 *contpc |= (insn.j_format.target << 2);
658 regs->regs[31] = regs->cp0_epc +
659 dec_insn.pc_inc + dec_insn.next_pc_inc;
662 *contpc = regs->cp0_epc + dec_insn.pc_inc;
665 *contpc |= (insn.j_format.target << 1);
666 set_isa16_mode(*contpc);
674 * Redundant with logic already in kernel/branch.c,
675 * embedded in compute_return_epc. At some point,
676 * a single subroutine should be used across both
679 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
680 unsigned long *contpc)
682 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
684 unsigned int bit = 0;
686 switch (insn.i_format.opcode) {
688 switch (insn.r_format.func) {
690 regs->regs[insn.r_format.rd] =
691 regs->cp0_epc + dec_insn.pc_inc +
692 dec_insn.next_pc_inc;
695 *contpc = regs->regs[insn.r_format.rs];
701 switch (insn.i_format.rt) {
704 regs->regs[31] = regs->cp0_epc +
706 dec_insn.next_pc_inc;
710 if ((long)regs->regs[insn.i_format.rs] < 0)
711 *contpc = regs->cp0_epc +
713 (insn.i_format.simmediate << 2);
715 *contpc = regs->cp0_epc +
717 dec_insn.next_pc_inc;
722 regs->regs[31] = regs->cp0_epc +
724 dec_insn.next_pc_inc;
728 if ((long)regs->regs[insn.i_format.rs] >= 0)
729 *contpc = regs->cp0_epc +
731 (insn.i_format.simmediate << 2);
733 *contpc = regs->cp0_epc +
735 dec_insn.next_pc_inc;
743 regs->regs[31] = regs->cp0_epc +
745 dec_insn.next_pc_inc;
748 *contpc = regs->cp0_epc + dec_insn.pc_inc;
751 *contpc |= (insn.j_format.target << 2);
752 /* Set microMIPS mode bit: XOR for jalx. */
758 if (regs->regs[insn.i_format.rs] ==
759 regs->regs[insn.i_format.rt])
760 *contpc = regs->cp0_epc +
762 (insn.i_format.simmediate << 2);
764 *contpc = regs->cp0_epc +
766 dec_insn.next_pc_inc;
771 if (regs->regs[insn.i_format.rs] !=
772 regs->regs[insn.i_format.rt])
773 *contpc = regs->cp0_epc +
775 (insn.i_format.simmediate << 2);
777 *contpc = regs->cp0_epc +
779 dec_insn.next_pc_inc;
784 if ((long)regs->regs[insn.i_format.rs] <= 0)
785 *contpc = regs->cp0_epc +
787 (insn.i_format.simmediate << 2);
789 *contpc = regs->cp0_epc +
791 dec_insn.next_pc_inc;
796 if ((long)regs->regs[insn.i_format.rs] > 0)
797 *contpc = regs->cp0_epc +
799 (insn.i_format.simmediate << 2);
801 *contpc = regs->cp0_epc +
803 dec_insn.next_pc_inc;
810 if (insn.i_format.rs == bc_op) {
813 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
815 fcr31 = current->thread.fpu.fcr31;
818 bit = (insn.i_format.rt >> 2);
821 switch (insn.i_format.rt & 3) {
824 if (~fcr31 & (1 << bit))
825 *contpc = regs->cp0_epc +
827 (insn.i_format.simmediate << 2);
829 *contpc = regs->cp0_epc +
831 dec_insn.next_pc_inc;
836 if (fcr31 & (1 << bit))
837 *contpc = regs->cp0_epc +
839 (insn.i_format.simmediate << 2);
841 *contpc = regs->cp0_epc +
843 dec_insn.next_pc_inc;
854 * In the Linux kernel, we support selection of FPR format on the
855 * basis of the Status.FR bit. If an FPU is not present, the FR bit
856 * is hardwired to zero, which would imply a 32-bit FPU even for
857 * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
858 * FPU emu is slow and bulky and optimizing this function offers fairly
859 * sizeable benefits so we try to be clever and make this function return
860 * a constant whenever possible, that is on 64-bit kernels without O32
861 * compatibility enabled and on 32-bit kernels.
863 static inline int cop1_64bit(struct pt_regs *xcp)
865 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
867 #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
868 return !test_thread_flag(TIF_32BIT_REGS);
874 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
875 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
877 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
878 cop1_64bit(xcp) || !(x & 1) ? \
879 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
880 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
882 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
883 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
885 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
886 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
887 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
888 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
891 * Emulate the single floating point instruction pointed at by EPC.
892 * Two instructions if the instruction is in a branch delay slot.
895 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
896 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
899 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
903 /* XXX NEC Vr54xx bug workaround */
904 if (xcp->cp0_cause & CAUSEF_BD) {
905 if (dec_insn.micro_mips_mode) {
906 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
907 xcp->cp0_cause &= ~CAUSEF_BD;
909 if (!isBranchInstr(xcp, dec_insn, &contpc))
910 xcp->cp0_cause &= ~CAUSEF_BD;
914 if (xcp->cp0_cause & CAUSEF_BD) {
916 * The instruction to be emulated is in a branch delay slot
917 * which means that we have to emulate the branch instruction
918 * BEFORE we do the cop1 instruction.
920 * This branch could be a COP1 branch, but in that case we
921 * would have had a trap for that instruction, and would not
922 * come through this route.
924 * Linux MIPS branch emulator operates on context, updating the
927 ir = dec_insn.next_insn; /* process delay slot instr */
928 pc_inc = dec_insn.next_pc_inc;
930 ir = dec_insn.insn; /* process current instr */
931 pc_inc = dec_insn.pc_inc;
935 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
936 * instructions, we want to convert microMIPS FPU instructions
937 * into MIPS32 instructions so that we could reuse all of the
938 * FPU emulation code.
940 * NOTE: We cannot do this for branch instructions since they
941 * are not a subset. Example: Cannot emulate a 16-bit
942 * aligned target address with a MIPS32 instruction.
944 if (dec_insn.micro_mips_mode) {
946 * If next instruction is a 16-bit instruction, then it
947 * it cannot be a FPU instruction. This could happen
948 * since we can be called for non-FPU instructions.
951 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
957 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
958 MIPS_FPU_EMU_INC_STATS(emulated);
959 switch (MIPSInst_OPCODE(ir)) {
961 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
965 MIPS_FPU_EMU_INC_STATS(loads);
967 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
968 MIPS_FPU_EMU_INC_STATS(errors);
972 if (__get_user(val, va)) {
973 MIPS_FPU_EMU_INC_STATS(errors);
977 DITOREG(val, MIPSInst_RT(ir));
982 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
986 MIPS_FPU_EMU_INC_STATS(stores);
987 DIFROMREG(val, MIPSInst_RT(ir));
988 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
989 MIPS_FPU_EMU_INC_STATS(errors);
993 if (__put_user(val, va)) {
994 MIPS_FPU_EMU_INC_STATS(errors);
1002 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1006 MIPS_FPU_EMU_INC_STATS(loads);
1007 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1008 MIPS_FPU_EMU_INC_STATS(errors);
1012 if (__get_user(val, va)) {
1013 MIPS_FPU_EMU_INC_STATS(errors);
1017 SITOREG(val, MIPSInst_RT(ir));
1022 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1026 MIPS_FPU_EMU_INC_STATS(stores);
1027 SIFROMREG(val, MIPSInst_RT(ir));
1028 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1029 MIPS_FPU_EMU_INC_STATS(errors);
1033 if (__put_user(val, va)) {
1034 MIPS_FPU_EMU_INC_STATS(errors);
1042 switch (MIPSInst_RS(ir)) {
1044 #if defined(__mips64)
1046 /* copregister fs -> gpr[rt] */
1047 if (MIPSInst_RT(ir) != 0) {
1048 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1054 /* copregister fs <- rt */
1055 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1060 /* copregister rd -> gpr[rt] */
1061 if (MIPSInst_RT(ir) != 0) {
1062 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1068 /* copregister rd <- rt */
1069 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1073 /* cop control register rd -> gpr[rt] */
1076 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1078 value = (value & ~FPU_CSR_RM) |
1079 mips_rm[modeindex(value)];
1081 printk("%p gpr[%d]<-csr=%08x\n",
1082 (void *) (xcp->cp0_epc),
1083 MIPSInst_RT(ir), value);
1086 else if (MIPSInst_RD(ir) == FPCREG_RID)
1090 if (MIPSInst_RT(ir))
1091 xcp->regs[MIPSInst_RT(ir)] = value;
1096 /* copregister rd <- rt */
1099 if (MIPSInst_RT(ir) == 0)
1102 value = xcp->regs[MIPSInst_RT(ir)];
1104 /* we only have one writable control reg
1106 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1108 printk("%p gpr[%d]->csr=%08x\n",
1109 (void *) (xcp->cp0_epc),
1110 MIPSInst_RT(ir), value);
1114 * Don't write reserved bits,
1115 * and convert to ieee library modes
1117 ctx->fcr31 = (value &
1118 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1119 ieee_rm[modeindex(value)];
1121 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1130 if (xcp->cp0_cause & CAUSEF_BD)
1134 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1136 cond = ctx->fcr31 & FPU_CSR_COND;
1138 switch (MIPSInst_RT(ir) & 3) {
1149 /* thats an illegal instruction */
1153 xcp->cp0_cause |= CAUSEF_BD;
1155 /* branch taken: emulate dslot
1158 xcp->cp0_epc += dec_insn.pc_inc;
1160 contpc = MIPSInst_SIMM(ir);
1161 ir = dec_insn.next_insn;
1162 if (dec_insn.micro_mips_mode) {
1163 contpc = (xcp->cp0_epc + (contpc << 1));
1165 /* If 16-bit instruction, not FPU. */
1166 if ((dec_insn.next_pc_inc == 2) ||
1167 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1170 * Since this instruction will
1171 * be put on the stack with
1172 * 32-bit words, get around
1173 * this problem by putting a
1174 * NOP16 as the second one.
1176 if (dec_insn.next_pc_inc == 2)
1177 ir = (ir & (~0xffff)) | MM_NOP16;
1180 * Single step the non-CP1
1181 * instruction in the dslot.
1183 return mips_dsemul(xcp, ir, contpc);
1186 contpc = (xcp->cp0_epc + (contpc << 2));
1188 switch (MIPSInst_OPCODE(ir)) {
1191 #if (__mips >= 2 || defined(__mips64))
1196 #if __mips >= 4 && __mips != 32
1199 /* its one of ours */
1203 if (MIPSInst_FUNC(ir) == movc_op)
1210 * Single step the non-cp1
1211 * instruction in the dslot
1213 return mips_dsemul(xcp, ir, contpc);
1216 /* branch not taken */
1219 * branch likely nullifies
1220 * dslot if not taken
1222 xcp->cp0_epc += dec_insn.pc_inc;
1223 contpc += dec_insn.pc_inc;
1225 * else continue & execute
1226 * dslot as normal insn
1234 if (!(MIPSInst_RS(ir) & 0x10))
1239 /* a real fpu computation instruction */
1240 if ((sig = fpu_emu(xcp, ctx, ir)))
1246 #if __mips >= 4 && __mips != 32
1248 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1257 if (MIPSInst_FUNC(ir) != movc_op)
1259 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1260 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1261 xcp->regs[MIPSInst_RD(ir)] =
1262 xcp->regs[MIPSInst_RS(ir)];
1271 xcp->cp0_epc = contpc;
1272 xcp->cp0_cause &= ~CAUSEF_BD;
1278 * Conversion table from MIPS compare ops 48-63
1279 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1281 static const unsigned char cmptab[8] = {
1282 0, /* cmp_0 (sig) cmp_sf */
1283 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1284 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1285 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1286 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1287 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1288 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1289 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1293 #if __mips >= 4 && __mips != 32
1296 * Additional MIPS4 instructions
1299 #define DEF3OP(name, p, f1, f2, f3) \
1300 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1303 struct _ieee754_csr ieee754_csr_save; \
1305 ieee754_csr_save = ieee754_csr; \
1307 ieee754_csr_save.cx |= ieee754_csr.cx; \
1308 ieee754_csr_save.sx |= ieee754_csr.sx; \
1310 ieee754_csr.cx |= ieee754_csr_save.cx; \
1311 ieee754_csr.sx |= ieee754_csr_save.sx; \
1315 static ieee754dp fpemu_dp_recip(ieee754dp d)
1317 return ieee754dp_div(ieee754dp_one(0), d);
1320 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
1322 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1325 static ieee754sp fpemu_sp_recip(ieee754sp s)
1327 return ieee754sp_div(ieee754sp_one(0), s);
1330 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
1332 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1335 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1336 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1337 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1338 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1339 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1340 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1341 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1342 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1344 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1345 mips_instruction ir, void *__user *fault_addr)
1347 unsigned rcsr = 0; /* resulting csr */
1349 MIPS_FPU_EMU_INC_STATS(cp1xops);
1351 switch (MIPSInst_FMA_FFMT(ir)) {
1352 case s_fmt:{ /* 0 */
1354 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
1355 ieee754sp fd, fr, fs, ft;
1359 switch (MIPSInst_FUNC(ir)) {
1361 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1362 xcp->regs[MIPSInst_FT(ir)]);
1364 MIPS_FPU_EMU_INC_STATS(loads);
1365 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1366 MIPS_FPU_EMU_INC_STATS(errors);
1370 if (__get_user(val, va)) {
1371 MIPS_FPU_EMU_INC_STATS(errors);
1375 SITOREG(val, MIPSInst_FD(ir));
1379 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1380 xcp->regs[MIPSInst_FT(ir)]);
1382 MIPS_FPU_EMU_INC_STATS(stores);
1384 SIFROMREG(val, MIPSInst_FS(ir));
1385 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1386 MIPS_FPU_EMU_INC_STATS(errors);
1390 if (put_user(val, va)) {
1391 MIPS_FPU_EMU_INC_STATS(errors);
1398 handler = fpemu_sp_madd;
1401 handler = fpemu_sp_msub;
1404 handler = fpemu_sp_nmadd;
1407 handler = fpemu_sp_nmsub;
1411 SPFROMREG(fr, MIPSInst_FR(ir));
1412 SPFROMREG(fs, MIPSInst_FS(ir));
1413 SPFROMREG(ft, MIPSInst_FT(ir));
1414 fd = (*handler) (fr, fs, ft);
1415 SPTOREG(fd, MIPSInst_FD(ir));
1418 if (ieee754_cxtest(IEEE754_INEXACT))
1419 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1420 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1421 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1422 if (ieee754_cxtest(IEEE754_OVERFLOW))
1423 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1424 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1425 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1427 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1428 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1429 /*printk ("SIGFPE: fpu csr = %08x\n",
1442 case d_fmt:{ /* 1 */
1443 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
1444 ieee754dp fd, fr, fs, ft;
1448 switch (MIPSInst_FUNC(ir)) {
1450 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1451 xcp->regs[MIPSInst_FT(ir)]);
1453 MIPS_FPU_EMU_INC_STATS(loads);
1454 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1455 MIPS_FPU_EMU_INC_STATS(errors);
1459 if (__get_user(val, va)) {
1460 MIPS_FPU_EMU_INC_STATS(errors);
1464 DITOREG(val, MIPSInst_FD(ir));
1468 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1469 xcp->regs[MIPSInst_FT(ir)]);
1471 MIPS_FPU_EMU_INC_STATS(stores);
1472 DIFROMREG(val, MIPSInst_FS(ir));
1473 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1474 MIPS_FPU_EMU_INC_STATS(errors);
1478 if (__put_user(val, va)) {
1479 MIPS_FPU_EMU_INC_STATS(errors);
1486 handler = fpemu_dp_madd;
1489 handler = fpemu_dp_msub;
1492 handler = fpemu_dp_nmadd;
1495 handler = fpemu_dp_nmsub;
1499 DPFROMREG(fr, MIPSInst_FR(ir));
1500 DPFROMREG(fs, MIPSInst_FS(ir));
1501 DPFROMREG(ft, MIPSInst_FT(ir));
1502 fd = (*handler) (fr, fs, ft);
1503 DPTOREG(fd, MIPSInst_FD(ir));
1513 if (MIPSInst_FUNC(ir) != pfetch_op) {
1516 /* ignore prefx operation */
1530 * Emulate a single COP1 arithmetic instruction.
1532 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1533 mips_instruction ir)
1535 int rfmt; /* resulting format */
1536 unsigned rcsr = 0; /* resulting csr */
1545 } rv; /* resulting value */
1547 MIPS_FPU_EMU_INC_STATS(cp1ops);
1548 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1549 case s_fmt:{ /* 0 */
1551 ieee754sp(*b) (ieee754sp, ieee754sp);
1552 ieee754sp(*u) (ieee754sp);
1555 switch (MIPSInst_FUNC(ir)) {
1558 handler.b = ieee754sp_add;
1561 handler.b = ieee754sp_sub;
1564 handler.b = ieee754sp_mul;
1567 handler.b = ieee754sp_div;
1571 #if __mips >= 2 || defined(__mips64)
1573 handler.u = ieee754sp_sqrt;
1576 #if __mips >= 4 && __mips != 32
1578 handler.u = fpemu_sp_rsqrt;
1581 handler.u = fpemu_sp_recip;
1586 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1587 if (((ctx->fcr31 & cond) != 0) !=
1588 ((MIPSInst_FT(ir) & 1) != 0))
1590 SPFROMREG(rv.s, MIPSInst_FS(ir));
1593 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1595 SPFROMREG(rv.s, MIPSInst_FS(ir));
1598 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1600 SPFROMREG(rv.s, MIPSInst_FS(ir));
1604 handler.u = ieee754sp_abs;
1607 handler.u = ieee754sp_neg;
1611 SPFROMREG(rv.s, MIPSInst_FS(ir));
1614 /* binary op on handler */
1619 SPFROMREG(fs, MIPSInst_FS(ir));
1620 SPFROMREG(ft, MIPSInst_FT(ir));
1622 rv.s = (*handler.b) (fs, ft);
1629 SPFROMREG(fs, MIPSInst_FS(ir));
1630 rv.s = (*handler.u) (fs);
1634 if (ieee754_cxtest(IEEE754_INEXACT))
1635 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1636 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1637 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1638 if (ieee754_cxtest(IEEE754_OVERFLOW))
1639 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1640 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1641 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1642 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1643 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1646 /* unary conv ops */
1648 return SIGILL; /* not defined */
1652 SPFROMREG(fs, MIPSInst_FS(ir));
1653 rv.d = ieee754dp_fsp(fs);
1660 SPFROMREG(fs, MIPSInst_FS(ir));
1661 rv.w = ieee754sp_tint(fs);
1666 #if __mips >= 2 || defined(__mips64)
1671 unsigned int oldrm = ieee754_csr.rm;
1674 SPFROMREG(fs, MIPSInst_FS(ir));
1675 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1676 rv.w = ieee754sp_tint(fs);
1677 ieee754_csr.rm = oldrm;
1681 #endif /* __mips >= 2 */
1683 #if defined(__mips64)
1687 SPFROMREG(fs, MIPSInst_FS(ir));
1688 rv.l = ieee754sp_tlong(fs);
1697 unsigned int oldrm = ieee754_csr.rm;
1700 SPFROMREG(fs, MIPSInst_FS(ir));
1701 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1702 rv.l = ieee754sp_tlong(fs);
1703 ieee754_csr.rm = oldrm;
1707 #endif /* defined(__mips64) */
1710 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1711 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1714 SPFROMREG(fs, MIPSInst_FS(ir));
1715 SPFROMREG(ft, MIPSInst_FT(ir));
1716 rv.w = ieee754sp_cmp(fs, ft,
1717 cmptab[cmpop & 0x7], cmpop & 0x8);
1719 if ((cmpop & 0x8) && ieee754_cxtest
1720 (IEEE754_INVALID_OPERATION))
1721 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1736 ieee754dp(*b) (ieee754dp, ieee754dp);
1737 ieee754dp(*u) (ieee754dp);
1740 switch (MIPSInst_FUNC(ir)) {
1743 handler.b = ieee754dp_add;
1746 handler.b = ieee754dp_sub;
1749 handler.b = ieee754dp_mul;
1752 handler.b = ieee754dp_div;
1756 #if __mips >= 2 || defined(__mips64)
1758 handler.u = ieee754dp_sqrt;
1761 #if __mips >= 4 && __mips != 32
1763 handler.u = fpemu_dp_rsqrt;
1766 handler.u = fpemu_dp_recip;
1771 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1772 if (((ctx->fcr31 & cond) != 0) !=
1773 ((MIPSInst_FT(ir) & 1) != 0))
1775 DPFROMREG(rv.d, MIPSInst_FS(ir));
1778 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1780 DPFROMREG(rv.d, MIPSInst_FS(ir));
1783 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1785 DPFROMREG(rv.d, MIPSInst_FS(ir));
1789 handler.u = ieee754dp_abs;
1793 handler.u = ieee754dp_neg;
1798 DPFROMREG(rv.d, MIPSInst_FS(ir));
1801 /* binary op on handler */
1805 DPFROMREG(fs, MIPSInst_FS(ir));
1806 DPFROMREG(ft, MIPSInst_FT(ir));
1808 rv.d = (*handler.b) (fs, ft);
1814 DPFROMREG(fs, MIPSInst_FS(ir));
1815 rv.d = (*handler.u) (fs);
1819 /* unary conv ops */
1823 DPFROMREG(fs, MIPSInst_FS(ir));
1824 rv.s = ieee754sp_fdp(fs);
1829 return SIGILL; /* not defined */
1834 DPFROMREG(fs, MIPSInst_FS(ir));
1835 rv.w = ieee754dp_tint(fs); /* wrong */
1840 #if __mips >= 2 || defined(__mips64)
1845 unsigned int oldrm = ieee754_csr.rm;
1848 DPFROMREG(fs, MIPSInst_FS(ir));
1849 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1850 rv.w = ieee754dp_tint(fs);
1851 ieee754_csr.rm = oldrm;
1857 #if defined(__mips64)
1861 DPFROMREG(fs, MIPSInst_FS(ir));
1862 rv.l = ieee754dp_tlong(fs);
1871 unsigned int oldrm = ieee754_csr.rm;
1874 DPFROMREG(fs, MIPSInst_FS(ir));
1875 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1876 rv.l = ieee754dp_tlong(fs);
1877 ieee754_csr.rm = oldrm;
1881 #endif /* __mips >= 3 */
1884 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1885 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1888 DPFROMREG(fs, MIPSInst_FS(ir));
1889 DPFROMREG(ft, MIPSInst_FT(ir));
1890 rv.w = ieee754dp_cmp(fs, ft,
1891 cmptab[cmpop & 0x7], cmpop & 0x8);
1896 (IEEE754_INVALID_OPERATION))
1897 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1913 switch (MIPSInst_FUNC(ir)) {
1915 /* convert word to single precision real */
1916 SPFROMREG(fs, MIPSInst_FS(ir));
1917 rv.s = ieee754sp_fint(fs.bits);
1921 /* convert word to double precision real */
1922 SPFROMREG(fs, MIPSInst_FS(ir));
1923 rv.d = ieee754dp_fint(fs.bits);
1932 #if defined(__mips64)
1934 switch (MIPSInst_FUNC(ir)) {
1936 /* convert long to single precision real */
1937 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1941 /* convert long to double precision real */
1942 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1957 * Update the fpu CSR register for this operation.
1958 * If an exception is required, generate a tidy SIGFPE exception,
1959 * without updating the result register.
1960 * Note: cause exception bits do not accumulate, they are rewritten
1961 * for each op; only the flag/sticky bits accumulate.
1963 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1964 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1965 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1970 * Now we can safely write the result back to the register file.
1975 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1977 cond = FPU_CSR_COND;
1982 ctx->fcr31 &= ~cond;
1986 DPTOREG(rv.d, MIPSInst_FD(ir));
1989 SPTOREG(rv.s, MIPSInst_FD(ir));
1992 SITOREG(rv.w, MIPSInst_FD(ir));
1994 #if defined(__mips64)
1996 DITOREG(rv.l, MIPSInst_FD(ir));
2006 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2007 int has_fpu, void *__user *fault_addr)
2009 unsigned long oldepc, prevepc;
2010 struct mm_decoded_insn dec_insn;
2015 oldepc = xcp->cp0_epc;
2017 prevepc = xcp->cp0_epc;
2019 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2021 * Get next 2 microMIPS instructions and convert them
2022 * into 32-bit instructions.
2024 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2025 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2026 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2027 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2028 MIPS_FPU_EMU_INC_STATS(errors);
2033 /* Get first instruction. */
2034 if (mm_insn_16bit(*instr_ptr)) {
2035 /* Duplicate the half-word. */
2036 dec_insn.insn = (*instr_ptr << 16) |
2038 /* 16-bit instruction. */
2039 dec_insn.pc_inc = 2;
2042 dec_insn.insn = (*instr_ptr << 16) |
2044 /* 32-bit instruction. */
2045 dec_insn.pc_inc = 4;
2048 /* Get second instruction. */
2049 if (mm_insn_16bit(*instr_ptr)) {
2050 /* Duplicate the half-word. */
2051 dec_insn.next_insn = (*instr_ptr << 16) |
2053 /* 16-bit instruction. */
2054 dec_insn.next_pc_inc = 2;
2056 dec_insn.next_insn = (*instr_ptr << 16) |
2058 /* 32-bit instruction. */
2059 dec_insn.next_pc_inc = 4;
2061 dec_insn.micro_mips_mode = 1;
2063 if ((get_user(dec_insn.insn,
2064 (mips_instruction __user *) xcp->cp0_epc)) ||
2065 (get_user(dec_insn.next_insn,
2066 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2067 MIPS_FPU_EMU_INC_STATS(errors);
2070 dec_insn.pc_inc = 4;
2071 dec_insn.next_pc_inc = 4;
2072 dec_insn.micro_mips_mode = 0;
2075 if ((dec_insn.insn == 0) ||
2076 ((dec_insn.pc_inc == 2) &&
2077 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2078 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2081 * The 'ieee754_csr' is an alias of
2082 * ctx->fcr31. No need to copy ctx->fcr31 to
2083 * ieee754_csr. But ieee754_csr.rm is ieee
2084 * library modes. (not mips rounding mode)
2086 /* convert to ieee library modes */
2087 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
2088 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2089 /* revert to mips rounding mode */
2090 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
2099 } while (xcp->cp0_epc > prevepc);
2101 /* SIGILL indicates a non-fpu instruction */
2102 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2103 /* but if epc has advanced, then ignore it */
2109 #ifdef CONFIG_DEBUG_FS
2111 static int fpuemu_stat_get(void *data, u64 *val)
2114 unsigned long sum = 0;
2115 for_each_online_cpu(cpu) {
2116 struct mips_fpu_emulator_stats *ps;
2118 ps = &per_cpu(fpuemustats, cpu);
2119 pv = (void *)ps + (unsigned long)data;
2120 sum += local_read(pv);
2125 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2127 extern struct dentry *mips_debugfs_dir;
2128 static int __init debugfs_fpuemu(void)
2130 struct dentry *d, *dir;
2132 if (!mips_debugfs_dir)
2134 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
2138 #define FPU_STAT_CREATE(M) \
2140 d = debugfs_create_file(#M , S_IRUGO, dir, \
2141 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2142 &fops_fpuemu_stat); \
2147 FPU_STAT_CREATE(emulated);
2148 FPU_STAT_CREATE(loads);
2149 FPU_STAT_CREATE(stores);
2150 FPU_STAT_CREATE(cp1ops);
2151 FPU_STAT_CREATE(cp1xops);
2152 FPU_STAT_CREATE(errors);
2156 __initcall(debugfs_fpuemu);