2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
41 #include <asm/bootinfo.h>
42 #include <asm/processor.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/mipsregs.h>
46 #include <asm/fpu_emulator.h>
47 #include <asm/uaccess.h>
48 #include <asm/branch.h>
52 /* Strap kernel emulator for full MIPS IV emulation */
59 /* Function which emulates a floating point instruction. */
61 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
64 #if __mips >= 4 && __mips != 32
65 static int fpux_emu(struct pt_regs *,
66 struct mips_fpu_struct *, mips_instruction);
69 /* Further private data for which no space exists in mips_fpu_struct */
71 #ifdef CONFIG_DEBUG_FS
72 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
75 /* Control registers */
77 #define FPCREG_RID 0 /* $0 = revision id */
78 #define FPCREG_CSR 31 /* $31 = csr */
80 /* Determine rounding mode from the RM bits of the FCSR */
81 #define modeindex(v) ((v) & FPU_CSR_RM)
83 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
84 static const unsigned char ieee_rm[4] = {
85 [FPU_CSR_RN] = IEEE754_RN,
86 [FPU_CSR_RZ] = IEEE754_RZ,
87 [FPU_CSR_RU] = IEEE754_RU,
88 [FPU_CSR_RD] = IEEE754_RD,
90 /* Convert IEEE library modes to Mips rounding mode (0..3). */
91 static const unsigned char mips_rm[4] = {
92 [IEEE754_RN] = FPU_CSR_RN,
93 [IEEE754_RZ] = FPU_CSR_RZ,
94 [IEEE754_RD] = FPU_CSR_RD,
95 [IEEE754_RU] = FPU_CSR_RU,
99 /* convert condition code register number to csr bit */
100 static const unsigned int fpucondbit[8] = {
114 * Redundant with logic already in kernel/branch.c,
115 * embedded in compute_return_epc. At some point,
116 * a single subroutine should be used across both
119 static int isBranchInstr(mips_instruction * i)
121 switch (MIPSInst_OPCODE(*i)) {
123 switch (MIPSInst_FUNC(*i)) {
131 switch (MIPSInst_RT(*i)) {
161 if (MIPSInst_RS(*i) == bc_op)
170 * In the Linux kernel, we support selection of FPR format on the
171 * basis of the Status.FR bit. If an FPU is not present, the FR bit
172 * is hardwired to zero, which would imply a 32-bit FPU even for
173 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
174 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
175 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
176 * even FPRs are used (Status.FR = 0).
178 static inline int cop1_64bit(struct pt_regs *xcp)
181 return xcp->cp0_status & ST0_FR;
183 return !test_thread_flag(TIF_32BIT_REGS);
189 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
190 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
192 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
193 cop1_64bit(xcp) || !(x & 1) ? \
194 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
195 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
197 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
198 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
200 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
201 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
202 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
203 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
206 * Emulate the single floating point instruction pointed at by EPC.
207 * Two instructions if the instruction is in a branch delay slot.
210 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
213 unsigned long emulpc, contpc;
216 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
217 MIPS_FPU_EMU_INC_STATS(errors);
221 /* XXX NEC Vr54xx bug workaround */
222 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
223 xcp->cp0_cause &= ~CAUSEF_BD;
225 if (xcp->cp0_cause & CAUSEF_BD) {
227 * The instruction to be emulated is in a branch delay slot
228 * which means that we have to emulate the branch instruction
229 * BEFORE we do the cop1 instruction.
231 * This branch could be a COP1 branch, but in that case we
232 * would have had a trap for that instruction, and would not
233 * come through this route.
235 * Linux MIPS branch emulator operates on context, updating the
238 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
240 if (__compute_return_epc(xcp)) {
242 printk("failed to emulate branch at %p\n",
243 (void *) (xcp->cp0_epc));
247 if (get_user(ir, (mips_instruction __user *) emulpc)) {
248 MIPS_FPU_EMU_INC_STATS(errors);
251 /* __compute_return_epc() will have updated cp0_epc */
252 contpc = xcp->cp0_epc;
253 /* In order not to confuse ptrace() et al, tweak context */
254 xcp->cp0_epc = emulpc - 4;
256 emulpc = xcp->cp0_epc;
257 contpc = xcp->cp0_epc + 4;
261 MIPS_FPU_EMU_INC_STATS(emulated);
262 switch (MIPSInst_OPCODE(ir)) {
264 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
268 MIPS_FPU_EMU_INC_STATS(loads);
269 if (get_user(val, va)) {
270 MIPS_FPU_EMU_INC_STATS(errors);
273 DITOREG(val, MIPSInst_RT(ir));
278 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
282 MIPS_FPU_EMU_INC_STATS(stores);
283 DIFROMREG(val, MIPSInst_RT(ir));
284 if (put_user(val, va)) {
285 MIPS_FPU_EMU_INC_STATS(errors);
292 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
296 MIPS_FPU_EMU_INC_STATS(loads);
297 if (get_user(val, va)) {
298 MIPS_FPU_EMU_INC_STATS(errors);
301 SITOREG(val, MIPSInst_RT(ir));
306 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
310 MIPS_FPU_EMU_INC_STATS(stores);
311 SIFROMREG(val, MIPSInst_RT(ir));
312 if (put_user(val, va)) {
313 MIPS_FPU_EMU_INC_STATS(errors);
320 switch (MIPSInst_RS(ir)) {
322 #if defined(__mips64)
324 /* copregister fs -> gpr[rt] */
325 if (MIPSInst_RT(ir) != 0) {
326 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
332 /* copregister fs <- rt */
333 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
338 /* copregister rd -> gpr[rt] */
339 if (MIPSInst_RT(ir) != 0) {
340 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
346 /* copregister rd <- rt */
347 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
351 /* cop control register rd -> gpr[rt] */
354 if (MIPSInst_RD(ir) == FPCREG_CSR) {
356 value = (value & ~FPU_CSR_RM) |
357 mips_rm[modeindex(value)];
359 printk("%p gpr[%d]<-csr=%08x\n",
360 (void *) (xcp->cp0_epc),
361 MIPSInst_RT(ir), value);
364 else if (MIPSInst_RD(ir) == FPCREG_RID)
369 xcp->regs[MIPSInst_RT(ir)] = value;
374 /* copregister rd <- rt */
377 if (MIPSInst_RT(ir) == 0)
380 value = xcp->regs[MIPSInst_RT(ir)];
382 /* we only have one writable control reg
384 if (MIPSInst_RD(ir) == FPCREG_CSR) {
386 printk("%p gpr[%d]->csr=%08x\n",
387 (void *) (xcp->cp0_epc),
388 MIPSInst_RT(ir), value);
392 * Don't write reserved bits,
393 * and convert to ieee library modes
395 ctx->fcr31 = (value &
396 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
397 ieee_rm[modeindex(value)];
399 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
408 if (xcp->cp0_cause & CAUSEF_BD)
412 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
414 cond = ctx->fcr31 & FPU_CSR_COND;
416 switch (MIPSInst_RT(ir) & 3) {
427 /* thats an illegal instruction */
431 xcp->cp0_cause |= CAUSEF_BD;
433 /* branch taken: emulate dslot
437 contpc = (xcp->cp0_epc +
438 (MIPSInst_SIMM(ir) << 2));
441 (mips_instruction __user *) xcp->cp0_epc)) {
442 MIPS_FPU_EMU_INC_STATS(errors);
446 switch (MIPSInst_OPCODE(ir)) {
449 #if (__mips >= 2 || defined(__mips64))
454 #if __mips >= 4 && __mips != 32
457 /* its one of ours */
461 if (MIPSInst_FUNC(ir) == movc_op)
468 * Single step the non-cp1
469 * instruction in the dslot
471 return mips_dsemul(xcp, ir, contpc);
474 /* branch not taken */
477 * branch likely nullifies
483 * else continue & execute
484 * dslot as normal insn
492 if (!(MIPSInst_RS(ir) & 0x10))
497 /* a real fpu computation instruction */
498 if ((sig = fpu_emu(xcp, ctx, ir)))
504 #if __mips >= 4 && __mips != 32
508 if ((sig = fpux_emu(xcp, ctx, ir)))
516 if (MIPSInst_FUNC(ir) != movc_op)
518 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
519 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
520 xcp->regs[MIPSInst_RD(ir)] =
521 xcp->regs[MIPSInst_RS(ir)];
530 xcp->cp0_epc = contpc;
531 xcp->cp0_cause &= ~CAUSEF_BD;
537 * Conversion table from MIPS compare ops 48-63
538 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
540 static const unsigned char cmptab[8] = {
541 0, /* cmp_0 (sig) cmp_sf */
542 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
543 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
544 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
545 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
546 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
547 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
548 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
552 #if __mips >= 4 && __mips != 32
555 * Additional MIPS4 instructions
558 #define DEF3OP(name, p, f1, f2, f3) \
559 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
562 struct _ieee754_csr ieee754_csr_save; \
564 ieee754_csr_save = ieee754_csr; \
566 ieee754_csr_save.cx |= ieee754_csr.cx; \
567 ieee754_csr_save.sx |= ieee754_csr.sx; \
569 ieee754_csr.cx |= ieee754_csr_save.cx; \
570 ieee754_csr.sx |= ieee754_csr_save.sx; \
574 static ieee754dp fpemu_dp_recip(ieee754dp d)
576 return ieee754dp_div(ieee754dp_one(0), d);
579 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
581 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
584 static ieee754sp fpemu_sp_recip(ieee754sp s)
586 return ieee754sp_div(ieee754sp_one(0), s);
589 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
591 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
594 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
595 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
596 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
597 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
598 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
599 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
600 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
601 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
603 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
606 unsigned rcsr = 0; /* resulting csr */
608 MIPS_FPU_EMU_INC_STATS(cp1xops);
610 switch (MIPSInst_FMA_FFMT(ir)) {
613 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
614 ieee754sp fd, fr, fs, ft;
618 switch (MIPSInst_FUNC(ir)) {
620 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
621 xcp->regs[MIPSInst_FT(ir)]);
623 MIPS_FPU_EMU_INC_STATS(loads);
624 if (get_user(val, va)) {
625 MIPS_FPU_EMU_INC_STATS(errors);
628 SITOREG(val, MIPSInst_FD(ir));
632 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
633 xcp->regs[MIPSInst_FT(ir)]);
635 MIPS_FPU_EMU_INC_STATS(stores);
637 SIFROMREG(val, MIPSInst_FS(ir));
638 if (put_user(val, va)) {
639 MIPS_FPU_EMU_INC_STATS(errors);
645 handler = fpemu_sp_madd;
648 handler = fpemu_sp_msub;
651 handler = fpemu_sp_nmadd;
654 handler = fpemu_sp_nmsub;
658 SPFROMREG(fr, MIPSInst_FR(ir));
659 SPFROMREG(fs, MIPSInst_FS(ir));
660 SPFROMREG(ft, MIPSInst_FT(ir));
661 fd = (*handler) (fr, fs, ft);
662 SPTOREG(fd, MIPSInst_FD(ir));
665 if (ieee754_cxtest(IEEE754_INEXACT))
666 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
667 if (ieee754_cxtest(IEEE754_UNDERFLOW))
668 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
669 if (ieee754_cxtest(IEEE754_OVERFLOW))
670 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
671 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
672 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
674 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
675 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
676 /*printk ("SIGFPE: fpu csr = %08x\n",
690 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
691 ieee754dp fd, fr, fs, ft;
695 switch (MIPSInst_FUNC(ir)) {
697 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
698 xcp->regs[MIPSInst_FT(ir)]);
700 MIPS_FPU_EMU_INC_STATS(loads);
701 if (get_user(val, va)) {
702 MIPS_FPU_EMU_INC_STATS(errors);
705 DITOREG(val, MIPSInst_FD(ir));
709 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
710 xcp->regs[MIPSInst_FT(ir)]);
712 MIPS_FPU_EMU_INC_STATS(stores);
713 DIFROMREG(val, MIPSInst_FS(ir));
714 if (put_user(val, va)) {
715 MIPS_FPU_EMU_INC_STATS(errors);
721 handler = fpemu_dp_madd;
724 handler = fpemu_dp_msub;
727 handler = fpemu_dp_nmadd;
730 handler = fpemu_dp_nmsub;
734 DPFROMREG(fr, MIPSInst_FR(ir));
735 DPFROMREG(fs, MIPSInst_FS(ir));
736 DPFROMREG(ft, MIPSInst_FT(ir));
737 fd = (*handler) (fr, fs, ft);
738 DPTOREG(fd, MIPSInst_FD(ir));
748 if (MIPSInst_FUNC(ir) != pfetch_op) {
751 /* ignore prefx operation */
765 * Emulate a single COP1 arithmetic instruction.
767 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
770 int rfmt; /* resulting format */
771 unsigned rcsr = 0; /* resulting csr */
780 } rv; /* resulting value */
782 MIPS_FPU_EMU_INC_STATS(cp1ops);
783 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
786 ieee754sp(*b) (ieee754sp, ieee754sp);
787 ieee754sp(*u) (ieee754sp);
790 switch (MIPSInst_FUNC(ir)) {
793 handler.b = ieee754sp_add;
796 handler.b = ieee754sp_sub;
799 handler.b = ieee754sp_mul;
802 handler.b = ieee754sp_div;
806 #if __mips >= 2 || defined(__mips64)
808 handler.u = ieee754sp_sqrt;
811 #if __mips >= 4 && __mips != 32
813 handler.u = fpemu_sp_rsqrt;
816 handler.u = fpemu_sp_recip;
821 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
822 if (((ctx->fcr31 & cond) != 0) !=
823 ((MIPSInst_FT(ir) & 1) != 0))
825 SPFROMREG(rv.s, MIPSInst_FS(ir));
828 if (xcp->regs[MIPSInst_FT(ir)] != 0)
830 SPFROMREG(rv.s, MIPSInst_FS(ir));
833 if (xcp->regs[MIPSInst_FT(ir)] == 0)
835 SPFROMREG(rv.s, MIPSInst_FS(ir));
839 handler.u = ieee754sp_abs;
842 handler.u = ieee754sp_neg;
846 SPFROMREG(rv.s, MIPSInst_FS(ir));
849 /* binary op on handler */
854 SPFROMREG(fs, MIPSInst_FS(ir));
855 SPFROMREG(ft, MIPSInst_FT(ir));
857 rv.s = (*handler.b) (fs, ft);
864 SPFROMREG(fs, MIPSInst_FS(ir));
865 rv.s = (*handler.u) (fs);
869 if (ieee754_cxtest(IEEE754_INEXACT))
870 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
871 if (ieee754_cxtest(IEEE754_UNDERFLOW))
872 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
873 if (ieee754_cxtest(IEEE754_OVERFLOW))
874 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
875 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
876 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
877 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
878 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
883 return SIGILL; /* not defined */
887 SPFROMREG(fs, MIPSInst_FS(ir));
888 rv.d = ieee754dp_fsp(fs);
895 SPFROMREG(fs, MIPSInst_FS(ir));
896 rv.w = ieee754sp_tint(fs);
901 #if __mips >= 2 || defined(__mips64)
906 unsigned int oldrm = ieee754_csr.rm;
909 SPFROMREG(fs, MIPSInst_FS(ir));
910 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
911 rv.w = ieee754sp_tint(fs);
912 ieee754_csr.rm = oldrm;
916 #endif /* __mips >= 2 */
918 #if defined(__mips64)
922 SPFROMREG(fs, MIPSInst_FS(ir));
923 rv.l = ieee754sp_tlong(fs);
932 unsigned int oldrm = ieee754_csr.rm;
935 SPFROMREG(fs, MIPSInst_FS(ir));
936 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
937 rv.l = ieee754sp_tlong(fs);
938 ieee754_csr.rm = oldrm;
942 #endif /* defined(__mips64) */
945 if (MIPSInst_FUNC(ir) >= fcmp_op) {
946 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
949 SPFROMREG(fs, MIPSInst_FS(ir));
950 SPFROMREG(ft, MIPSInst_FT(ir));
951 rv.w = ieee754sp_cmp(fs, ft,
952 cmptab[cmpop & 0x7], cmpop & 0x8);
954 if ((cmpop & 0x8) && ieee754_cxtest
955 (IEEE754_INVALID_OPERATION))
956 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
971 ieee754dp(*b) (ieee754dp, ieee754dp);
972 ieee754dp(*u) (ieee754dp);
975 switch (MIPSInst_FUNC(ir)) {
978 handler.b = ieee754dp_add;
981 handler.b = ieee754dp_sub;
984 handler.b = ieee754dp_mul;
987 handler.b = ieee754dp_div;
991 #if __mips >= 2 || defined(__mips64)
993 handler.u = ieee754dp_sqrt;
996 #if __mips >= 4 && __mips != 32
998 handler.u = fpemu_dp_rsqrt;
1001 handler.u = fpemu_dp_recip;
1006 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1007 if (((ctx->fcr31 & cond) != 0) !=
1008 ((MIPSInst_FT(ir) & 1) != 0))
1010 DPFROMREG(rv.d, MIPSInst_FS(ir));
1013 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1015 DPFROMREG(rv.d, MIPSInst_FS(ir));
1018 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1020 DPFROMREG(rv.d, MIPSInst_FS(ir));
1024 handler.u = ieee754dp_abs;
1028 handler.u = ieee754dp_neg;
1033 DPFROMREG(rv.d, MIPSInst_FS(ir));
1036 /* binary op on handler */
1040 DPFROMREG(fs, MIPSInst_FS(ir));
1041 DPFROMREG(ft, MIPSInst_FT(ir));
1043 rv.d = (*handler.b) (fs, ft);
1049 DPFROMREG(fs, MIPSInst_FS(ir));
1050 rv.d = (*handler.u) (fs);
1054 /* unary conv ops */
1058 DPFROMREG(fs, MIPSInst_FS(ir));
1059 rv.s = ieee754sp_fdp(fs);
1064 return SIGILL; /* not defined */
1069 DPFROMREG(fs, MIPSInst_FS(ir));
1070 rv.w = ieee754dp_tint(fs); /* wrong */
1075 #if __mips >= 2 || defined(__mips64)
1080 unsigned int oldrm = ieee754_csr.rm;
1083 DPFROMREG(fs, MIPSInst_FS(ir));
1084 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1085 rv.w = ieee754dp_tint(fs);
1086 ieee754_csr.rm = oldrm;
1092 #if defined(__mips64)
1096 DPFROMREG(fs, MIPSInst_FS(ir));
1097 rv.l = ieee754dp_tlong(fs);
1106 unsigned int oldrm = ieee754_csr.rm;
1109 DPFROMREG(fs, MIPSInst_FS(ir));
1110 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1111 rv.l = ieee754dp_tlong(fs);
1112 ieee754_csr.rm = oldrm;
1116 #endif /* __mips >= 3 */
1119 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1120 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1123 DPFROMREG(fs, MIPSInst_FS(ir));
1124 DPFROMREG(ft, MIPSInst_FT(ir));
1125 rv.w = ieee754dp_cmp(fs, ft,
1126 cmptab[cmpop & 0x7], cmpop & 0x8);
1131 (IEEE754_INVALID_OPERATION))
1132 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1148 switch (MIPSInst_FUNC(ir)) {
1150 /* convert word to single precision real */
1151 SPFROMREG(fs, MIPSInst_FS(ir));
1152 rv.s = ieee754sp_fint(fs.bits);
1156 /* convert word to double precision real */
1157 SPFROMREG(fs, MIPSInst_FS(ir));
1158 rv.d = ieee754dp_fint(fs.bits);
1167 #if defined(__mips64)
1169 switch (MIPSInst_FUNC(ir)) {
1171 /* convert long to single precision real */
1172 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1176 /* convert long to double precision real */
1177 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1192 * Update the fpu CSR register for this operation.
1193 * If an exception is required, generate a tidy SIGFPE exception,
1194 * without updating the result register.
1195 * Note: cause exception bits do not accumulate, they are rewritten
1196 * for each op; only the flag/sticky bits accumulate.
1198 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1199 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1200 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1205 * Now we can safely write the result back to the register file.
1210 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1212 cond = FPU_CSR_COND;
1217 ctx->fcr31 &= ~cond;
1221 DPTOREG(rv.d, MIPSInst_FD(ir));
1224 SPTOREG(rv.s, MIPSInst_FD(ir));
1227 SITOREG(rv.w, MIPSInst_FD(ir));
1229 #if defined(__mips64)
1231 DITOREG(rv.l, MIPSInst_FD(ir));
1241 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1244 unsigned long oldepc, prevepc;
1245 mips_instruction insn;
1248 oldepc = xcp->cp0_epc;
1250 prevepc = xcp->cp0_epc;
1252 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1253 MIPS_FPU_EMU_INC_STATS(errors);
1257 xcp->cp0_epc += 4; /* skip nops */
1260 * The 'ieee754_csr' is an alias of
1261 * ctx->fcr31. No need to copy ctx->fcr31 to
1262 * ieee754_csr. But ieee754_csr.rm is ieee
1263 * library modes. (not mips rounding mode)
1265 /* convert to ieee library modes */
1266 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1267 sig = cop1Emulate(xcp, ctx);
1268 /* revert to mips rounding mode */
1269 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1278 } while (xcp->cp0_epc > prevepc);
1280 /* SIGILL indicates a non-fpu instruction */
1281 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1282 /* but if epc has advanced, then ignore it */
1288 #ifdef CONFIG_DEBUG_FS
1290 static int fpuemu_stat_get(void *data, u64 *val)
1293 unsigned long sum = 0;
1294 for_each_online_cpu(cpu) {
1295 struct mips_fpu_emulator_stats *ps;
1297 ps = &per_cpu(fpuemustats, cpu);
1298 pv = (void *)ps + (unsigned long)data;
1299 sum += local_read(pv);
1304 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1306 extern struct dentry *mips_debugfs_dir;
1307 static int __init debugfs_fpuemu(void)
1309 struct dentry *d, *dir;
1311 if (!mips_debugfs_dir)
1313 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1317 #define FPU_STAT_CREATE(M) \
1319 d = debugfs_create_file(#M , S_IRUGO, dir, \
1320 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1321 &fops_fpuemu_stat); \
1326 FPU_STAT_CREATE(emulated);
1327 FPU_STAT_CREATE(loads);
1328 FPU_STAT_CREATE(stores);
1329 FPU_STAT_CREATE(cp1ops);
1330 FPU_STAT_CREATE(cp1xops);
1331 FPU_STAT_CREATE(errors);
1335 __initcall(debugfs_fpuemu);