arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/percpu-defs.h>
  39 #include <linux/perf_event.h>
  40
  41 #include <asm/branch.h>
  42 #include <asm/inst.h>
  43 #include <asm/ptrace.h>
  44 #include <asm/signal.h>
  45 #include <linux/uaccess.h>
  46
  47 #include <asm/cpu-info.h>
  48 #include <asm/processor.h>
  49 #include <asm/fpu_emulator.h>
  50 #include <asm/fpu.h>
  51 #include <asm/mips-r2-to-r6-emul.h>
  52
  53 #include "ieee754.h"
  54
  55 /* Function which emulates a floating point instruction. */
  56
  57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  58         mips_instruction);
  59
  60 static int fpux_emu(struct pt_regs *,
  61         struct mips_fpu_struct *, mips_instruction, void *__user *);
  62
  63 /* Control registers */
  64
  65 #define FPCREG_RID      0       /* $0  = revision id */
  66 #define FPCREG_FCCR     25      /* $25 = fccr */
  67 #define FPCREG_FEXR     26      /* $26 = fexr */
  68 #define FPCREG_FENR     28      /* $28 = fenr */
  69 #define FPCREG_CSR      31      /* $31 = csr */
  70
  71 /* convert condition code register number to csr bit */
  72 const unsigned int fpucondbit[8] = {
  73         FPU_CSR_COND,
  74         FPU_CSR_COND1,
  75         FPU_CSR_COND2,
  76         FPU_CSR_COND3,
  77         FPU_CSR_COND4,
  78         FPU_CSR_COND5,
  79         FPU_CSR_COND6,
  80         FPU_CSR_COND7
  81 };
  82
  83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  88
  89 /*
  90  * This functions translates a 32-bit microMIPS instruction
  91  * into a 32-bit MIPS32 instruction. Returns 0 on success
  92  * and SIGILL otherwise.
  93  */
  94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  95 {
  96         union mips_instruction insn = *insn_ptr;
  97         union mips_instruction mips32_insn = insn;
  98         int func, fmt, op;
  99
 100         switch (insn.mm_i_format.opcode) {
 101         case mm_ldc132_op:
 102                 mips32_insn.mm_i_format.opcode = ldc1_op;
 103                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 104                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 105                 break;
 106         case mm_lwc132_op:
 107                 mips32_insn.mm_i_format.opcode = lwc1_op;
 108                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 109                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 110                 break;
 111         case mm_sdc132_op:
 112                 mips32_insn.mm_i_format.opcode = sdc1_op;
 113                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 114                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 115                 break;
 116         case mm_swc132_op:
 117                 mips32_insn.mm_i_format.opcode = swc1_op;
 118                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 119                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 120                 break;
 121         case mm_pool32i_op:
 122                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 123                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 124                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 125                         mips32_insn.fb_format.opcode = cop1_op;
 126                         mips32_insn.fb_format.bc = bc_op;
 127                         mips32_insn.fb_format.flag =
 128                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 129                 } else
 130                         return SIGILL;
 131                 break;
 132         case mm_pool32f_op:
 133                 switch (insn.mm_fp0_format.func) {
 134                 case mm_32f_01_op:
 135                 case mm_32f_11_op:
 136                 case mm_32f_02_op:
 137                 case mm_32f_12_op:
 138                 case mm_32f_41_op:
 139                 case mm_32f_51_op:
 140                 case mm_32f_42_op:
 141                 case mm_32f_52_op:
 142                         op = insn.mm_fp0_format.func;
 143                         if (op == mm_32f_01_op)
 144                                 func = madd_s_op;
 145                         else if (op == mm_32f_11_op)
 146                                 func = madd_d_op;
 147                         else if (op == mm_32f_02_op)
 148                                 func = nmadd_s_op;
 149                         else if (op == mm_32f_12_op)
 150                                 func = nmadd_d_op;
 151                         else if (op == mm_32f_41_op)
 152                                 func = msub_s_op;
 153                         else if (op == mm_32f_51_op)
 154                                 func = msub_d_op;
 155                         else if (op == mm_32f_42_op)
 156                                 func = nmsub_s_op;
 157                         else
 158                                 func = nmsub_d_op;
 159                         mips32_insn.fp6_format.opcode = cop1x_op;
 160                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 161                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 162                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 163                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 164                         mips32_insn.fp6_format.func = func;
 165                         break;
 166                 case mm_32f_10_op:
 167                         func = -1;      /* Invalid */
 168                         op = insn.mm_fp5_format.op & 0x7;
 169                         if (op == mm_ldxc1_op)
 170                                 func = ldxc1_op;
 171                         else if (op == mm_sdxc1_op)
 172                                 func = sdxc1_op;
 173                         else if (op == mm_lwxc1_op)
 174                                 func = lwxc1_op;
 175                         else if (op == mm_swxc1_op)
 176                                 func = swxc1_op;
 177
 178                         if (func != -1) {
 179                                 mips32_insn.r_format.opcode = cop1x_op;
 180                                 mips32_insn.r_format.rs =
 181                                         insn.mm_fp5_format.base;
 182                                 mips32_insn.r_format.rt =
 183                                         insn.mm_fp5_format.index;
 184                                 mips32_insn.r_format.rd = 0;
 185                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 186                                 mips32_insn.r_format.func = func;
 187                         } else
 188                                 return SIGILL;
 189                         break;
 190                 case mm_32f_40_op:
 191                         op = -1;        /* Invalid */
 192                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 193                                 op = 1;
 194                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 195                                 op = 0;
 196                         if (op != -1) {
 197                                 mips32_insn.fp0_format.opcode = cop1_op;
 198                                 mips32_insn.fp0_format.fmt =
 199                                         sdps_format[insn.mm_fp2_format.fmt];
 200                                 mips32_insn.fp0_format.ft =
 201                                         (insn.mm_fp2_format.cc<<2) + op;
 202                                 mips32_insn.fp0_format.fs =
 203                                         insn.mm_fp2_format.fs;
 204                                 mips32_insn.fp0_format.fd =
 205                                         insn.mm_fp2_format.fd;
 206                                 mips32_insn.fp0_format.func = fmovc_op;
 207                         } else
 208                                 return SIGILL;
 209                         break;
 210                 case mm_32f_60_op:
 211                         func = -1;      /* Invalid */
 212                         if (insn.mm_fp0_format.op == mm_fadd_op)
 213                                 func = fadd_op;
 214                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 215                                 func = fsub_op;
 216                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 217                                 func = fmul_op;
 218                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 219                                 func = fdiv_op;
 220                         if (func != -1) {
 221                                 mips32_insn.fp0_format.opcode = cop1_op;
 222                                 mips32_insn.fp0_format.fmt =
 223                                         sdps_format[insn.mm_fp0_format.fmt];
 224                                 mips32_insn.fp0_format.ft =
 225                                         insn.mm_fp0_format.ft;
 226                                 mips32_insn.fp0_format.fs =
 227                                         insn.mm_fp0_format.fs;
 228                                 mips32_insn.fp0_format.fd =
 229                                         insn.mm_fp0_format.fd;
 230                                 mips32_insn.fp0_format.func = func;
 231                         } else
 232                                 return SIGILL;
 233                         break;
 234                 case mm_32f_70_op:
 235                         func = -1;      /* Invalid */
 236                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 237                                 func = fmovn_op;
 238                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 239                                 func = fmovz_op;
 240                         if (func != -1) {
 241                                 mips32_insn.fp0_format.opcode = cop1_op;
 242                                 mips32_insn.fp0_format.fmt =
 243                                         sdps_format[insn.mm_fp0_format.fmt];
 244                                 mips32_insn.fp0_format.ft =
 245                                         insn.mm_fp0_format.ft;
 246                                 mips32_insn.fp0_format.fs =
 247                                         insn.mm_fp0_format.fs;
 248                                 mips32_insn.fp0_format.fd =
 249                                         insn.mm_fp0_format.fd;
 250                                 mips32_insn.fp0_format.func = func;
 251                         } else
 252                                 return SIGILL;
 253                         break;
 254                 case mm_32f_73_op:    /* POOL32FXF */
 255                         switch (insn.mm_fp1_format.op) {
 256                         case mm_movf0_op:
 257                         case mm_movf1_op:
 258                         case mm_movt0_op:
 259                         case mm_movt1_op:
 260                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 261                                     mm_movf0_op)
 262                                         op = 0;
 263                                 else
 264                                         op = 1;
 265                                 mips32_insn.r_format.opcode = spec_op;
 266                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 267                                 mips32_insn.r_format.rt =
 268                                         (insn.mm_fp4_format.cc << 2) + op;
 269                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 270                                 mips32_insn.r_format.re = 0;
 271                                 mips32_insn.r_format.func = movc_op;
 272                                 break;
 273                         case mm_fcvtd0_op:
 274                         case mm_fcvtd1_op:
 275                         case mm_fcvts0_op:
 276                         case mm_fcvts1_op:
 277                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 278                                     mm_fcvtd0_op) {
 279                                         func = fcvtd_op;
 280                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 281                                 } else {
 282                                         func = fcvts_op;
 283                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 284                                 }
 285                                 mips32_insn.fp0_format.opcode = cop1_op;
 286                                 mips32_insn.fp0_format.fmt = fmt;
 287                                 mips32_insn.fp0_format.ft = 0;
 288                                 mips32_insn.fp0_format.fs =
 289                                         insn.mm_fp3_format.fs;
 290                                 mips32_insn.fp0_format.fd =
 291                                         insn.mm_fp3_format.rt;
 292                                 mips32_insn.fp0_format.func = func;
 293                                 break;
 294                         case mm_fmov0_op:
 295                         case mm_fmov1_op:
 296                         case mm_fabs0_op:
 297                         case mm_fabs1_op:
 298                         case mm_fneg0_op:
 299                         case mm_fneg1_op:
 300                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 301                                     mm_fmov0_op)
 302                                         func = fmov_op;
 303                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 304                                          mm_fabs0_op)
 305                                         func = fabs_op;
 306                                 else
 307                                         func = fneg_op;
 308                                 mips32_insn.fp0_format.opcode = cop1_op;
 309                                 mips32_insn.fp0_format.fmt =
 310                                         sdps_format[insn.mm_fp3_format.fmt];
 311                                 mips32_insn.fp0_format.ft = 0;
 312                                 mips32_insn.fp0_format.fs =
 313                                         insn.mm_fp3_format.fs;
 314                                 mips32_insn.fp0_format.fd =
 315                                         insn.mm_fp3_format.rt;
 316                                 mips32_insn.fp0_format.func = func;
 317                                 break;
 318                         case mm_ffloorl_op:
 319                         case mm_ffloorw_op:
 320                         case mm_fceill_op:
 321                         case mm_fceilw_op:
 322                         case mm_ftruncl_op:
 323                         case mm_ftruncw_op:
 324                         case mm_froundl_op:
 325                         case mm_froundw_op:
 326                         case mm_fcvtl_op:
 327                         case mm_fcvtw_op:
 328                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 329                                         func = ffloorl_op;
 330                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 331                                         func = ffloor_op;
 332                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 333                                         func = fceill_op;
 334                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 335                                         func = fceil_op;
 336                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 337                                         func = ftruncl_op;
 338                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 339                                         func = ftrunc_op;
 340                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 341                                         func = froundl_op;
 342                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 343                                         func = fround_op;
 344                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 345                                         func = fcvtl_op;
 346                                 else
 347                                         func = fcvtw_op;
 348                                 mips32_insn.fp0_format.opcode = cop1_op;
 349                                 mips32_insn.fp0_format.fmt =
 350                                         sd_format[insn.mm_fp1_format.fmt];
 351                                 mips32_insn.fp0_format.ft = 0;
 352                                 mips32_insn.fp0_format.fs =
 353                                         insn.mm_fp1_format.fs;
 354                                 mips32_insn.fp0_format.fd =
 355                                         insn.mm_fp1_format.rt;
 356                                 mips32_insn.fp0_format.func = func;
 357                                 break;
 358                         case mm_frsqrt_op:
 359                         case mm_fsqrt_op:
 360                         case mm_frecip_op:
 361                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 362                                         func = frsqrt_op;
 363                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 364                                         func = fsqrt_op;
 365                                 else
 366                                         func = frecip_op;
 367                                 mips32_insn.fp0_format.opcode = cop1_op;
 368                                 mips32_insn.fp0_format.fmt =
 369                                         sdps_format[insn.mm_fp1_format.fmt];
 370                                 mips32_insn.fp0_format.ft = 0;
 371                                 mips32_insn.fp0_format.fs =
 372                                         insn.mm_fp1_format.fs;
 373                                 mips32_insn.fp0_format.fd =
 374                                         insn.mm_fp1_format.rt;
 375                                 mips32_insn.fp0_format.func = func;
 376                                 break;
 377                         case mm_mfc1_op:
 378                         case mm_mtc1_op:
 379                         case mm_cfc1_op:
 380                         case mm_ctc1_op:
 381                         case mm_mfhc1_op:
 382                         case mm_mthc1_op:
 383                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 384                                         op = mfc_op;
 385                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 386                                         op = mtc_op;
 387                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 388                                         op = cfc_op;
 389                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 390                                         op = ctc_op;
 391                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 392                                         op = mfhc_op;
 393                                 else
 394                                         op = mthc_op;
 395                                 mips32_insn.fp1_format.opcode = cop1_op;
 396                                 mips32_insn.fp1_format.op = op;
 397                                 mips32_insn.fp1_format.rt =
 398                                         insn.mm_fp1_format.rt;
 399                                 mips32_insn.fp1_format.fs =
 400                                         insn.mm_fp1_format.fs;
 401                                 mips32_insn.fp1_format.fd = 0;
 402                                 mips32_insn.fp1_format.func = 0;
 403                                 break;
 404                         default:
 405                                 return SIGILL;
 406                         }
 407                         break;
 408                 case mm_32f_74_op:      /* c.cond.fmt */
 409                         mips32_insn.fp0_format.opcode = cop1_op;
 410                         mips32_insn.fp0_format.fmt =
 411                                 sdps_format[insn.mm_fp4_format.fmt];
 412                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 413                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 414                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 415                         mips32_insn.fp0_format.func =
 416                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 417                         break;
 418                 default:
 419                         return SIGILL;
 420                 }
 421                 break;
 422         default:
 423                 return SIGILL;
 424         }
 425
 426         *insn_ptr = mips32_insn;
 427         return 0;
 428 }
 429
 430 /*
 431  * Redundant with logic already in kernel/branch.c,
 432  * embedded in compute_return_epc.  At some point,
 433  * a single subroutine should be used across both
 434  * modules.
 435  */
 436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 437                   unsigned long *contpc)
 438 {
 439         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 440         unsigned int fcr31;
 441         unsigned int bit = 0;
 442         unsigned int bit0;
 443         union fpureg *fpr;
 444
 445         switch (insn.i_format.opcode) {
 446         case spec_op:
 447                 switch (insn.r_format.func) {
 448                 case jalr_op:
 449                         if (insn.r_format.rd != 0) {
 450                                 regs->regs[insn.r_format.rd] =
 451                                         regs->cp0_epc + dec_insn.pc_inc +
 452                                         dec_insn.next_pc_inc;
 453                         }
 454                         /* Fall through */
 455                 case jr_op:
 456                         /* For R6, JR already emulated in jalr_op */
 457                         if (NO_R6EMU && insn.r_format.func == jr_op)
 458                                 break;
 459                         *contpc = regs->regs[insn.r_format.rs];
 460                         return 1;
 461                 }
 462                 break;
 463         case bcond_op:
 464                 switch (insn.i_format.rt) {
 465                 case bltzal_op:
 466                 case bltzall_op:
 467                         if (NO_R6EMU && (insn.i_format.rs ||
 468                             insn.i_format.rt == bltzall_op))
 469                                 break;
 470
 471                         regs->regs[31] = regs->cp0_epc +
 472                                 dec_insn.pc_inc +
 473                                 dec_insn.next_pc_inc;
 474                         /* Fall through */
 475                 case bltzl_op:
 476                         if (NO_R6EMU)
 477                                 break;
 478                 case bltz_op:
 479                         if ((long)regs->regs[insn.i_format.rs] < 0)
 480                                 *contpc = regs->cp0_epc +
 481                                         dec_insn.pc_inc +
 482                                         (insn.i_format.simmediate << 2);
 483                         else
 484                                 *contpc = regs->cp0_epc +
 485                                         dec_insn.pc_inc +
 486                                         dec_insn.next_pc_inc;
 487                         return 1;
 488                 case bgezal_op:
 489                 case bgezall_op:
 490                         if (NO_R6EMU && (insn.i_format.rs ||
 491                             insn.i_format.rt == bgezall_op))
 492                                 break;
 493
 494                         regs->regs[31] = regs->cp0_epc +
 495                                 dec_insn.pc_inc +
 496                                 dec_insn.next_pc_inc;
 497                         /* Fall through */
 498                 case bgezl_op:
 499                         if (NO_R6EMU)
 500                                 break;
 501                 case bgez_op:
 502                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 503                                 *contpc = regs->cp0_epc +
 504                                         dec_insn.pc_inc +
 505                                         (insn.i_format.simmediate << 2);
 506                         else
 507                                 *contpc = regs->cp0_epc +
 508                                         dec_insn.pc_inc +
 509                                         dec_insn.next_pc_inc;
 510                         return 1;
 511                 }
 512                 break;
 513         case jalx_op:
 514                 set_isa16_mode(bit);
 515         case jal_op:
 516                 regs->regs[31] = regs->cp0_epc +
 517                         dec_insn.pc_inc +
 518                         dec_insn.next_pc_inc;
 519                 /* Fall through */
 520         case j_op:
 521                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 522                 *contpc >>= 28;
 523                 *contpc <<= 28;
 524                 *contpc |= (insn.j_format.target << 2);
 525                 /* Set microMIPS mode bit: XOR for jalx. */
 526                 *contpc ^= bit;
 527                 return 1;
 528         case beql_op:
 529                 if (NO_R6EMU)
 530                         break;
 531         case beq_op:
 532                 if (regs->regs[insn.i_format.rs] ==
 533                     regs->regs[insn.i_format.rt])
 534                         *contpc = regs->cp0_epc +
 535                                 dec_insn.pc_inc +
 536                                 (insn.i_format.simmediate << 2);
 537                 else
 538                         *contpc = regs->cp0_epc +
 539                                 dec_insn.pc_inc +
 540                                 dec_insn.next_pc_inc;
 541                 return 1;
 542         case bnel_op:
 543                 if (NO_R6EMU)
 544                         break;
 545         case bne_op:
 546                 if (regs->regs[insn.i_format.rs] !=
 547                     regs->regs[insn.i_format.rt])
 548                         *contpc = regs->cp0_epc +
 549                                 dec_insn.pc_inc +
 550                                 (insn.i_format.simmediate << 2);
 551                 else
 552                         *contpc = regs->cp0_epc +
 553                                 dec_insn.pc_inc +
 554                                 dec_insn.next_pc_inc;
 555                 return 1;
 556         case blezl_op:
 557                 if (!insn.i_format.rt && NO_R6EMU)
 558                         break;
 559         case blez_op:
 560
 561                 /*
 562                  * Compact branches for R6 for the
 563                  * blez and blezl opcodes.
 564                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
 565                  * BLEZ  | rs = rt != 0      == BGEZALC
 566                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
 567                  * BLEZL | rs = 0 | rt != 0  == BLEZC
 568                  * BLEZL | rs = rt != 0      == BGEZC
 569                  * BLEZL | rs != 0 | rt != 0 == BGEC
 570                  *
 571                  * For real BLEZ{,L}, rt is always 0.
 572                  */
 573                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 574                         if ((insn.i_format.opcode == blez_op) &&
 575                             ((!insn.i_format.rs && insn.i_format.rt) ||
 576                              (insn.i_format.rs == insn.i_format.rt)))
 577                                 regs->regs[31] = regs->cp0_epc +
 578                                         dec_insn.pc_inc;
 579                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 580                                 dec_insn.next_pc_inc;
 581
 582                         return 1;
 583                 }
 584                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 585                         *contpc = regs->cp0_epc +
 586                                 dec_insn.pc_inc +
 587                                 (insn.i_format.simmediate << 2);
 588                 else
 589                         *contpc = regs->cp0_epc +
 590                                 dec_insn.pc_inc +
 591                                 dec_insn.next_pc_inc;
 592                 return 1;
 593         case bgtzl_op:
 594                 if (!insn.i_format.rt && NO_R6EMU)
 595                         break;
 596         case bgtz_op:
 597                 /*
 598                  * Compact branches for R6 for the
 599                  * bgtz and bgtzl opcodes.
 600                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
 601                  * BGTZ  | rs = rt != 0      == BLTZALC
 602                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
 603                  * BGTZL | rs = 0 | rt != 0  == BGTZC
 604                  * BGTZL | rs = rt != 0      == BLTZC
 605                  * BGTZL | rs != 0 | rt != 0 == BLTC
 606                  *
 607                  * *ZALC varint for BGTZ &&& rt != 0
 608                  * For real GTZ{,L}, rt is always 0.
 609                  */
 610                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 611                         if ((insn.i_format.opcode == blez_op) &&
 612                             ((!insn.i_format.rs && insn.i_format.rt) ||
 613                              (insn.i_format.rs == insn.i_format.rt)))
 614                                 regs->regs[31] = regs->cp0_epc +
 615                                         dec_insn.pc_inc;
 616                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 617                                 dec_insn.next_pc_inc;
 618
 619                         return 1;
 620                 }
 621
 622                 if ((long)regs->regs[insn.i_format.rs] > 0)
 623                         *contpc = regs->cp0_epc +
 624                                 dec_insn.pc_inc +
 625                                 (insn.i_format.simmediate << 2);
 626                 else
 627                         *contpc = regs->cp0_epc +
 628                                 dec_insn.pc_inc +
 629                                 dec_insn.next_pc_inc;
 630                 return 1;
 631         case pop10_op:
 632         case pop30_op:
 633                 if (!cpu_has_mips_r6)
 634                         break;
 635                 if (insn.i_format.rt && !insn.i_format.rs)
 636                         regs->regs[31] = regs->cp0_epc + 4;
 637                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 638                         dec_insn.next_pc_inc;
 639
 640                 return 1;
 641 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 642         case lwc2_op: /* This is bbit0 on Octeon */
 643                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 644                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 645                 else
 646                         *contpc = regs->cp0_epc + 8;
 647                 return 1;
 648         case ldc2_op: /* This is bbit032 on Octeon */
 649                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 650                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 651                 else
 652                         *contpc = regs->cp0_epc + 8;
 653                 return 1;
 654         case swc2_op: /* This is bbit1 on Octeon */
 655                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 656                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 657                 else
 658                         *contpc = regs->cp0_epc + 8;
 659                 return 1;
 660         case sdc2_op: /* This is bbit132 on Octeon */
 661                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 662                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 663                 else
 664                         *contpc = regs->cp0_epc + 8;
 665                 return 1;
 666 #else
 667         case bc6_op:
 668                 /*
 669                  * Only valid for MIPS R6 but we can still end up
 670                  * here from a broken userland so just tell emulator
 671                  * this is not a branch and let it break later on.
 672                  */
 673                 if  (!cpu_has_mips_r6)
 674                         break;
 675                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 676                         dec_insn.next_pc_inc;
 677
 678                 return 1;
 679         case balc6_op:
 680                 if (!cpu_has_mips_r6)
 681                         break;
 682                 regs->regs[31] = regs->cp0_epc + 4;
 683                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 684                         dec_insn.next_pc_inc;
 685
 686                 return 1;
 687         case pop66_op:
 688                 if (!cpu_has_mips_r6)
 689                         break;
 690                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 691                         dec_insn.next_pc_inc;
 692
 693                 return 1;
 694         case pop76_op:
 695                 if (!cpu_has_mips_r6)
 696                         break;
 697                 if (!insn.i_format.rs)
 698                         regs->regs[31] = regs->cp0_epc + 4;
 699                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 700                         dec_insn.next_pc_inc;
 701
 702                 return 1;
 703 #endif
 704         case cop0_op:
 705         case cop1_op:
 706                 /* Need to check for R6 bc1nez and bc1eqz branches */
 707                 if (cpu_has_mips_r6 &&
 708                     ((insn.i_format.rs == bc1eqz_op) ||
 709                      (insn.i_format.rs == bc1nez_op))) {
 710                         bit = 0;
 711                         fpr = &current->thread.fpu.fpr[insn.i_format.rt];
 712                         bit0 = get_fpr32(fpr, 0) & 0x1;
 713                         switch (insn.i_format.rs) {
 714                         case bc1eqz_op:
 715                                 bit = bit0 == 0;
 716                                 break;
 717                         case bc1nez_op:
 718                                 bit = bit0 != 0;
 719                                 break;
 720                         }
 721                         if (bit)
 722                                 *contpc = regs->cp0_epc +
 723                                         dec_insn.pc_inc +
 724                                         (insn.i_format.simmediate << 2);
 725                         else
 726                                 *contpc = regs->cp0_epc +
 727                                         dec_insn.pc_inc +
 728                                         dec_insn.next_pc_inc;
 729
 730                         return 1;
 731                 }
 732                 /* R2/R6 compatible cop1 instruction. Fall through */
 733         case cop2_op:
 734         case cop1x_op:
 735                 if (insn.i_format.rs == bc_op) {
 736                         preempt_disable();
 737                         if (is_fpu_owner())
 738                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 739                         else
 740                                 fcr31 = current->thread.fpu.fcr31;
 741                         preempt_enable();
 742
 743                         bit = (insn.i_format.rt >> 2);
 744                         bit += (bit != 0);
 745                         bit += 23;
 746                         switch (insn.i_format.rt & 3) {
 747                         case 0: /* bc1f */
 748                         case 2: /* bc1fl */
 749                                 if (~fcr31 & (1 << bit))
 750                                         *contpc = regs->cp0_epc +
 751                                                 dec_insn.pc_inc +
 752                                                 (insn.i_format.simmediate << 2);
 753                                 else
 754                                         *contpc = regs->cp0_epc +
 755                                                 dec_insn.pc_inc +
 756                                                 dec_insn.next_pc_inc;
 757                                 return 1;
 758                         case 1: /* bc1t */
 759                         case 3: /* bc1tl */
 760                                 if (fcr31 & (1 << bit))
 761                                         *contpc = regs->cp0_epc +
 762                                                 dec_insn.pc_inc +
 763                                                 (insn.i_format.simmediate << 2);
 764                                 else
 765                                         *contpc = regs->cp0_epc +
 766                                                 dec_insn.pc_inc +
 767                                                 dec_insn.next_pc_inc;
 768                                 return 1;
 769                         }
 770                 }
 771                 break;
 772         }
 773         return 0;
 774 }
 775
 776 /*
 777  * In the Linux kernel, we support selection of FPR format on the
 778  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 779  * is hardwired to zero, which would imply a 32-bit FPU even for
 780  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 781  * FPU emu is slow and bulky and optimizing this function offers fairly
 782  * sizeable benefits so we try to be clever and make this function return
 783  * a constant whenever possible, that is on 64-bit kernels without O32
 784  * compatibility enabled and on 32-bit without 64-bit FPU support.
 785  */
 786 static inline int cop1_64bit(struct pt_regs *xcp)
 787 {
 788         if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
 789                 return 1;
 790         else if (IS_ENABLED(CONFIG_32BIT) &&
 791                  !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
 792                 return 0;
 793
 794         return !test_thread_flag(TIF_32BIT_FPREGS);
 795 }
 796
 797 static inline bool hybrid_fprs(void)
 798 {
 799         return test_thread_flag(TIF_HYBRID_FPREGS);
 800 }
 801
 802 #define SIFROMREG(si, x)                                                \
 803 do {                                                                    \
 804         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 805                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 806         else                                                            \
 807                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 808 } while (0)
 809
 810 #define SITOREG(si, x)                                                  \
 811 do {                                                                    \
 812         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 813                 unsigned i;                                             \
 814                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 815                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 816                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 817         } else {                                                        \
 818                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 819         }                                                               \
 820 } while (0)
 821
 822 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 823
 824 #define SITOHREG(si, x)                                                 \
 825 do {                                                                    \
 826         unsigned i;                                                     \
 827         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 828         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 829                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 830 } while (0)
 831
 832 #define DIFROMREG(di, x)                                                \
 833         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 834
 835 #define DITOREG(di, x)                                                  \
 836 do {                                                                    \
 837         unsigned fpr, i;                                                \
 838         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 839         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 840         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 841                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 842 } while (0)
 843
 844 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 845 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 846 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 847 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 848
 849 /*
 850  * Emulate a CFC1 instruction.
 851  */
 852 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 853                             mips_instruction ir)
 854 {
 855         u32 fcr31 = ctx->fcr31;
 856         u32 value = 0;
 857
 858         switch (MIPSInst_RD(ir)) {
 859         case FPCREG_CSR:
 860                 value = fcr31;
 861                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 862                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 863                 break;
 864
 865         case FPCREG_FENR:
 866                 if (!cpu_has_mips_r)
 867                         break;
 868                 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 869                         MIPS_FENR_FS;
 870                 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
 871                 pr_debug("%p gpr[%d]<-enr=%08x\n",
 872                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 873                 break;
 874
 875         case FPCREG_FEXR:
 876                 if (!cpu_has_mips_r)
 877                         break;
 878                 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 879                 pr_debug("%p gpr[%d]<-exr=%08x\n",
 880                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 881                 break;
 882
 883         case FPCREG_FCCR:
 884                 if (!cpu_has_mips_r)
 885                         break;
 886                 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 887                         MIPS_FCCR_COND0;
 888                 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 889                          (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
 890                 pr_debug("%p gpr[%d]<-ccr=%08x\n",
 891                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 892                 break;
 893
 894         case FPCREG_RID:
 895                 value = boot_cpu_data.fpu_id;
 896                 break;
 897
 898         default:
 899                 break;
 900         }
 901
 902         if (MIPSInst_RT(ir))
 903                 xcp->regs[MIPSInst_RT(ir)] = value;
 904 }
 905
 906 /*
 907  * Emulate a CTC1 instruction.
 908  */
 909 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 910                             mips_instruction ir)
 911 {
 912         u32 fcr31 = ctx->fcr31;
 913         u32 value;
 914         u32 mask;
 915
 916         if (MIPSInst_RT(ir) == 0)
 917                 value = 0;
 918         else
 919                 value = xcp->regs[MIPSInst_RT(ir)];
 920
 921         switch (MIPSInst_RD(ir)) {
 922         case FPCREG_CSR:
 923                 pr_debug("%p gpr[%d]->csr=%08x\n",
 924                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 925
 926                 /* Preserve read-only bits.  */
 927                 mask = boot_cpu_data.fpu_msk31;
 928                 fcr31 = (value & ~mask) | (fcr31 & mask);
 929                 break;
 930
 931         case FPCREG_FENR:
 932                 if (!cpu_has_mips_r)
 933                         break;
 934                 pr_debug("%p gpr[%d]->enr=%08x\n",
 935                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 936                 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
 937                 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 938                          FPU_CSR_FS;
 939                 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
 940                 break;
 941
 942         case FPCREG_FEXR:
 943                 if (!cpu_has_mips_r)
 944                         break;
 945                 pr_debug("%p gpr[%d]->exr=%08x\n",
 946                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 947                 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 948                 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 949                 break;
 950
 951         case FPCREG_FCCR:
 952                 if (!cpu_has_mips_r)
 953                         break;
 954                 pr_debug("%p gpr[%d]->ccr=%08x\n",
 955                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 956                 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
 957                 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 958                          FPU_CSR_COND;
 959                 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 960                          FPU_CSR_CONDX;
 961                 break;
 962
 963         default:
 964                 break;
 965         }
 966
 967         ctx->fcr31 = fcr31;
 968 }
 969
 970 /*
 971  * Emulate the single floating point instruction pointed at by EPC.
 972  * Two instructions if the instruction is in a branch delay slot.
 973  */
 974
 975 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 976                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 977 {
 978         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 979         unsigned int cond, cbit, bit0;
 980         mips_instruction ir;
 981         int likely, pc_inc;
 982         union fpureg *fpr;
 983         u32 __user *wva;
 984         u64 __user *dva;
 985         u32 wval;
 986         u64 dval;
 987         int sig;
 988
 989         /*
 990          * These are giving gcc a gentle hint about what to expect in
 991          * dec_inst in order to do better optimization.
 992          */
 993         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 994                 unreachable();
 995
 996         /* XXX NEC Vr54xx bug workaround */
 997         if (delay_slot(xcp)) {
 998                 if (dec_insn.micro_mips_mode) {
 999                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
1000                                 clear_delay_slot(xcp);
1001                 } else {
1002                         if (!isBranchInstr(xcp, dec_insn, &contpc))
1003                                 clear_delay_slot(xcp);
1004                 }
1005         }
1006
1007         if (delay_slot(xcp)) {
1008                 /*
1009                  * The instruction to be emulated is in a branch delay slot
1010                  * which means that we have to  emulate the branch instruction
1011                  * BEFORE we do the cop1 instruction.
1012                  *
1013                  * This branch could be a COP1 branch, but in that case we
1014                  * would have had a trap for that instruction, and would not
1015                  * come through this route.
1016                  *
1017                  * Linux MIPS branch emulator operates on context, updating the
1018                  * cp0_epc.
1019                  */
1020                 ir = dec_insn.next_insn;  /* process delay slot instr */
1021                 pc_inc = dec_insn.next_pc_inc;
1022         } else {
1023                 ir = dec_insn.insn;       /* process current instr */
1024                 pc_inc = dec_insn.pc_inc;
1025         }
1026
1027         /*
1028          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1029          * instructions, we want to convert microMIPS FPU instructions
1030          * into MIPS32 instructions so that we could reuse all of the
1031          * FPU emulation code.
1032          *
1033          * NOTE: We cannot do this for branch instructions since they
1034          *       are not a subset. Example: Cannot emulate a 16-bit
1035          *       aligned target address with a MIPS32 instruction.
1036          */
1037         if (dec_insn.micro_mips_mode) {
1038                 /*
1039                  * If next instruction is a 16-bit instruction, then it
1040                  * it cannot be a FPU instruction. This could happen
1041                  * since we can be called for non-FPU instructions.
1042                  */
1043                 if ((pc_inc == 2) ||
1044                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1045                          == SIGILL))
1046                         return SIGILL;
1047         }
1048
1049 emul:
1050         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1051         MIPS_FPU_EMU_INC_STATS(emulated);
1052         switch (MIPSInst_OPCODE(ir)) {
1053         case ldc1_op:
1054                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1055                                      MIPSInst_SIMM(ir));
1056                 MIPS_FPU_EMU_INC_STATS(loads);
1057
1058                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1059                         MIPS_FPU_EMU_INC_STATS(errors);
1060                         *fault_addr = dva;
1061                         return SIGBUS;
1062                 }
1063                 if (__get_user(dval, dva)) {
1064                         MIPS_FPU_EMU_INC_STATS(errors);
1065                         *fault_addr = dva;
1066                         return SIGSEGV;
1067                 }
1068                 DITOREG(dval, MIPSInst_RT(ir));
1069                 break;
1070
1071         case sdc1_op:
1072                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1073                                       MIPSInst_SIMM(ir));
1074                 MIPS_FPU_EMU_INC_STATS(stores);
1075                 DIFROMREG(dval, MIPSInst_RT(ir));
1076                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1077                         MIPS_FPU_EMU_INC_STATS(errors);
1078                         *fault_addr = dva;
1079                         return SIGBUS;
1080                 }
1081                 if (__put_user(dval, dva)) {
1082                         MIPS_FPU_EMU_INC_STATS(errors);
1083                         *fault_addr = dva;
1084                         return SIGSEGV;
1085                 }
1086                 break;
1087
1088         case lwc1_op:
1089                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1090                                       MIPSInst_SIMM(ir));
1091                 MIPS_FPU_EMU_INC_STATS(loads);
1092                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1093                         MIPS_FPU_EMU_INC_STATS(errors);
1094                         *fault_addr = wva;
1095                         return SIGBUS;
1096                 }
1097                 if (__get_user(wval, wva)) {
1098                         MIPS_FPU_EMU_INC_STATS(errors);
1099                         *fault_addr = wva;
1100                         return SIGSEGV;
1101                 }
1102                 SITOREG(wval, MIPSInst_RT(ir));
1103                 break;
1104
1105         case swc1_op:
1106                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1107                                       MIPSInst_SIMM(ir));
1108                 MIPS_FPU_EMU_INC_STATS(stores);
1109                 SIFROMREG(wval, MIPSInst_RT(ir));
1110                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1111                         MIPS_FPU_EMU_INC_STATS(errors);
1112                         *fault_addr = wva;
1113                         return SIGBUS;
1114                 }
1115                 if (__put_user(wval, wva)) {
1116                         MIPS_FPU_EMU_INC_STATS(errors);
1117                         *fault_addr = wva;
1118                         return SIGSEGV;
1119                 }
1120                 break;
1121
1122         case cop1_op:
1123                 switch (MIPSInst_RS(ir)) {
1124                 case dmfc_op:
1125                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1126                                 return SIGILL;
1127
1128                         /* copregister fs -> gpr[rt] */
1129                         if (MIPSInst_RT(ir) != 0) {
1130                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1131                                         MIPSInst_RD(ir));
1132                         }
1133                         break;
1134
1135                 case dmtc_op:
1136                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1137                                 return SIGILL;
1138
1139                         /* copregister fs <- rt */
1140                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1141                         break;
1142
1143                 case mfhc_op:
1144                         if (!cpu_has_mips_r2_r6)
1145                                 return SIGILL;
1146
1147                         /* copregister rd -> gpr[rt] */
1148                         if (MIPSInst_RT(ir) != 0) {
1149                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1150                                         MIPSInst_RD(ir));
1151                         }
1152                         break;
1153
1154                 case mthc_op:
1155                         if (!cpu_has_mips_r2_r6)
1156                                 return SIGILL;
1157
1158                         /* copregister rd <- gpr[rt] */
1159                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1160                         break;
1161
1162                 case mfc_op:
1163                         /* copregister rd -> gpr[rt] */
1164                         if (MIPSInst_RT(ir) != 0) {
1165                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1166                                         MIPSInst_RD(ir));
1167                         }
1168                         break;
1169
1170                 case mtc_op:
1171                         /* copregister rd <- rt */
1172                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1173                         break;
1174
1175                 case cfc_op:
1176                         /* cop control register rd -> gpr[rt] */
1177                         cop1_cfc(xcp, ctx, ir);
1178                         break;
1179
1180                 case ctc_op:
1181                         /* copregister rd <- rt */
1182                         cop1_ctc(xcp, ctx, ir);
1183                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1184                                 return SIGFPE;
1185                         }
1186                         break;
1187
1188                 case bc1eqz_op:
1189                 case bc1nez_op:
1190                         if (!cpu_has_mips_r6 || delay_slot(xcp))
1191                                 return SIGILL;
1192
1193                         cond = likely = 0;
1194                         fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
1195                         bit0 = get_fpr32(fpr, 0) & 0x1;
1196                         switch (MIPSInst_RS(ir)) {
1197                         case bc1eqz_op:
1198                                 cond = bit0 == 0;
1199                                 break;
1200                         case bc1nez_op:
1201                                 cond = bit0 != 0;
1202                                 break;
1203                         }
1204                         goto branch_common;
1205
1206                 case bc_op:
1207                         if (delay_slot(xcp))
1208                                 return SIGILL;
1209
1210                         if (cpu_has_mips_4_5_r)
1211                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1212                         else
1213                                 cbit = FPU_CSR_COND;
1214                         cond = ctx->fcr31 & cbit;
1215
1216                         likely = 0;
1217                         switch (MIPSInst_RT(ir) & 3) {
1218                         case bcfl_op:
1219                                 if (cpu_has_mips_2_3_4_5_r)
1220                                         likely = 1;
1221                                 /* Fall through */
1222                         case bcf_op:
1223                                 cond = !cond;
1224                                 break;
1225                         case bctl_op:
1226                                 if (cpu_has_mips_2_3_4_5_r)
1227                                         likely = 1;
1228                                 /* Fall through */
1229                         case bct_op:
1230                                 break;
1231                         }
1232 branch_common:
1233                         set_delay_slot(xcp);
1234                         if (cond) {
1235                                 /*
1236                                  * Branch taken: emulate dslot instruction
1237                                  */
1238                                 unsigned long bcpc;
1239
1240                                 /*
1241                                  * Remember EPC at the branch to point back
1242                                  * at so that any delay-slot instruction
1243                                  * signal is not silently ignored.
1244                                  */
1245                                 bcpc = xcp->cp0_epc;
1246                                 xcp->cp0_epc += dec_insn.pc_inc;
1247
1248                                 contpc = MIPSInst_SIMM(ir);
1249                                 ir = dec_insn.next_insn;
1250                                 if (dec_insn.micro_mips_mode) {
1251                                         contpc = (xcp->cp0_epc + (contpc << 1));
1252
1253                                         /* If 16-bit instruction, not FPU. */
1254                                         if ((dec_insn.next_pc_inc == 2) ||
1255                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1256
1257                                                 /*
1258                                                  * Since this instruction will
1259                                                  * be put on the stack with
1260                                                  * 32-bit words, get around
1261                                                  * this problem by putting a
1262                                                  * NOP16 as the second one.
1263                                                  */
1264                                                 if (dec_insn.next_pc_inc == 2)
1265                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1266
1267                                                 /*
1268                                                  * Single step the non-CP1
1269                                                  * instruction in the dslot.
1270                                                  */
1271                                                 sig = mips_dsemul(xcp, ir,
1272                                                                   bcpc, contpc);
1273                                                 if (sig < 0)
1274                                                         break;
1275                                                 if (sig)
1276                                                         xcp->cp0_epc = bcpc;
1277                                                 /*
1278                                                  * SIGILL forces out of
1279                                                  * the emulation loop.
1280                                                  */
1281                                                 return sig ? sig : SIGILL;
1282                                         }
1283                                 } else
1284                                         contpc = (xcp->cp0_epc + (contpc << 2));
1285
1286                                 switch (MIPSInst_OPCODE(ir)) {
1287                                 case lwc1_op:
1288                                 case swc1_op:
1289                                         goto emul;
1290
1291                                 case ldc1_op:
1292                                 case sdc1_op:
1293                                         if (cpu_has_mips_2_3_4_5_r)
1294                                                 goto emul;
1295
1296                                         goto bc_sigill;
1297
1298                                 case cop1_op:
1299                                         goto emul;
1300
1301                                 case cop1x_op:
1302                                         if (cpu_has_mips_4_5_64_r2_r6)
1303                                                 /* its one of ours */
1304                                                 goto emul;
1305
1306                                         goto bc_sigill;
1307
1308                                 case spec_op:
1309                                         switch (MIPSInst_FUNC(ir)) {
1310                                         case movc_op:
1311                                                 if (cpu_has_mips_4_5_r)
1312                                                         goto emul;
1313
1314                                                 goto bc_sigill;
1315                                         }
1316                                         break;
1317
1318                                 bc_sigill:
1319                                         xcp->cp0_epc = bcpc;
1320                                         return SIGILL;
1321                                 }
1322
1323                                 /*
1324                                  * Single step the non-cp1
1325                                  * instruction in the dslot
1326                                  */
1327                                 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1328                                 if (sig < 0)
1329                                         break;
1330                                 if (sig)
1331                                         xcp->cp0_epc = bcpc;
1332                                 /* SIGILL forces out of the emulation loop.  */
1333                                 return sig ? sig : SIGILL;
1334                         } else if (likely) {    /* branch not taken */
1335                                 /*
1336                                  * branch likely nullifies
1337                                  * dslot if not taken
1338                                  */
1339                                 xcp->cp0_epc += dec_insn.pc_inc;
1340                                 contpc += dec_insn.pc_inc;
1341                                 /*
1342                                  * else continue & execute
1343                                  * dslot as normal insn
1344                                  */
1345                         }
1346                         break;
1347
1348                 default:
1349                         if (!(MIPSInst_RS(ir) & 0x10))
1350                                 return SIGILL;
1351
1352                         /* a real fpu computation instruction */
1353                         if ((sig = fpu_emu(xcp, ctx, ir)))
1354                                 return sig;
1355                 }
1356                 break;
1357
1358         case cop1x_op:
1359                 if (!cpu_has_mips_4_5_64_r2_r6)
1360                         return SIGILL;
1361
1362                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1363                 if (sig)
1364                         return sig;
1365                 break;
1366
1367         case spec_op:
1368                 if (!cpu_has_mips_4_5_r)
1369                         return SIGILL;
1370
1371                 if (MIPSInst_FUNC(ir) != movc_op)
1372                         return SIGILL;
1373                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1374                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1375                         xcp->regs[MIPSInst_RD(ir)] =
1376                                 xcp->regs[MIPSInst_RS(ir)];
1377                 break;
1378         default:
1379                 return SIGILL;
1380         }
1381
1382         /* we did it !! */
1383         xcp->cp0_epc = contpc;
1384         clear_delay_slot(xcp);
1385
1386         return 0;
1387 }
1388
1389 /*
1390  * Conversion table from MIPS compare ops 48-63
1391  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1392  */
1393 static const unsigned char cmptab[8] = {
1394         0,                      /* cmp_0 (sig) cmp_sf */
1395         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1396         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1397         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1398         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1399         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1400         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1401         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1402 };
1403
1404 static const unsigned char negative_cmptab[8] = {
1405         0, /* Reserved */
1406         IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1407         IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1408         IEEE754_CLT | IEEE754_CGT,
1409         /* Reserved */
1410 };
1411
1412
1413 /*
1414  * Additional MIPS4 instructions
1415  */
1416
1417 #define DEF3OP(name, p, f1, f2, f3)                                     \
1418 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1419         union ieee754##p s, union ieee754##p t)                         \
1420 {                                                                       \
1421         struct _ieee754_csr ieee754_csr_save;                           \
1422         s = f1(s, t);                                                   \
1423         ieee754_csr_save = ieee754_csr;                                 \
1424         s = f2(s, r);                                                   \
1425         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1426         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1427         s = f3(s);                                                      \
1428         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1429         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1430         return s;                                                       \
1431 }
1432
1433 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1434 {
1435         return ieee754dp_div(ieee754dp_one(0), d);
1436 }
1437
1438 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1439 {
1440         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1441 }
1442
1443 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1444 {
1445         return ieee754sp_div(ieee754sp_one(0), s);
1446 }
1447
1448 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1449 {
1450         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1451 }
1452
1453 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1454 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1455 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1456 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1457 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1458 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1459 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1460 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1461
1462 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1463         mips_instruction ir, void *__user *fault_addr)
1464 {
1465         unsigned rcsr = 0;      /* resulting csr */
1466
1467         MIPS_FPU_EMU_INC_STATS(cp1xops);
1468
1469         switch (MIPSInst_FMA_FFMT(ir)) {
1470         case s_fmt:{            /* 0 */
1471
1472                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1473                 union ieee754sp fd, fr, fs, ft;
1474                 u32 __user *va;
1475                 u32 val;
1476
1477                 switch (MIPSInst_FUNC(ir)) {
1478                 case lwxc1_op:
1479                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1480                                 xcp->regs[MIPSInst_FT(ir)]);
1481
1482                         MIPS_FPU_EMU_INC_STATS(loads);
1483                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1484                                 MIPS_FPU_EMU_INC_STATS(errors);
1485                                 *fault_addr = va;
1486                                 return SIGBUS;
1487                         }
1488                         if (__get_user(val, va)) {
1489                                 MIPS_FPU_EMU_INC_STATS(errors);
1490                                 *fault_addr = va;
1491                                 return SIGSEGV;
1492                         }
1493                         SITOREG(val, MIPSInst_FD(ir));
1494                         break;
1495
1496                 case swxc1_op:
1497                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1498                                 xcp->regs[MIPSInst_FT(ir)]);
1499
1500                         MIPS_FPU_EMU_INC_STATS(stores);
1501
1502                         SIFROMREG(val, MIPSInst_FS(ir));
1503                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1504                                 MIPS_FPU_EMU_INC_STATS(errors);
1505                                 *fault_addr = va;
1506                                 return SIGBUS;
1507                         }
1508                         if (put_user(val, va)) {
1509                                 MIPS_FPU_EMU_INC_STATS(errors);
1510                                 *fault_addr = va;
1511                                 return SIGSEGV;
1512                         }
1513                         break;
1514
1515                 case madd_s_op:
1516                         handler = fpemu_sp_madd;
1517                         goto scoptop;
1518                 case msub_s_op:
1519                         handler = fpemu_sp_msub;
1520                         goto scoptop;
1521                 case nmadd_s_op:
1522                         handler = fpemu_sp_nmadd;
1523                         goto scoptop;
1524                 case nmsub_s_op:
1525                         handler = fpemu_sp_nmsub;
1526                         goto scoptop;
1527
1528                       scoptop:
1529                         SPFROMREG(fr, MIPSInst_FR(ir));
1530                         SPFROMREG(fs, MIPSInst_FS(ir));
1531                         SPFROMREG(ft, MIPSInst_FT(ir));
1532                         fd = (*handler) (fr, fs, ft);
1533                         SPTOREG(fd, MIPSInst_FD(ir));
1534
1535                       copcsr:
1536                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1537                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1538                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1539                         }
1540                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1541                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1542                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1543                         }
1544                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1545                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1546                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1547                         }
1548                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1549                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1550                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1551                         }
1552
1553                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1554                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1555                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1556                                    ctx->fcr31); */
1557                                 return SIGFPE;
1558                         }
1559
1560                         break;
1561
1562                 default:
1563                         return SIGILL;
1564                 }
1565                 break;
1566         }
1567
1568         case d_fmt:{            /* 1 */
1569                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1570                 union ieee754dp fd, fr, fs, ft;
1571                 u64 __user *va;
1572                 u64 val;
1573
1574                 switch (MIPSInst_FUNC(ir)) {
1575                 case ldxc1_op:
1576                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1577                                 xcp->regs[MIPSInst_FT(ir)]);
1578
1579                         MIPS_FPU_EMU_INC_STATS(loads);
1580                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1581                                 MIPS_FPU_EMU_INC_STATS(errors);
1582                                 *fault_addr = va;
1583                                 return SIGBUS;
1584                         }
1585                         if (__get_user(val, va)) {
1586                                 MIPS_FPU_EMU_INC_STATS(errors);
1587                                 *fault_addr = va;
1588                                 return SIGSEGV;
1589                         }
1590                         DITOREG(val, MIPSInst_FD(ir));
1591                         break;
1592
1593                 case sdxc1_op:
1594                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1595                                 xcp->regs[MIPSInst_FT(ir)]);
1596
1597                         MIPS_FPU_EMU_INC_STATS(stores);
1598                         DIFROMREG(val, MIPSInst_FS(ir));
1599                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1600                                 MIPS_FPU_EMU_INC_STATS(errors);
1601                                 *fault_addr = va;
1602                                 return SIGBUS;
1603                         }
1604                         if (__put_user(val, va)) {
1605                                 MIPS_FPU_EMU_INC_STATS(errors);
1606                                 *fault_addr = va;
1607                                 return SIGSEGV;
1608                         }
1609                         break;
1610
1611                 case madd_d_op:
1612                         handler = fpemu_dp_madd;
1613                         goto dcoptop;
1614                 case msub_d_op:
1615                         handler = fpemu_dp_msub;
1616                         goto dcoptop;
1617                 case nmadd_d_op:
1618                         handler = fpemu_dp_nmadd;
1619                         goto dcoptop;
1620                 case nmsub_d_op:
1621                         handler = fpemu_dp_nmsub;
1622                         goto dcoptop;
1623
1624                       dcoptop:
1625                         DPFROMREG(fr, MIPSInst_FR(ir));
1626                         DPFROMREG(fs, MIPSInst_FS(ir));
1627                         DPFROMREG(ft, MIPSInst_FT(ir));
1628                         fd = (*handler) (fr, fs, ft);
1629                         DPTOREG(fd, MIPSInst_FD(ir));
1630                         goto copcsr;
1631
1632                 default:
1633                         return SIGILL;
1634                 }
1635                 break;
1636         }
1637
1638         case 0x3:
1639                 if (MIPSInst_FUNC(ir) != pfetch_op)
1640                         return SIGILL;
1641
1642                 /* ignore prefx operation */
1643                 break;
1644
1645         default:
1646                 return SIGILL;
1647         }
1648
1649         return 0;
1650 }
1651
1652
1653
1654 /*
1655  * Emulate a single COP1 arithmetic instruction.
1656  */
1657 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1658         mips_instruction ir)
1659 {
1660         int rfmt;               /* resulting format */
1661         unsigned rcsr = 0;      /* resulting csr */
1662         unsigned int oldrm;
1663         unsigned int cbit;
1664         unsigned cond;
1665         union {
1666                 union ieee754dp d;
1667                 union ieee754sp s;
1668                 int w;
1669                 s64 l;
1670         } rv;                   /* resulting value */
1671         u64 bits;
1672
1673         MIPS_FPU_EMU_INC_STATS(cp1ops);
1674         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1675         case s_fmt: {           /* 0 */
1676                 union {
1677                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1678                         union ieee754sp(*u) (union ieee754sp);
1679                 } handler;
1680                 union ieee754sp fd, fs, ft;
1681
1682                 switch (MIPSInst_FUNC(ir)) {
1683                         /* binary ops */
1684                 case fadd_op:
1685                         handler.b = ieee754sp_add;
1686                         goto scopbop;
1687                 case fsub_op:
1688                         handler.b = ieee754sp_sub;
1689                         goto scopbop;
1690                 case fmul_op:
1691                         handler.b = ieee754sp_mul;
1692                         goto scopbop;
1693                 case fdiv_op:
1694                         handler.b = ieee754sp_div;
1695                         goto scopbop;
1696
1697                         /* unary  ops */
1698                 case fsqrt_op:
1699                         if (!cpu_has_mips_2_3_4_5_r)
1700                                 return SIGILL;
1701
1702                         handler.u = ieee754sp_sqrt;
1703                         goto scopuop;
1704
1705                 /*
1706                  * Note that on some MIPS IV implementations such as the
1707                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1708                  * achieve full IEEE-754 accuracy - however this emulator does.
1709                  */
1710                 case frsqrt_op:
1711                         if (!cpu_has_mips_4_5_64_r2_r6)
1712                                 return SIGILL;
1713
1714                         handler.u = fpemu_sp_rsqrt;
1715                         goto scopuop;
1716
1717                 case frecip_op:
1718                         if (!cpu_has_mips_4_5_64_r2_r6)
1719                                 return SIGILL;
1720
1721                         handler.u = fpemu_sp_recip;
1722                         goto scopuop;
1723
1724                 case fmovc_op:
1725                         if (!cpu_has_mips_4_5_r)
1726                                 return SIGILL;
1727
1728                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1729                         if (((ctx->fcr31 & cond) != 0) !=
1730                                 ((MIPSInst_FT(ir) & 1) != 0))
1731                                 return 0;
1732                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1733                         break;
1734
1735                 case fmovz_op:
1736                         if (!cpu_has_mips_4_5_r)
1737                                 return SIGILL;
1738
1739                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1740                                 return 0;
1741                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1742                         break;
1743
1744                 case fmovn_op:
1745                         if (!cpu_has_mips_4_5_r)
1746                                 return SIGILL;
1747
1748                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1749                                 return 0;
1750                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1751                         break;
1752
1753                 case fseleqz_op:
1754                         if (!cpu_has_mips_r6)
1755                                 return SIGILL;
1756
1757                         SPFROMREG(rv.s, MIPSInst_FT(ir));
1758                         if (rv.w & 0x1)
1759                                 rv.w = 0;
1760                         else
1761                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1762                         break;
1763
1764                 case fselnez_op:
1765                         if (!cpu_has_mips_r6)
1766                                 return SIGILL;
1767
1768                         SPFROMREG(rv.s, MIPSInst_FT(ir));
1769                         if (rv.w & 0x1)
1770                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1771                         else
1772                                 rv.w = 0;
1773                         break;
1774
1775                 case fmaddf_op: {
1776                         union ieee754sp ft, fs, fd;
1777
1778                         if (!cpu_has_mips_r6)
1779                                 return SIGILL;
1780
1781                         SPFROMREG(ft, MIPSInst_FT(ir));
1782                         SPFROMREG(fs, MIPSInst_FS(ir));
1783                         SPFROMREG(fd, MIPSInst_FD(ir));
1784                         rv.s = ieee754sp_maddf(fd, fs, ft);
1785                         break;
1786                 }
1787
1788                 case fmsubf_op: {
1789                         union ieee754sp ft, fs, fd;
1790
1791                         if (!cpu_has_mips_r6)
1792                                 return SIGILL;
1793
1794                         SPFROMREG(ft, MIPSInst_FT(ir));
1795                         SPFROMREG(fs, MIPSInst_FS(ir));
1796                         SPFROMREG(fd, MIPSInst_FD(ir));
1797                         rv.s = ieee754sp_msubf(fd, fs, ft);
1798                         break;
1799                 }
1800
1801                 case frint_op: {
1802                         union ieee754sp fs;
1803
1804                         if (!cpu_has_mips_r6)
1805                                 return SIGILL;
1806
1807                         SPFROMREG(fs, MIPSInst_FS(ir));
1808                         rv.l = ieee754sp_tlong(fs);
1809                         rv.s = ieee754sp_flong(rv.l);
1810                         goto copcsr;
1811                 }
1812
1813                 case fclass_op: {
1814                         union ieee754sp fs;
1815
1816                         if (!cpu_has_mips_r6)
1817                                 return SIGILL;
1818
1819                         SPFROMREG(fs, MIPSInst_FS(ir));
1820                         rv.w = ieee754sp_2008class(fs);
1821                         rfmt = w_fmt;
1822                         break;
1823                 }
1824
1825                 case fmin_op: {
1826                         union ieee754sp fs, ft;
1827
1828                         if (!cpu_has_mips_r6)
1829                                 return SIGILL;
1830
1831                         SPFROMREG(ft, MIPSInst_FT(ir));
1832                         SPFROMREG(fs, MIPSInst_FS(ir));
1833                         rv.s = ieee754sp_fmin(fs, ft);
1834                         break;
1835                 }
1836
1837                 case fmina_op: {
1838                         union ieee754sp fs, ft;
1839
1840                         if (!cpu_has_mips_r6)
1841                                 return SIGILL;
1842
1843                         SPFROMREG(ft, MIPSInst_FT(ir));
1844                         SPFROMREG(fs, MIPSInst_FS(ir));
1845                         rv.s = ieee754sp_fmina(fs, ft);
1846                         break;
1847                 }
1848
1849                 case fmax_op: {
1850                         union ieee754sp fs, ft;
1851
1852                         if (!cpu_has_mips_r6)
1853                                 return SIGILL;
1854
1855                         SPFROMREG(ft, MIPSInst_FT(ir));
1856                         SPFROMREG(fs, MIPSInst_FS(ir));
1857                         rv.s = ieee754sp_fmax(fs, ft);
1858                         break;
1859                 }
1860
1861                 case fmaxa_op: {
1862                         union ieee754sp fs, ft;
1863
1864                         if (!cpu_has_mips_r6)
1865                                 return SIGILL;
1866
1867                         SPFROMREG(ft, MIPSInst_FT(ir));
1868                         SPFROMREG(fs, MIPSInst_FS(ir));
1869                         rv.s = ieee754sp_fmaxa(fs, ft);
1870                         break;
1871                 }
1872
1873                 case fabs_op:
1874                         handler.u = ieee754sp_abs;
1875                         goto scopuop;
1876
1877                 case fneg_op:
1878                         handler.u = ieee754sp_neg;
1879                         goto scopuop;
1880
1881                 case fmov_op:
1882                         /* an easy one */
1883                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1884                         goto copcsr;
1885
1886                         /* binary op on handler */
1887 scopbop:
1888                         SPFROMREG(fs, MIPSInst_FS(ir));
1889                         SPFROMREG(ft, MIPSInst_FT(ir));
1890
1891                         rv.s = (*handler.b) (fs, ft);
1892                         goto copcsr;
1893 scopuop:
1894                         SPFROMREG(fs, MIPSInst_FS(ir));
1895                         rv.s = (*handler.u) (fs);
1896                         goto copcsr;
1897 copcsr:
1898                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1899                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1900                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1901                         }
1902                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1903                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1904                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1905                         }
1906                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1907                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1908                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1909                         }
1910                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1911                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1912                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1913                         }
1914                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1915                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1916                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1917                         }
1918                         break;
1919
1920                         /* unary conv ops */
1921                 case fcvts_op:
1922                         return SIGILL;  /* not defined */
1923
1924                 case fcvtd_op:
1925                         SPFROMREG(fs, MIPSInst_FS(ir));
1926                         rv.d = ieee754dp_fsp(fs);
1927                         rfmt = d_fmt;
1928                         goto copcsr;
1929
1930                 case fcvtw_op:
1931                         SPFROMREG(fs, MIPSInst_FS(ir));
1932                         rv.w = ieee754sp_tint(fs);
1933                         rfmt = w_fmt;
1934                         goto copcsr;
1935
1936                 case fround_op:
1937                 case ftrunc_op:
1938                 case fceil_op:
1939                 case ffloor_op:
1940                         if (!cpu_has_mips_2_3_4_5_r)
1941                                 return SIGILL;
1942
1943                         oldrm = ieee754_csr.rm;
1944                         SPFROMREG(fs, MIPSInst_FS(ir));
1945                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1946                         rv.w = ieee754sp_tint(fs);
1947                         ieee754_csr.rm = oldrm;
1948                         rfmt = w_fmt;
1949                         goto copcsr;
1950
1951                 case fsel_op:
1952                         if (!cpu_has_mips_r6)
1953                                 return SIGILL;
1954
1955                         SPFROMREG(fd, MIPSInst_FD(ir));
1956                         if (fd.bits & 0x1)
1957                                 SPFROMREG(rv.s, MIPSInst_FT(ir));
1958                         else
1959                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1960                         break;
1961
1962                 case fcvtl_op:
1963                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1964                                 return SIGILL;
1965
1966                         SPFROMREG(fs, MIPSInst_FS(ir));
1967                         rv.l = ieee754sp_tlong(fs);
1968                         rfmt = l_fmt;
1969                         goto copcsr;
1970
1971                 case froundl_op:
1972                 case ftruncl_op:
1973                 case fceill_op:
1974                 case ffloorl_op:
1975                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1976                                 return SIGILL;
1977
1978                         oldrm = ieee754_csr.rm;
1979                         SPFROMREG(fs, MIPSInst_FS(ir));
1980                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1981                         rv.l = ieee754sp_tlong(fs);
1982                         ieee754_csr.rm = oldrm;
1983                         rfmt = l_fmt;
1984                         goto copcsr;
1985
1986                 default:
1987                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1988                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1989                                 union ieee754sp fs, ft;
1990
1991                                 SPFROMREG(fs, MIPSInst_FS(ir));
1992                                 SPFROMREG(ft, MIPSInst_FT(ir));
1993                                 rv.w = ieee754sp_cmp(fs, ft,
1994                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1995                                 rfmt = -1;
1996                                 if ((cmpop & 0x8) && ieee754_cxtest
1997                                         (IEEE754_INVALID_OPERATION))
1998                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1999                                 else
2000                                         goto copcsr;
2001
2002                         } else
2003                                 return SIGILL;
2004                         break;
2005                 }
2006                 break;
2007         }
2008
2009         case d_fmt: {
2010                 union ieee754dp fd, fs, ft;
2011                 union {
2012                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2013                         union ieee754dp(*u) (union ieee754dp);
2014                 } handler;
2015
2016                 switch (MIPSInst_FUNC(ir)) {
2017                         /* binary ops */
2018                 case fadd_op:
2019                         handler.b = ieee754dp_add;
2020                         goto dcopbop;
2021                 case fsub_op:
2022                         handler.b = ieee754dp_sub;
2023                         goto dcopbop;
2024                 case fmul_op:
2025                         handler.b = ieee754dp_mul;
2026                         goto dcopbop;
2027                 case fdiv_op:
2028                         handler.b = ieee754dp_div;
2029                         goto dcopbop;
2030
2031                         /* unary  ops */
2032                 case fsqrt_op:
2033                         if (!cpu_has_mips_2_3_4_5_r)
2034                                 return SIGILL;
2035
2036                         handler.u = ieee754dp_sqrt;
2037                         goto dcopuop;
2038                 /*
2039                  * Note that on some MIPS IV implementations such as the
2040                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
2041                  * achieve full IEEE-754 accuracy - however this emulator does.
2042                  */
2043                 case frsqrt_op:
2044                         if (!cpu_has_mips_4_5_64_r2_r6)
2045                                 return SIGILL;
2046
2047                         handler.u = fpemu_dp_rsqrt;
2048                         goto dcopuop;
2049                 case frecip_op:
2050                         if (!cpu_has_mips_4_5_64_r2_r6)
2051                                 return SIGILL;
2052
2053                         handler.u = fpemu_dp_recip;
2054                         goto dcopuop;
2055                 case fmovc_op:
2056                         if (!cpu_has_mips_4_5_r)
2057                                 return SIGILL;
2058
2059                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2060                         if (((ctx->fcr31 & cond) != 0) !=
2061                                 ((MIPSInst_FT(ir) & 1) != 0))
2062                                 return 0;
2063                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2064                         break;
2065                 case fmovz_op:
2066                         if (!cpu_has_mips_4_5_r)
2067                                 return SIGILL;
2068
2069                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
2070                                 return 0;
2071                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2072                         break;
2073                 case fmovn_op:
2074                         if (!cpu_has_mips_4_5_r)
2075                                 return SIGILL;
2076
2077                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
2078                                 return 0;
2079                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2080                         break;
2081
2082                 case fseleqz_op:
2083                         if (!cpu_has_mips_r6)
2084                                 return SIGILL;
2085
2086                         DPFROMREG(rv.d, MIPSInst_FT(ir));
2087                         if (rv.l & 0x1)
2088                                 rv.l = 0;
2089                         else
2090                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2091                         break;
2092
2093                 case fselnez_op:
2094                         if (!cpu_has_mips_r6)
2095                                 return SIGILL;
2096
2097                         DPFROMREG(rv.d, MIPSInst_FT(ir));
2098                         if (rv.l & 0x1)
2099                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2100                         else
2101                                 rv.l = 0;
2102                         break;
2103
2104                 case fmaddf_op: {
2105                         union ieee754dp ft, fs, fd;
2106
2107                         if (!cpu_has_mips_r6)
2108                                 return SIGILL;
2109
2110                         DPFROMREG(ft, MIPSInst_FT(ir));
2111                         DPFROMREG(fs, MIPSInst_FS(ir));
2112                         DPFROMREG(fd, MIPSInst_FD(ir));
2113                         rv.d = ieee754dp_maddf(fd, fs, ft);
2114                         break;
2115                 }
2116
2117                 case fmsubf_op: {
2118                         union ieee754dp ft, fs, fd;
2119
2120                         if (!cpu_has_mips_r6)
2121                                 return SIGILL;
2122
2123                         DPFROMREG(ft, MIPSInst_FT(ir));
2124                         DPFROMREG(fs, MIPSInst_FS(ir));
2125                         DPFROMREG(fd, MIPSInst_FD(ir));
2126                         rv.d = ieee754dp_msubf(fd, fs, ft);
2127                         break;
2128                 }
2129
2130                 case frint_op: {
2131                         union ieee754dp fs;
2132
2133                         if (!cpu_has_mips_r6)
2134                                 return SIGILL;
2135
2136                         DPFROMREG(fs, MIPSInst_FS(ir));
2137                         rv.l = ieee754dp_tlong(fs);
2138                         rv.d = ieee754dp_flong(rv.l);
2139                         goto copcsr;
2140                 }
2141
2142                 case fclass_op: {
2143                         union ieee754dp fs;
2144
2145                         if (!cpu_has_mips_r6)
2146                                 return SIGILL;
2147
2148                         DPFROMREG(fs, MIPSInst_FS(ir));
2149                         rv.w = ieee754dp_2008class(fs);
2150                         rfmt = w_fmt;
2151                         break;
2152                 }
2153
2154                 case fmin_op: {
2155                         union ieee754dp fs, ft;
2156
2157                         if (!cpu_has_mips_r6)
2158                                 return SIGILL;
2159
2160                         DPFROMREG(ft, MIPSInst_FT(ir));
2161                         DPFROMREG(fs, MIPSInst_FS(ir));
2162                         rv.d = ieee754dp_fmin(fs, ft);
2163                         break;
2164                 }
2165
2166                 case fmina_op: {
2167                         union ieee754dp fs, ft;
2168
2169                         if (!cpu_has_mips_r6)
2170                                 return SIGILL;
2171
2172                         DPFROMREG(ft, MIPSInst_FT(ir));
2173                         DPFROMREG(fs, MIPSInst_FS(ir));
2174                         rv.d = ieee754dp_fmina(fs, ft);
2175                         break;
2176                 }
2177
2178                 case fmax_op: {
2179                         union ieee754dp fs, ft;
2180
2181                         if (!cpu_has_mips_r6)
2182                                 return SIGILL;
2183
2184                         DPFROMREG(ft, MIPSInst_FT(ir));
2185                         DPFROMREG(fs, MIPSInst_FS(ir));
2186                         rv.d = ieee754dp_fmax(fs, ft);
2187                         break;
2188                 }
2189
2190                 case fmaxa_op: {
2191                         union ieee754dp fs, ft;
2192
2193                         if (!cpu_has_mips_r6)
2194                                 return SIGILL;
2195
2196                         DPFROMREG(ft, MIPSInst_FT(ir));
2197                         DPFROMREG(fs, MIPSInst_FS(ir));
2198                         rv.d = ieee754dp_fmaxa(fs, ft);
2199                         break;
2200                 }
2201
2202                 case fabs_op:
2203                         handler.u = ieee754dp_abs;
2204                         goto dcopuop;
2205
2206                 case fneg_op:
2207                         handler.u = ieee754dp_neg;
2208                         goto dcopuop;
2209
2210                 case fmov_op:
2211                         /* an easy one */
2212                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2213                         goto copcsr;
2214
2215                         /* binary op on handler */
2216 dcopbop:
2217                         DPFROMREG(fs, MIPSInst_FS(ir));
2218                         DPFROMREG(ft, MIPSInst_FT(ir));
2219
2220                         rv.d = (*handler.b) (fs, ft);
2221                         goto copcsr;
2222 dcopuop:
2223                         DPFROMREG(fs, MIPSInst_FS(ir));
2224                         rv.d = (*handler.u) (fs);
2225                         goto copcsr;
2226
2227                 /*
2228                  * unary conv ops
2229                  */
2230                 case fcvts_op:
2231                         DPFROMREG(fs, MIPSInst_FS(ir));
2232                         rv.s = ieee754sp_fdp(fs);
2233                         rfmt = s_fmt;
2234                         goto copcsr;
2235
2236                 case fcvtd_op:
2237                         return SIGILL;  /* not defined */
2238
2239                 case fcvtw_op:
2240                         DPFROMREG(fs, MIPSInst_FS(ir));
2241                         rv.w = ieee754dp_tint(fs);      /* wrong */
2242                         rfmt = w_fmt;
2243                         goto copcsr;
2244
2245                 case fround_op:
2246                 case ftrunc_op:
2247                 case fceil_op:
2248                 case ffloor_op:
2249                         if (!cpu_has_mips_2_3_4_5_r)
2250                                 return SIGILL;
2251
2252                         oldrm = ieee754_csr.rm;
2253                         DPFROMREG(fs, MIPSInst_FS(ir));
2254                         ieee754_csr.rm = MIPSInst_FUNC(ir);
2255                         rv.w = ieee754dp_tint(fs);
2256                         ieee754_csr.rm = oldrm;
2257                         rfmt = w_fmt;
2258                         goto copcsr;
2259
2260                 case fsel_op:
2261                         if (!cpu_has_mips_r6)
2262                                 return SIGILL;
2263
2264                         DPFROMREG(fd, MIPSInst_FD(ir));
2265                         if (fd.bits & 0x1)
2266                                 DPFROMREG(rv.d, MIPSInst_FT(ir));
2267                         else
2268                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2269                         break;
2270
2271                 case fcvtl_op:
2272                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2273                                 return SIGILL;
2274
2275                         DPFROMREG(fs, MIPSInst_FS(ir));
2276                         rv.l = ieee754dp_tlong(fs);
2277                         rfmt = l_fmt;
2278                         goto copcsr;
2279
2280                 case froundl_op:
2281                 case ftruncl_op:
2282                 case fceill_op:
2283                 case ffloorl_op:
2284                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2285                                 return SIGILL;
2286
2287                         oldrm = ieee754_csr.rm;
2288                         DPFROMREG(fs, MIPSInst_FS(ir));
2289                         ieee754_csr.rm = MIPSInst_FUNC(ir);
2290                         rv.l = ieee754dp_tlong(fs);
2291                         ieee754_csr.rm = oldrm;
2292                         rfmt = l_fmt;
2293                         goto copcsr;
2294
2295                 default:
2296                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2297                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2298                                 union ieee754dp fs, ft;
2299
2300                                 DPFROMREG(fs, MIPSInst_FS(ir));
2301                                 DPFROMREG(ft, MIPSInst_FT(ir));
2302                                 rv.w = ieee754dp_cmp(fs, ft,
2303                                         cmptab[cmpop & 0x7], cmpop & 0x8);
2304                                 rfmt = -1;
2305                                 if ((cmpop & 0x8)
2306                                         &&
2307                                         ieee754_cxtest
2308                                         (IEEE754_INVALID_OPERATION))
2309                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2310                                 else
2311                                         goto copcsr;
2312
2313                         }
2314                         else {
2315                                 return SIGILL;
2316                         }
2317                         break;
2318                 }
2319                 break;
2320         }
2321
2322         case w_fmt: {
2323                 union ieee754dp fs;
2324
2325                 switch (MIPSInst_FUNC(ir)) {
2326                 case fcvts_op:
2327                         /* convert word to single precision real */
2328                         SPFROMREG(fs, MIPSInst_FS(ir));
2329                         rv.s = ieee754sp_fint(fs.bits);
2330                         rfmt = s_fmt;
2331                         goto copcsr;
2332                 case fcvtd_op:
2333                         /* convert word to double precision real */
2334                         SPFROMREG(fs, MIPSInst_FS(ir));
2335                         rv.d = ieee754dp_fint(fs.bits);
2336                         rfmt = d_fmt;
2337                         goto copcsr;
2338                 default: {
2339                         /* Emulating the new CMP.condn.fmt R6 instruction */
2340 #define CMPOP_MASK      0x7
2341 #define SIGN_BIT        (0x1 << 3)
2342 #define PREDICATE_BIT   (0x1 << 4)
2343
2344                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2345                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2346                         union ieee754sp fs, ft;
2347
2348                         /* This is an R6 only instruction */
2349                         if (!cpu_has_mips_r6 ||
2350                             (MIPSInst_FUNC(ir) & 0x20))
2351                                 return SIGILL;
2352
2353                         /* fmt is w_fmt for single precision so fix it */
2354                         rfmt = s_fmt;
2355                         /* default to false */
2356                         rv.w = 0;
2357
2358                         /* CMP.condn.S */
2359                         SPFROMREG(fs, MIPSInst_FS(ir));
2360                         SPFROMREG(ft, MIPSInst_FT(ir));
2361
2362                         /* positive predicates */
2363                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2364                                 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2365                                                   sig))
2366                                     rv.w = -1; /* true, all 1s */
2367                                 if ((sig) &&
2368                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2369                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2370                                 else
2371                                         goto copcsr;
2372                         } else {
2373                                 /* negative predicates */
2374                                 switch (cmpop) {
2375                                 case 1:
2376                                 case 2:
2377                                 case 3:
2378                                         if (ieee754sp_cmp(fs, ft,
2379                                                           negative_cmptab[cmpop],
2380                                                           sig))
2381                                                 rv.w = -1; /* true, all 1s */
2382                                         if (sig &&
2383                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2384                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2385                                         else
2386                                                 goto copcsr;
2387                                         break;
2388                                 default:
2389                                         /* Reserved R6 ops */
2390                                         pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2391                                         return SIGILL;
2392                                 }
2393                         }
2394                         break;
2395                         }
2396                 }
2397         }
2398
2399         case l_fmt:
2400
2401                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2402                         return SIGILL;
2403
2404                 DIFROMREG(bits, MIPSInst_FS(ir));
2405
2406                 switch (MIPSInst_FUNC(ir)) {
2407                 case fcvts_op:
2408                         /* convert long to single precision real */
2409                         rv.s = ieee754sp_flong(bits);
2410                         rfmt = s_fmt;
2411                         goto copcsr;
2412                 case fcvtd_op:
2413                         /* convert long to double precision real */
2414                         rv.d = ieee754dp_flong(bits);
2415                         rfmt = d_fmt;
2416                         goto copcsr;
2417                 default: {
2418                         /* Emulating the new CMP.condn.fmt R6 instruction */
2419                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2420                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2421                         union ieee754dp fs, ft;
2422
2423                         if (!cpu_has_mips_r6 ||
2424                             (MIPSInst_FUNC(ir) & 0x20))
2425                                 return SIGILL;
2426
2427                         /* fmt is l_fmt for double precision so fix it */
2428                         rfmt = d_fmt;
2429                         /* default to false */
2430                         rv.l = 0;
2431
2432                         /* CMP.condn.D */
2433                         DPFROMREG(fs, MIPSInst_FS(ir));
2434                         DPFROMREG(ft, MIPSInst_FT(ir));
2435
2436                         /* positive predicates */
2437                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2438                                 if (ieee754dp_cmp(fs, ft,
2439                                                   cmptab[cmpop], sig))
2440                                     rv.l = -1LL; /* true, all 1s */
2441                                 if (sig &&
2442                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2443                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2444                                 else
2445                                         goto copcsr;
2446                         } else {
2447                                 /* negative predicates */
2448                                 switch (cmpop) {
2449                                 case 1:
2450                                 case 2:
2451                                 case 3:
2452                                         if (ieee754dp_cmp(fs, ft,
2453                                                           negative_cmptab[cmpop],
2454                                                           sig))
2455                                                 rv.l = -1LL; /* true, all 1s */
2456                                         if (sig &&
2457                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2458                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2459                                         else
2460                                                 goto copcsr;
2461                                         break;
2462                                 default:
2463                                         /* Reserved R6 ops */
2464                                         pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2465                                         return SIGILL;
2466                                 }
2467                         }
2468                         break;
2469                         }
2470                 }
2471         default:
2472                 return SIGILL;
2473         }
2474
2475         /*
2476          * Update the fpu CSR register for this operation.
2477          * If an exception is required, generate a tidy SIGFPE exception,
2478          * without updating the result register.
2479          * Note: cause exception bits do not accumulate, they are rewritten
2480          * for each op; only the flag/sticky bits accumulate.
2481          */
2482         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2483         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2484                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2485                 return SIGFPE;
2486         }
2487
2488         /*
2489          * Now we can safely write the result back to the register file.
2490          */
2491         switch (rfmt) {
2492         case -1:
2493
2494                 if (cpu_has_mips_4_5_r)
2495                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2496                 else
2497                         cbit = FPU_CSR_COND;
2498                 if (rv.w)
2499                         ctx->fcr31 |= cbit;
2500                 else
2501                         ctx->fcr31 &= ~cbit;
2502                 break;
2503
2504         case d_fmt:
2505                 DPTOREG(rv.d, MIPSInst_FD(ir));
2506                 break;
2507         case s_fmt:
2508                 SPTOREG(rv.s, MIPSInst_FD(ir));
2509                 break;
2510         case w_fmt:
2511                 SITOREG(rv.w, MIPSInst_FD(ir));
2512                 break;
2513         case l_fmt:
2514                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2515                         return SIGILL;
2516
2517                 DITOREG(rv.l, MIPSInst_FD(ir));
2518                 break;
2519         default:
2520                 return SIGILL;
2521         }
2522
2523         return 0;
2524 }
2525
2526 /*
2527  * Emulate FPU instructions.
2528  *
2529  * If we use FPU hardware, then we have been typically called to handle
2530  * an unimplemented operation, such as where an operand is a NaN or
2531  * denormalized.  In that case exit the emulation loop after a single
2532  * iteration so as to let hardware execute any subsequent instructions.
2533  *
2534  * If we have no FPU hardware or it has been disabled, then continue
2535  * emulating floating-point instructions until one of these conditions
2536  * has occurred:
2537  *
2538  * - a non-FPU instruction has been encountered,
2539  *
2540  * - an attempt to emulate has ended with a signal,
2541  *
2542  * - the ISA mode has been switched.
2543  *
2544  * We need to terminate the emulation loop if we got switched to the
2545  * MIPS16 mode, whether supported or not, so that we do not attempt
2546  * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2547  * Similarly if we got switched to the microMIPS mode and only the
2548  * regular MIPS mode is supported, so that we do not attempt to emulate
2549  * a microMIPS instruction as a regular MIPS FPU instruction.  Or if
2550  * we got switched to the regular MIPS mode and only the microMIPS mode
2551  * is supported, so that we do not attempt to emulate a regular MIPS
2552  * instruction that should cause an Address Error exception instead.
2553  * For simplicity we always terminate upon an ISA mode switch.
2554  */
2555 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2556         int has_fpu, void *__user *fault_addr)
2557 {
2558         unsigned long oldepc, prevepc;
2559         struct mm_decoded_insn dec_insn;
2560         u16 instr[4];
2561         u16 *instr_ptr;
2562         int sig = 0;
2563
2564         oldepc = xcp->cp0_epc;
2565         do {
2566                 prevepc = xcp->cp0_epc;
2567
2568                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2569                         /*
2570                          * Get next 2 microMIPS instructions and convert them
2571                          * into 32-bit instructions.
2572                          */
2573                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2574                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2575                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2576                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2577                                 MIPS_FPU_EMU_INC_STATS(errors);
2578                                 return SIGBUS;
2579                         }
2580                         instr_ptr = instr;
2581
2582                         /* Get first instruction. */
2583                         if (mm_insn_16bit(*instr_ptr)) {
2584                                 /* Duplicate the half-word. */
2585                                 dec_insn.insn = (*instr_ptr << 16) |
2586                                         (*instr_ptr);
2587                                 /* 16-bit instruction. */
2588                                 dec_insn.pc_inc = 2;
2589                                 instr_ptr += 1;
2590                         } else {
2591                                 dec_insn.insn = (*instr_ptr << 16) |
2592                                         *(instr_ptr+1);
2593                                 /* 32-bit instruction. */
2594                                 dec_insn.pc_inc = 4;
2595                                 instr_ptr += 2;
2596                         }
2597                         /* Get second instruction. */
2598                         if (mm_insn_16bit(*instr_ptr)) {
2599                                 /* Duplicate the half-word. */
2600                                 dec_insn.next_insn = (*instr_ptr << 16) |
2601                                         (*instr_ptr);
2602                                 /* 16-bit instruction. */
2603                                 dec_insn.next_pc_inc = 2;
2604                         } else {
2605                                 dec_insn.next_insn = (*instr_ptr << 16) |
2606                                         *(instr_ptr+1);
2607                                 /* 32-bit instruction. */
2608                                 dec_insn.next_pc_inc = 4;
2609                         }
2610                         dec_insn.micro_mips_mode = 1;
2611                 } else {
2612                         if ((get_user(dec_insn.insn,
2613                             (mips_instruction __user *) xcp->cp0_epc)) ||
2614                             (get_user(dec_insn.next_insn,
2615                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2616                                 MIPS_FPU_EMU_INC_STATS(errors);
2617                                 return SIGBUS;
2618                         }
2619                         dec_insn.pc_inc = 4;
2620                         dec_insn.next_pc_inc = 4;
2621                         dec_insn.micro_mips_mode = 0;
2622                 }
2623
2624                 if ((dec_insn.insn == 0) ||
2625                    ((dec_insn.pc_inc == 2) &&
2626                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2627                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2628                 else {
2629                         /*
2630                          * The 'ieee754_csr' is an alias of ctx->fcr31.
2631                          * No need to copy ctx->fcr31 to ieee754_csr.
2632                          */
2633                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2634                 }
2635
2636                 if (has_fpu)
2637                         break;
2638                 if (sig)
2639                         break;
2640                 /*
2641                  * We have to check for the ISA bit explicitly here,
2642                  * because `get_isa16_mode' may return 0 if support
2643                  * for code compression has been globally disabled,
2644                  * or otherwise we may produce the wrong signal or
2645                  * even proceed successfully where we must not.
2646                  */
2647                 if ((xcp->cp0_epc ^ prevepc) & 0x1)
2648                         break;
2649
2650                 cond_resched();
2651         } while (xcp->cp0_epc > prevepc);
2652
2653         /* SIGILL indicates a non-fpu instruction */
2654         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2655                 /* but if EPC has advanced, then ignore it */
2656                 sig = 0;
2657
2658         return sig;
2659 }