2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/percpu-defs.h>
39 #include <linux/perf_event.h>
41 #include <asm/branch.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/uaccess.h>
47 #include <asm/cpu-info.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
51 #include <asm/mips-r2-to-r6-emul.h>
55 /* Function which emulates a floating point instruction. */
57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
60 static int fpux_emu(struct pt_regs *,
61 struct mips_fpu_struct *, mips_instruction, void *__user *);
63 /* Control registers */
65 #define FPCREG_RID 0 /* $0 = revision id */
66 #define FPCREG_FCCR 25 /* $25 = fccr */
67 #define FPCREG_FEXR 26 /* $26 = fexr */
68 #define FPCREG_FENR 28 /* $28 = fenr */
69 #define FPCREG_CSR 31 /* $31 = csr */
71 /* convert condition code register number to csr bit */
72 const unsigned int fpucondbit[8] = {
83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
90 * This functions translates a 32-bit microMIPS instruction
91 * into a 32-bit MIPS32 instruction. Returns 0 on success
92 * and SIGILL otherwise.
94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 union mips_instruction insn = *insn_ptr;
97 union mips_instruction mips32_insn = insn;
100 switch (insn.mm_i_format.opcode) {
102 mips32_insn.mm_i_format.opcode = ldc1_op;
103 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
104 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
107 mips32_insn.mm_i_format.opcode = lwc1_op;
108 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
109 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
112 mips32_insn.mm_i_format.opcode = sdc1_op;
113 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
114 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
117 mips32_insn.mm_i_format.opcode = swc1_op;
118 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
119 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
122 /* NOTE: offset is << by 1 if in microMIPS mode. */
123 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
124 (insn.mm_i_format.rt == mm_bc1t_op)) {
125 mips32_insn.fb_format.opcode = cop1_op;
126 mips32_insn.fb_format.bc = bc_op;
127 mips32_insn.fb_format.flag =
128 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
133 switch (insn.mm_fp0_format.func) {
142 op = insn.mm_fp0_format.func;
143 if (op == mm_32f_01_op)
145 else if (op == mm_32f_11_op)
147 else if (op == mm_32f_02_op)
149 else if (op == mm_32f_12_op)
151 else if (op == mm_32f_41_op)
153 else if (op == mm_32f_51_op)
155 else if (op == mm_32f_42_op)
159 mips32_insn.fp6_format.opcode = cop1x_op;
160 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
161 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
162 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
163 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
164 mips32_insn.fp6_format.func = func;
167 func = -1; /* Invalid */
168 op = insn.mm_fp5_format.op & 0x7;
169 if (op == mm_ldxc1_op)
171 else if (op == mm_sdxc1_op)
173 else if (op == mm_lwxc1_op)
175 else if (op == mm_swxc1_op)
179 mips32_insn.r_format.opcode = cop1x_op;
180 mips32_insn.r_format.rs =
181 insn.mm_fp5_format.base;
182 mips32_insn.r_format.rt =
183 insn.mm_fp5_format.index;
184 mips32_insn.r_format.rd = 0;
185 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
186 mips32_insn.r_format.func = func;
191 op = -1; /* Invalid */
192 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 else if (insn.mm_fp2_format.op == mm_fmovf_op)
197 mips32_insn.fp0_format.opcode = cop1_op;
198 mips32_insn.fp0_format.fmt =
199 sdps_format[insn.mm_fp2_format.fmt];
200 mips32_insn.fp0_format.ft =
201 (insn.mm_fp2_format.cc<<2) + op;
202 mips32_insn.fp0_format.fs =
203 insn.mm_fp2_format.fs;
204 mips32_insn.fp0_format.fd =
205 insn.mm_fp2_format.fd;
206 mips32_insn.fp0_format.func = fmovc_op;
211 func = -1; /* Invalid */
212 if (insn.mm_fp0_format.op == mm_fadd_op)
214 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 else if (insn.mm_fp0_format.op == mm_fdiv_op)
221 mips32_insn.fp0_format.opcode = cop1_op;
222 mips32_insn.fp0_format.fmt =
223 sdps_format[insn.mm_fp0_format.fmt];
224 mips32_insn.fp0_format.ft =
225 insn.mm_fp0_format.ft;
226 mips32_insn.fp0_format.fs =
227 insn.mm_fp0_format.fs;
228 mips32_insn.fp0_format.fd =
229 insn.mm_fp0_format.fd;
230 mips32_insn.fp0_format.func = func;
235 func = -1; /* Invalid */
236 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 else if (insn.mm_fp0_format.op == mm_fmovz_op)
241 mips32_insn.fp0_format.opcode = cop1_op;
242 mips32_insn.fp0_format.fmt =
243 sdps_format[insn.mm_fp0_format.fmt];
244 mips32_insn.fp0_format.ft =
245 insn.mm_fp0_format.ft;
246 mips32_insn.fp0_format.fs =
247 insn.mm_fp0_format.fs;
248 mips32_insn.fp0_format.fd =
249 insn.mm_fp0_format.fd;
250 mips32_insn.fp0_format.func = func;
254 case mm_32f_73_op: /* POOL32FXF */
255 switch (insn.mm_fp1_format.op) {
260 if ((insn.mm_fp1_format.op & 0x7f) ==
265 mips32_insn.r_format.opcode = spec_op;
266 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
267 mips32_insn.r_format.rt =
268 (insn.mm_fp4_format.cc << 2) + op;
269 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
270 mips32_insn.r_format.re = 0;
271 mips32_insn.r_format.func = movc_op;
277 if ((insn.mm_fp1_format.op & 0x7f) ==
280 fmt = swl_format[insn.mm_fp3_format.fmt];
283 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 mips32_insn.fp0_format.opcode = cop1_op;
286 mips32_insn.fp0_format.fmt = fmt;
287 mips32_insn.fp0_format.ft = 0;
288 mips32_insn.fp0_format.fs =
289 insn.mm_fp3_format.fs;
290 mips32_insn.fp0_format.fd =
291 insn.mm_fp3_format.rt;
292 mips32_insn.fp0_format.func = func;
300 if ((insn.mm_fp1_format.op & 0x7f) ==
303 else if ((insn.mm_fp1_format.op & 0x7f) ==
308 mips32_insn.fp0_format.opcode = cop1_op;
309 mips32_insn.fp0_format.fmt =
310 sdps_format[insn.mm_fp3_format.fmt];
311 mips32_insn.fp0_format.ft = 0;
312 mips32_insn.fp0_format.fs =
313 insn.mm_fp3_format.fs;
314 mips32_insn.fp0_format.fd =
315 insn.mm_fp3_format.rt;
316 mips32_insn.fp0_format.func = func;
328 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
348 mips32_insn.fp0_format.opcode = cop1_op;
349 mips32_insn.fp0_format.fmt =
350 sd_format[insn.mm_fp1_format.fmt];
351 mips32_insn.fp0_format.ft = 0;
352 mips32_insn.fp0_format.fs =
353 insn.mm_fp1_format.fs;
354 mips32_insn.fp0_format.fd =
355 insn.mm_fp1_format.rt;
356 mips32_insn.fp0_format.func = func;
361 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
367 mips32_insn.fp0_format.opcode = cop1_op;
368 mips32_insn.fp0_format.fmt =
369 sdps_format[insn.mm_fp1_format.fmt];
370 mips32_insn.fp0_format.ft = 0;
371 mips32_insn.fp0_format.fs =
372 insn.mm_fp1_format.fs;
373 mips32_insn.fp0_format.fd =
374 insn.mm_fp1_format.rt;
375 mips32_insn.fp0_format.func = func;
383 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
395 mips32_insn.fp1_format.opcode = cop1_op;
396 mips32_insn.fp1_format.op = op;
397 mips32_insn.fp1_format.rt =
398 insn.mm_fp1_format.rt;
399 mips32_insn.fp1_format.fs =
400 insn.mm_fp1_format.fs;
401 mips32_insn.fp1_format.fd = 0;
402 mips32_insn.fp1_format.func = 0;
408 case mm_32f_74_op: /* c.cond.fmt */
409 mips32_insn.fp0_format.opcode = cop1_op;
410 mips32_insn.fp0_format.fmt =
411 sdps_format[insn.mm_fp4_format.fmt];
412 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
413 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
414 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
415 mips32_insn.fp0_format.func =
416 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
426 *insn_ptr = mips32_insn;
431 * Redundant with logic already in kernel/branch.c,
432 * embedded in compute_return_epc. At some point,
433 * a single subroutine should be used across both
436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
437 unsigned long *contpc)
439 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int bit = 0;
443 switch (insn.i_format.opcode) {
445 switch (insn.r_format.func) {
447 if (insn.r_format.rd != 0) {
448 regs->regs[insn.r_format.rd] =
449 regs->cp0_epc + dec_insn.pc_inc +
450 dec_insn.next_pc_inc;
454 /* For R6, JR already emulated in jalr_op */
455 if (NO_R6EMU && insn.r_format.func == jr_op)
457 *contpc = regs->regs[insn.r_format.rs];
462 switch (insn.i_format.rt) {
465 if (NO_R6EMU && (insn.i_format.rs ||
466 insn.i_format.rt == bltzall_op))
469 regs->regs[31] = regs->cp0_epc +
471 dec_insn.next_pc_inc;
477 if ((long)regs->regs[insn.i_format.rs] < 0)
478 *contpc = regs->cp0_epc +
480 (insn.i_format.simmediate << 2);
482 *contpc = regs->cp0_epc +
484 dec_insn.next_pc_inc;
488 if (NO_R6EMU && (insn.i_format.rs ||
489 insn.i_format.rt == bgezall_op))
492 regs->regs[31] = regs->cp0_epc +
494 dec_insn.next_pc_inc;
500 if ((long)regs->regs[insn.i_format.rs] >= 0)
501 *contpc = regs->cp0_epc +
503 (insn.i_format.simmediate << 2);
505 *contpc = regs->cp0_epc +
507 dec_insn.next_pc_inc;
514 regs->regs[31] = regs->cp0_epc +
516 dec_insn.next_pc_inc;
519 *contpc = regs->cp0_epc + dec_insn.pc_inc;
522 *contpc |= (insn.j_format.target << 2);
523 /* Set microMIPS mode bit: XOR for jalx. */
530 if (regs->regs[insn.i_format.rs] ==
531 regs->regs[insn.i_format.rt])
532 *contpc = regs->cp0_epc +
534 (insn.i_format.simmediate << 2);
536 *contpc = regs->cp0_epc +
538 dec_insn.next_pc_inc;
544 if (regs->regs[insn.i_format.rs] !=
545 regs->regs[insn.i_format.rt])
546 *contpc = regs->cp0_epc +
548 (insn.i_format.simmediate << 2);
550 *contpc = regs->cp0_epc +
552 dec_insn.next_pc_inc;
555 if (!insn.i_format.rt && NO_R6EMU)
560 * Compact branches for R6 for the
561 * blez and blezl opcodes.
562 * BLEZ | rs = 0 | rt != 0 == BLEZALC
563 * BLEZ | rs = rt != 0 == BGEZALC
564 * BLEZ | rs != 0 | rt != 0 == BGEUC
565 * BLEZL | rs = 0 | rt != 0 == BLEZC
566 * BLEZL | rs = rt != 0 == BGEZC
567 * BLEZL | rs != 0 | rt != 0 == BGEC
569 * For real BLEZ{,L}, rt is always 0.
571 if (cpu_has_mips_r6 && insn.i_format.rt) {
572 if ((insn.i_format.opcode == blez_op) &&
573 ((!insn.i_format.rs && insn.i_format.rt) ||
574 (insn.i_format.rs == insn.i_format.rt)))
575 regs->regs[31] = regs->cp0_epc +
577 *contpc = regs->cp0_epc + dec_insn.pc_inc +
578 dec_insn.next_pc_inc;
582 if ((long)regs->regs[insn.i_format.rs] <= 0)
583 *contpc = regs->cp0_epc +
585 (insn.i_format.simmediate << 2);
587 *contpc = regs->cp0_epc +
589 dec_insn.next_pc_inc;
592 if (!insn.i_format.rt && NO_R6EMU)
596 * Compact branches for R6 for the
597 * bgtz and bgtzl opcodes.
598 * BGTZ | rs = 0 | rt != 0 == BGTZALC
599 * BGTZ | rs = rt != 0 == BLTZALC
600 * BGTZ | rs != 0 | rt != 0 == BLTUC
601 * BGTZL | rs = 0 | rt != 0 == BGTZC
602 * BGTZL | rs = rt != 0 == BLTZC
603 * BGTZL | rs != 0 | rt != 0 == BLTC
605 * *ZALC varint for BGTZ &&& rt != 0
606 * For real GTZ{,L}, rt is always 0.
608 if (cpu_has_mips_r6 && insn.i_format.rt) {
609 if ((insn.i_format.opcode == blez_op) &&
610 ((!insn.i_format.rs && insn.i_format.rt) ||
611 (insn.i_format.rs == insn.i_format.rt)))
612 regs->regs[31] = regs->cp0_epc +
614 *contpc = regs->cp0_epc + dec_insn.pc_inc +
615 dec_insn.next_pc_inc;
620 if ((long)regs->regs[insn.i_format.rs] > 0)
621 *contpc = regs->cp0_epc +
623 (insn.i_format.simmediate << 2);
625 *contpc = regs->cp0_epc +
627 dec_insn.next_pc_inc;
631 if (!cpu_has_mips_r6)
633 if (insn.i_format.rt && !insn.i_format.rs)
634 regs->regs[31] = regs->cp0_epc + 4;
635 *contpc = regs->cp0_epc + dec_insn.pc_inc +
636 dec_insn.next_pc_inc;
639 #ifdef CONFIG_CPU_CAVIUM_OCTEON
640 case lwc2_op: /* This is bbit0 on Octeon */
641 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
642 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
644 *contpc = regs->cp0_epc + 8;
646 case ldc2_op: /* This is bbit032 on Octeon */
647 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
648 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
650 *contpc = regs->cp0_epc + 8;
652 case swc2_op: /* This is bbit1 on Octeon */
653 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
654 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
656 *contpc = regs->cp0_epc + 8;
658 case sdc2_op: /* This is bbit132 on Octeon */
659 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
660 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
662 *contpc = regs->cp0_epc + 8;
667 * Only valid for MIPS R6 but we can still end up
668 * here from a broken userland so just tell emulator
669 * this is not a branch and let it break later on.
671 if (!cpu_has_mips_r6)
673 *contpc = regs->cp0_epc + dec_insn.pc_inc +
674 dec_insn.next_pc_inc;
678 if (!cpu_has_mips_r6)
680 regs->regs[31] = regs->cp0_epc + 4;
681 *contpc = regs->cp0_epc + dec_insn.pc_inc +
682 dec_insn.next_pc_inc;
686 if (!cpu_has_mips_r6)
688 *contpc = regs->cp0_epc + dec_insn.pc_inc +
689 dec_insn.next_pc_inc;
693 if (!cpu_has_mips_r6)
695 if (!insn.i_format.rs)
696 regs->regs[31] = regs->cp0_epc + 4;
697 *contpc = regs->cp0_epc + dec_insn.pc_inc +
698 dec_insn.next_pc_inc;
704 /* Need to check for R6 bc1nez and bc1eqz branches */
705 if (cpu_has_mips_r6 &&
706 ((insn.i_format.rs == bc1eqz_op) ||
707 (insn.i_format.rs == bc1nez_op))) {
709 switch (insn.i_format.rs) {
711 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
715 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
720 *contpc = regs->cp0_epc +
722 (insn.i_format.simmediate << 2);
724 *contpc = regs->cp0_epc +
726 dec_insn.next_pc_inc;
730 /* R2/R6 compatible cop1 instruction. Fall through */
733 if (insn.i_format.rs == bc_op) {
736 fcr31 = read_32bit_cp1_register(CP1_STATUS);
738 fcr31 = current->thread.fpu.fcr31;
741 bit = (insn.i_format.rt >> 2);
744 switch (insn.i_format.rt & 3) {
747 if (~fcr31 & (1 << bit))
748 *contpc = regs->cp0_epc +
750 (insn.i_format.simmediate << 2);
752 *contpc = regs->cp0_epc +
754 dec_insn.next_pc_inc;
758 if (fcr31 & (1 << bit))
759 *contpc = regs->cp0_epc +
761 (insn.i_format.simmediate << 2);
763 *contpc = regs->cp0_epc +
765 dec_insn.next_pc_inc;
775 * In the Linux kernel, we support selection of FPR format on the
776 * basis of the Status.FR bit. If an FPU is not present, the FR bit
777 * is hardwired to zero, which would imply a 32-bit FPU even for
778 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
779 * FPU emu is slow and bulky and optimizing this function offers fairly
780 * sizeable benefits so we try to be clever and make this function return
781 * a constant whenever possible, that is on 64-bit kernels without O32
782 * compatibility enabled and on 32-bit without 64-bit FPU support.
784 static inline int cop1_64bit(struct pt_regs *xcp)
786 if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
788 else if (IS_ENABLED(CONFIG_32BIT) &&
789 !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
792 return !test_thread_flag(TIF_32BIT_FPREGS);
795 static inline bool hybrid_fprs(void)
797 return test_thread_flag(TIF_HYBRID_FPREGS);
800 #define SIFROMREG(si, x) \
802 if (cop1_64bit(xcp) && !hybrid_fprs()) \
803 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
805 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
808 #define SITOREG(si, x) \
810 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
812 set_fpr32(&ctx->fpr[x], 0, si); \
813 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
814 set_fpr32(&ctx->fpr[x], i, 0); \
816 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
820 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
822 #define SITOHREG(si, x) \
825 set_fpr32(&ctx->fpr[x], 1, si); \
826 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
827 set_fpr32(&ctx->fpr[x], i, 0); \
830 #define DIFROMREG(di, x) \
831 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
833 #define DITOREG(di, x) \
836 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
837 set_fpr64(&ctx->fpr[fpr], 0, di); \
838 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
839 set_fpr64(&ctx->fpr[fpr], i, 0); \
842 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
843 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
844 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
845 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
848 * Emulate a CFC1 instruction.
850 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
853 u32 fcr31 = ctx->fcr31;
856 switch (MIPSInst_RD(ir)) {
859 pr_debug("%p gpr[%d]<-csr=%08x\n",
860 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
866 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
868 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
869 pr_debug("%p gpr[%d]<-enr=%08x\n",
870 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
876 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
877 pr_debug("%p gpr[%d]<-exr=%08x\n",
878 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
884 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
886 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
887 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
888 pr_debug("%p gpr[%d]<-ccr=%08x\n",
889 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
893 value = boot_cpu_data.fpu_id;
901 xcp->regs[MIPSInst_RT(ir)] = value;
905 * Emulate a CTC1 instruction.
907 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
910 u32 fcr31 = ctx->fcr31;
914 if (MIPSInst_RT(ir) == 0)
917 value = xcp->regs[MIPSInst_RT(ir)];
919 switch (MIPSInst_RD(ir)) {
921 pr_debug("%p gpr[%d]->csr=%08x\n",
922 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
924 /* Preserve read-only bits. */
925 mask = boot_cpu_data.fpu_msk31;
926 fcr31 = (value & ~mask) | (fcr31 & mask);
932 pr_debug("%p gpr[%d]->enr=%08x\n",
933 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
934 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
935 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
937 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
943 pr_debug("%p gpr[%d]->exr=%08x\n",
944 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
945 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
946 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
952 pr_debug("%p gpr[%d]->ccr=%08x\n",
953 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
954 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
955 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
957 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
969 * Emulate the single floating point instruction pointed at by EPC.
970 * Two instructions if the instruction is in a branch delay slot.
973 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
974 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
976 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
977 unsigned int cond, cbit, bit0;
988 * These are giving gcc a gentle hint about what to expect in
989 * dec_inst in order to do better optimization.
991 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
994 /* XXX NEC Vr54xx bug workaround */
995 if (delay_slot(xcp)) {
996 if (dec_insn.micro_mips_mode) {
997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
998 clear_delay_slot(xcp);
1000 if (!isBranchInstr(xcp, dec_insn, &contpc))
1001 clear_delay_slot(xcp);
1005 if (delay_slot(xcp)) {
1007 * The instruction to be emulated is in a branch delay slot
1008 * which means that we have to emulate the branch instruction
1009 * BEFORE we do the cop1 instruction.
1011 * This branch could be a COP1 branch, but in that case we
1012 * would have had a trap for that instruction, and would not
1013 * come through this route.
1015 * Linux MIPS branch emulator operates on context, updating the
1018 ir = dec_insn.next_insn; /* process delay slot instr */
1019 pc_inc = dec_insn.next_pc_inc;
1021 ir = dec_insn.insn; /* process current instr */
1022 pc_inc = dec_insn.pc_inc;
1026 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1027 * instructions, we want to convert microMIPS FPU instructions
1028 * into MIPS32 instructions so that we could reuse all of the
1029 * FPU emulation code.
1031 * NOTE: We cannot do this for branch instructions since they
1032 * are not a subset. Example: Cannot emulate a 16-bit
1033 * aligned target address with a MIPS32 instruction.
1035 if (dec_insn.micro_mips_mode) {
1037 * If next instruction is a 16-bit instruction, then it
1038 * it cannot be a FPU instruction. This could happen
1039 * since we can be called for non-FPU instructions.
1041 if ((pc_inc == 2) ||
1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1048 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1049 MIPS_FPU_EMU_INC_STATS(emulated);
1050 switch (MIPSInst_OPCODE(ir)) {
1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1054 MIPS_FPU_EMU_INC_STATS(loads);
1056 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1057 MIPS_FPU_EMU_INC_STATS(errors);
1061 if (__get_user(dval, dva)) {
1062 MIPS_FPU_EMU_INC_STATS(errors);
1066 DITOREG(dval, MIPSInst_RT(ir));
1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1072 MIPS_FPU_EMU_INC_STATS(stores);
1073 DIFROMREG(dval, MIPSInst_RT(ir));
1074 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1075 MIPS_FPU_EMU_INC_STATS(errors);
1079 if (__put_user(dval, dva)) {
1080 MIPS_FPU_EMU_INC_STATS(errors);
1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1089 MIPS_FPU_EMU_INC_STATS(loads);
1090 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1091 MIPS_FPU_EMU_INC_STATS(errors);
1095 if (__get_user(wval, wva)) {
1096 MIPS_FPU_EMU_INC_STATS(errors);
1100 SITOREG(wval, MIPSInst_RT(ir));
1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1106 MIPS_FPU_EMU_INC_STATS(stores);
1107 SIFROMREG(wval, MIPSInst_RT(ir));
1108 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1109 MIPS_FPU_EMU_INC_STATS(errors);
1113 if (__put_user(wval, wva)) {
1114 MIPS_FPU_EMU_INC_STATS(errors);
1121 switch (MIPSInst_RS(ir)) {
1123 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1126 /* copregister fs -> gpr[rt] */
1127 if (MIPSInst_RT(ir) != 0) {
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1134 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1137 /* copregister fs <- rt */
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1142 if (!cpu_has_mips_r2_r6)
1145 /* copregister rd -> gpr[rt] */
1146 if (MIPSInst_RT(ir) != 0) {
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1153 if (!cpu_has_mips_r2_r6)
1156 /* copregister rd <- gpr[rt] */
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1161 /* copregister rd -> gpr[rt] */
1162 if (MIPSInst_RT(ir) != 0) {
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1169 /* copregister rd <- rt */
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1174 /* cop control register rd -> gpr[rt] */
1175 cop1_cfc(xcp, ctx, ir);
1179 /* copregister rd <- rt */
1180 cop1_ctc(xcp, ctx, ir);
1181 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1188 if (!cpu_has_mips_r6 || delay_slot(xcp))
1192 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1193 bit0 = get_fpr32(fpr, 0) & 0x1;
1194 switch (MIPSInst_RS(ir)) {
1205 if (delay_slot(xcp))
1208 if (cpu_has_mips_4_5_r)
1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1211 cbit = FPU_CSR_COND;
1212 cond = ctx->fcr31 & cbit;
1215 switch (MIPSInst_RT(ir) & 3) {
1217 if (cpu_has_mips_2_3_4_5_r)
1224 if (cpu_has_mips_2_3_4_5_r)
1231 set_delay_slot(xcp);
1234 * Branch taken: emulate dslot instruction
1239 * Remember EPC at the branch to point back
1240 * at so that any delay-slot instruction
1241 * signal is not silently ignored.
1243 bcpc = xcp->cp0_epc;
1244 xcp->cp0_epc += dec_insn.pc_inc;
1246 contpc = MIPSInst_SIMM(ir);
1247 ir = dec_insn.next_insn;
1248 if (dec_insn.micro_mips_mode) {
1249 contpc = (xcp->cp0_epc + (contpc << 1));
1251 /* If 16-bit instruction, not FPU. */
1252 if ((dec_insn.next_pc_inc == 2) ||
1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1256 * Since this instruction will
1257 * be put on the stack with
1258 * 32-bit words, get around
1259 * this problem by putting a
1260 * NOP16 as the second one.
1262 if (dec_insn.next_pc_inc == 2)
1263 ir = (ir & (~0xffff)) | MM_NOP16;
1266 * Single step the non-CP1
1267 * instruction in the dslot.
1269 sig = mips_dsemul(xcp, ir,
1274 xcp->cp0_epc = bcpc;
1276 * SIGILL forces out of
1277 * the emulation loop.
1279 return sig ? sig : SIGILL;
1282 contpc = (xcp->cp0_epc + (contpc << 2));
1284 switch (MIPSInst_OPCODE(ir)) {
1291 if (cpu_has_mips_2_3_4_5_r)
1300 if (cpu_has_mips_4_5_64_r2_r6)
1301 /* its one of ours */
1307 switch (MIPSInst_FUNC(ir)) {
1309 if (cpu_has_mips_4_5_r)
1317 xcp->cp0_epc = bcpc;
1322 * Single step the non-cp1
1323 * instruction in the dslot
1325 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1329 xcp->cp0_epc = bcpc;
1330 /* SIGILL forces out of the emulation loop. */
1331 return sig ? sig : SIGILL;
1332 } else if (likely) { /* branch not taken */
1334 * branch likely nullifies
1335 * dslot if not taken
1337 xcp->cp0_epc += dec_insn.pc_inc;
1338 contpc += dec_insn.pc_inc;
1340 * else continue & execute
1341 * dslot as normal insn
1347 if (!(MIPSInst_RS(ir) & 0x10))
1350 /* a real fpu computation instruction */
1351 if ((sig = fpu_emu(xcp, ctx, ir)))
1357 if (!cpu_has_mips_4_5_64_r2_r6)
1360 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1366 if (!cpu_has_mips_4_5_r)
1369 if (MIPSInst_FUNC(ir) != movc_op)
1371 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1372 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1373 xcp->regs[MIPSInst_RD(ir)] =
1374 xcp->regs[MIPSInst_RS(ir)];
1382 xcp->cp0_epc = contpc;
1383 clear_delay_slot(xcp);
1389 * Conversion table from MIPS compare ops 48-63
1390 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1392 static const unsigned char cmptab[8] = {
1393 0, /* cmp_0 (sig) cmp_sf */
1394 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1395 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1396 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1397 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1398 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1399 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1400 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1403 static const unsigned char negative_cmptab[8] = {
1405 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1406 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1407 IEEE754_CLT | IEEE754_CGT,
1413 * Additional MIPS4 instructions
1416 #define DEF3OP(name, p, f1, f2, f3) \
1417 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1418 union ieee754##p s, union ieee754##p t) \
1420 struct _ieee754_csr ieee754_csr_save; \
1422 ieee754_csr_save = ieee754_csr; \
1424 ieee754_csr_save.cx |= ieee754_csr.cx; \
1425 ieee754_csr_save.sx |= ieee754_csr.sx; \
1427 ieee754_csr.cx |= ieee754_csr_save.cx; \
1428 ieee754_csr.sx |= ieee754_csr_save.sx; \
1432 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1434 return ieee754dp_div(ieee754dp_one(0), d);
1437 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1439 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1442 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1444 return ieee754sp_div(ieee754sp_one(0), s);
1447 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1449 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1452 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1453 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1454 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1455 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1456 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1457 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1458 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1459 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1461 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1462 mips_instruction ir, void *__user *fault_addr)
1464 unsigned rcsr = 0; /* resulting csr */
1466 MIPS_FPU_EMU_INC_STATS(cp1xops);
1468 switch (MIPSInst_FMA_FFMT(ir)) {
1469 case s_fmt:{ /* 0 */
1471 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1472 union ieee754sp fd, fr, fs, ft;
1476 switch (MIPSInst_FUNC(ir)) {
1478 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1479 xcp->regs[MIPSInst_FT(ir)]);
1481 MIPS_FPU_EMU_INC_STATS(loads);
1482 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1483 MIPS_FPU_EMU_INC_STATS(errors);
1487 if (__get_user(val, va)) {
1488 MIPS_FPU_EMU_INC_STATS(errors);
1492 SITOREG(val, MIPSInst_FD(ir));
1496 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1497 xcp->regs[MIPSInst_FT(ir)]);
1499 MIPS_FPU_EMU_INC_STATS(stores);
1501 SIFROMREG(val, MIPSInst_FS(ir));
1502 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1503 MIPS_FPU_EMU_INC_STATS(errors);
1507 if (put_user(val, va)) {
1508 MIPS_FPU_EMU_INC_STATS(errors);
1515 handler = fpemu_sp_madd;
1518 handler = fpemu_sp_msub;
1521 handler = fpemu_sp_nmadd;
1524 handler = fpemu_sp_nmsub;
1528 SPFROMREG(fr, MIPSInst_FR(ir));
1529 SPFROMREG(fs, MIPSInst_FS(ir));
1530 SPFROMREG(ft, MIPSInst_FT(ir));
1531 fd = (*handler) (fr, fs, ft);
1532 SPTOREG(fd, MIPSInst_FD(ir));
1535 if (ieee754_cxtest(IEEE754_INEXACT)) {
1536 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1537 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1539 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1540 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1541 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1543 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1544 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1545 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1547 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1548 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1549 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1552 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1553 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1554 /*printk ("SIGFPE: FPU csr = %08x\n",
1567 case d_fmt:{ /* 1 */
1568 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1569 union ieee754dp fd, fr, fs, ft;
1573 switch (MIPSInst_FUNC(ir)) {
1575 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1576 xcp->regs[MIPSInst_FT(ir)]);
1578 MIPS_FPU_EMU_INC_STATS(loads);
1579 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1580 MIPS_FPU_EMU_INC_STATS(errors);
1584 if (__get_user(val, va)) {
1585 MIPS_FPU_EMU_INC_STATS(errors);
1589 DITOREG(val, MIPSInst_FD(ir));
1593 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1594 xcp->regs[MIPSInst_FT(ir)]);
1596 MIPS_FPU_EMU_INC_STATS(stores);
1597 DIFROMREG(val, MIPSInst_FS(ir));
1598 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1599 MIPS_FPU_EMU_INC_STATS(errors);
1603 if (__put_user(val, va)) {
1604 MIPS_FPU_EMU_INC_STATS(errors);
1611 handler = fpemu_dp_madd;
1614 handler = fpemu_dp_msub;
1617 handler = fpemu_dp_nmadd;
1620 handler = fpemu_dp_nmsub;
1624 DPFROMREG(fr, MIPSInst_FR(ir));
1625 DPFROMREG(fs, MIPSInst_FS(ir));
1626 DPFROMREG(ft, MIPSInst_FT(ir));
1627 fd = (*handler) (fr, fs, ft);
1628 DPTOREG(fd, MIPSInst_FD(ir));
1638 if (MIPSInst_FUNC(ir) != pfetch_op)
1641 /* ignore prefx operation */
1654 * Emulate a single COP1 arithmetic instruction.
1656 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1657 mips_instruction ir)
1659 int rfmt; /* resulting format */
1660 unsigned rcsr = 0; /* resulting csr */
1669 } rv; /* resulting value */
1672 MIPS_FPU_EMU_INC_STATS(cp1ops);
1673 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1674 case s_fmt: { /* 0 */
1676 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1677 union ieee754sp(*u) (union ieee754sp);
1679 union ieee754sp fd, fs, ft;
1681 switch (MIPSInst_FUNC(ir)) {
1684 handler.b = ieee754sp_add;
1687 handler.b = ieee754sp_sub;
1690 handler.b = ieee754sp_mul;
1693 handler.b = ieee754sp_div;
1698 if (!cpu_has_mips_2_3_4_5_r)
1701 handler.u = ieee754sp_sqrt;
1705 * Note that on some MIPS IV implementations such as the
1706 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1707 * achieve full IEEE-754 accuracy - however this emulator does.
1710 if (!cpu_has_mips_4_5_64_r2_r6)
1713 handler.u = fpemu_sp_rsqrt;
1717 if (!cpu_has_mips_4_5_64_r2_r6)
1720 handler.u = fpemu_sp_recip;
1724 if (!cpu_has_mips_4_5_r)
1727 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1728 if (((ctx->fcr31 & cond) != 0) !=
1729 ((MIPSInst_FT(ir) & 1) != 0))
1731 SPFROMREG(rv.s, MIPSInst_FS(ir));
1735 if (!cpu_has_mips_4_5_r)
1738 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1740 SPFROMREG(rv.s, MIPSInst_FS(ir));
1744 if (!cpu_has_mips_4_5_r)
1747 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1749 SPFROMREG(rv.s, MIPSInst_FS(ir));
1753 if (!cpu_has_mips_r6)
1756 SPFROMREG(rv.s, MIPSInst_FT(ir));
1760 SPFROMREG(rv.s, MIPSInst_FS(ir));
1764 if (!cpu_has_mips_r6)
1767 SPFROMREG(rv.s, MIPSInst_FT(ir));
1769 SPFROMREG(rv.s, MIPSInst_FS(ir));
1775 union ieee754sp ft, fs, fd;
1777 if (!cpu_has_mips_r6)
1780 SPFROMREG(ft, MIPSInst_FT(ir));
1781 SPFROMREG(fs, MIPSInst_FS(ir));
1782 SPFROMREG(fd, MIPSInst_FD(ir));
1783 rv.s = ieee754sp_maddf(fd, fs, ft);
1788 union ieee754sp ft, fs, fd;
1790 if (!cpu_has_mips_r6)
1793 SPFROMREG(ft, MIPSInst_FT(ir));
1794 SPFROMREG(fs, MIPSInst_FS(ir));
1795 SPFROMREG(fd, MIPSInst_FD(ir));
1796 rv.s = ieee754sp_msubf(fd, fs, ft);
1803 if (!cpu_has_mips_r6)
1806 SPFROMREG(fs, MIPSInst_FS(ir));
1807 rv.l = ieee754sp_tlong(fs);
1808 rv.s = ieee754sp_flong(rv.l);
1815 if (!cpu_has_mips_r6)
1818 SPFROMREG(fs, MIPSInst_FS(ir));
1819 rv.w = ieee754sp_2008class(fs);
1825 union ieee754sp fs, ft;
1827 if (!cpu_has_mips_r6)
1830 SPFROMREG(ft, MIPSInst_FT(ir));
1831 SPFROMREG(fs, MIPSInst_FS(ir));
1832 rv.s = ieee754sp_fmin(fs, ft);
1837 union ieee754sp fs, ft;
1839 if (!cpu_has_mips_r6)
1842 SPFROMREG(ft, MIPSInst_FT(ir));
1843 SPFROMREG(fs, MIPSInst_FS(ir));
1844 rv.s = ieee754sp_fmina(fs, ft);
1849 union ieee754sp fs, ft;
1851 if (!cpu_has_mips_r6)
1854 SPFROMREG(ft, MIPSInst_FT(ir));
1855 SPFROMREG(fs, MIPSInst_FS(ir));
1856 rv.s = ieee754sp_fmax(fs, ft);
1861 union ieee754sp fs, ft;
1863 if (!cpu_has_mips_r6)
1866 SPFROMREG(ft, MIPSInst_FT(ir));
1867 SPFROMREG(fs, MIPSInst_FS(ir));
1868 rv.s = ieee754sp_fmaxa(fs, ft);
1873 handler.u = ieee754sp_abs;
1877 handler.u = ieee754sp_neg;
1882 SPFROMREG(rv.s, MIPSInst_FS(ir));
1885 /* binary op on handler */
1887 SPFROMREG(fs, MIPSInst_FS(ir));
1888 SPFROMREG(ft, MIPSInst_FT(ir));
1890 rv.s = (*handler.b) (fs, ft);
1893 SPFROMREG(fs, MIPSInst_FS(ir));
1894 rv.s = (*handler.u) (fs);
1897 if (ieee754_cxtest(IEEE754_INEXACT)) {
1898 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1899 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1901 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1902 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1903 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1905 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1906 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1907 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1909 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1910 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1911 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1913 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1914 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1915 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1919 /* unary conv ops */
1921 return SIGILL; /* not defined */
1924 SPFROMREG(fs, MIPSInst_FS(ir));
1925 rv.d = ieee754dp_fsp(fs);
1930 SPFROMREG(fs, MIPSInst_FS(ir));
1931 rv.w = ieee754sp_tint(fs);
1939 if (!cpu_has_mips_2_3_4_5_r)
1942 oldrm = ieee754_csr.rm;
1943 SPFROMREG(fs, MIPSInst_FS(ir));
1944 ieee754_csr.rm = MIPSInst_FUNC(ir);
1945 rv.w = ieee754sp_tint(fs);
1946 ieee754_csr.rm = oldrm;
1951 if (!cpu_has_mips_r6)
1954 SPFROMREG(fd, MIPSInst_FD(ir));
1956 SPFROMREG(rv.s, MIPSInst_FT(ir));
1958 SPFROMREG(rv.s, MIPSInst_FS(ir));
1962 if (!cpu_has_mips_3_4_5_64_r2_r6)
1965 SPFROMREG(fs, MIPSInst_FS(ir));
1966 rv.l = ieee754sp_tlong(fs);
1974 if (!cpu_has_mips_3_4_5_64_r2_r6)
1977 oldrm = ieee754_csr.rm;
1978 SPFROMREG(fs, MIPSInst_FS(ir));
1979 ieee754_csr.rm = MIPSInst_FUNC(ir);
1980 rv.l = ieee754sp_tlong(fs);
1981 ieee754_csr.rm = oldrm;
1986 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1987 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1988 union ieee754sp fs, ft;
1990 SPFROMREG(fs, MIPSInst_FS(ir));
1991 SPFROMREG(ft, MIPSInst_FT(ir));
1992 rv.w = ieee754sp_cmp(fs, ft,
1993 cmptab[cmpop & 0x7], cmpop & 0x8);
1995 if ((cmpop & 0x8) && ieee754_cxtest
1996 (IEEE754_INVALID_OPERATION))
1997 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2009 union ieee754dp fd, fs, ft;
2011 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2012 union ieee754dp(*u) (union ieee754dp);
2015 switch (MIPSInst_FUNC(ir)) {
2018 handler.b = ieee754dp_add;
2021 handler.b = ieee754dp_sub;
2024 handler.b = ieee754dp_mul;
2027 handler.b = ieee754dp_div;
2032 if (!cpu_has_mips_2_3_4_5_r)
2035 handler.u = ieee754dp_sqrt;
2038 * Note that on some MIPS IV implementations such as the
2039 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2040 * achieve full IEEE-754 accuracy - however this emulator does.
2043 if (!cpu_has_mips_4_5_64_r2_r6)
2046 handler.u = fpemu_dp_rsqrt;
2049 if (!cpu_has_mips_4_5_64_r2_r6)
2052 handler.u = fpemu_dp_recip;
2055 if (!cpu_has_mips_4_5_r)
2058 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2059 if (((ctx->fcr31 & cond) != 0) !=
2060 ((MIPSInst_FT(ir) & 1) != 0))
2062 DPFROMREG(rv.d, MIPSInst_FS(ir));
2065 if (!cpu_has_mips_4_5_r)
2068 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2070 DPFROMREG(rv.d, MIPSInst_FS(ir));
2073 if (!cpu_has_mips_4_5_r)
2076 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2078 DPFROMREG(rv.d, MIPSInst_FS(ir));
2082 if (!cpu_has_mips_r6)
2085 DPFROMREG(rv.d, MIPSInst_FT(ir));
2089 DPFROMREG(rv.d, MIPSInst_FS(ir));
2093 if (!cpu_has_mips_r6)
2096 DPFROMREG(rv.d, MIPSInst_FT(ir));
2098 DPFROMREG(rv.d, MIPSInst_FS(ir));
2104 union ieee754dp ft, fs, fd;
2106 if (!cpu_has_mips_r6)
2109 DPFROMREG(ft, MIPSInst_FT(ir));
2110 DPFROMREG(fs, MIPSInst_FS(ir));
2111 DPFROMREG(fd, MIPSInst_FD(ir));
2112 rv.d = ieee754dp_maddf(fd, fs, ft);
2117 union ieee754dp ft, fs, fd;
2119 if (!cpu_has_mips_r6)
2122 DPFROMREG(ft, MIPSInst_FT(ir));
2123 DPFROMREG(fs, MIPSInst_FS(ir));
2124 DPFROMREG(fd, MIPSInst_FD(ir));
2125 rv.d = ieee754dp_msubf(fd, fs, ft);
2132 if (!cpu_has_mips_r6)
2135 DPFROMREG(fs, MIPSInst_FS(ir));
2136 rv.l = ieee754dp_tlong(fs);
2137 rv.d = ieee754dp_flong(rv.l);
2144 if (!cpu_has_mips_r6)
2147 DPFROMREG(fs, MIPSInst_FS(ir));
2148 rv.w = ieee754dp_2008class(fs);
2154 union ieee754dp fs, ft;
2156 if (!cpu_has_mips_r6)
2159 DPFROMREG(ft, MIPSInst_FT(ir));
2160 DPFROMREG(fs, MIPSInst_FS(ir));
2161 rv.d = ieee754dp_fmin(fs, ft);
2166 union ieee754dp fs, ft;
2168 if (!cpu_has_mips_r6)
2171 DPFROMREG(ft, MIPSInst_FT(ir));
2172 DPFROMREG(fs, MIPSInst_FS(ir));
2173 rv.d = ieee754dp_fmina(fs, ft);
2178 union ieee754dp fs, ft;
2180 if (!cpu_has_mips_r6)
2183 DPFROMREG(ft, MIPSInst_FT(ir));
2184 DPFROMREG(fs, MIPSInst_FS(ir));
2185 rv.d = ieee754dp_fmax(fs, ft);
2190 union ieee754dp fs, ft;
2192 if (!cpu_has_mips_r6)
2195 DPFROMREG(ft, MIPSInst_FT(ir));
2196 DPFROMREG(fs, MIPSInst_FS(ir));
2197 rv.d = ieee754dp_fmaxa(fs, ft);
2202 handler.u = ieee754dp_abs;
2206 handler.u = ieee754dp_neg;
2211 DPFROMREG(rv.d, MIPSInst_FS(ir));
2214 /* binary op on handler */
2216 DPFROMREG(fs, MIPSInst_FS(ir));
2217 DPFROMREG(ft, MIPSInst_FT(ir));
2219 rv.d = (*handler.b) (fs, ft);
2222 DPFROMREG(fs, MIPSInst_FS(ir));
2223 rv.d = (*handler.u) (fs);
2230 DPFROMREG(fs, MIPSInst_FS(ir));
2231 rv.s = ieee754sp_fdp(fs);
2236 return SIGILL; /* not defined */
2239 DPFROMREG(fs, MIPSInst_FS(ir));
2240 rv.w = ieee754dp_tint(fs); /* wrong */
2248 if (!cpu_has_mips_2_3_4_5_r)
2251 oldrm = ieee754_csr.rm;
2252 DPFROMREG(fs, MIPSInst_FS(ir));
2253 ieee754_csr.rm = MIPSInst_FUNC(ir);
2254 rv.w = ieee754dp_tint(fs);
2255 ieee754_csr.rm = oldrm;
2260 if (!cpu_has_mips_r6)
2263 DPFROMREG(fd, MIPSInst_FD(ir));
2265 DPFROMREG(rv.d, MIPSInst_FT(ir));
2267 DPFROMREG(rv.d, MIPSInst_FS(ir));
2271 if (!cpu_has_mips_3_4_5_64_r2_r6)
2274 DPFROMREG(fs, MIPSInst_FS(ir));
2275 rv.l = ieee754dp_tlong(fs);
2283 if (!cpu_has_mips_3_4_5_64_r2_r6)
2286 oldrm = ieee754_csr.rm;
2287 DPFROMREG(fs, MIPSInst_FS(ir));
2288 ieee754_csr.rm = MIPSInst_FUNC(ir);
2289 rv.l = ieee754dp_tlong(fs);
2290 ieee754_csr.rm = oldrm;
2295 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2296 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2297 union ieee754dp fs, ft;
2299 DPFROMREG(fs, MIPSInst_FS(ir));
2300 DPFROMREG(ft, MIPSInst_FT(ir));
2301 rv.w = ieee754dp_cmp(fs, ft,
2302 cmptab[cmpop & 0x7], cmpop & 0x8);
2307 (IEEE754_INVALID_OPERATION))
2308 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2324 switch (MIPSInst_FUNC(ir)) {
2326 /* convert word to single precision real */
2327 SPFROMREG(fs, MIPSInst_FS(ir));
2328 rv.s = ieee754sp_fint(fs.bits);
2332 /* convert word to double precision real */
2333 SPFROMREG(fs, MIPSInst_FS(ir));
2334 rv.d = ieee754dp_fint(fs.bits);
2338 /* Emulating the new CMP.condn.fmt R6 instruction */
2339 #define CMPOP_MASK 0x7
2340 #define SIGN_BIT (0x1 << 3)
2341 #define PREDICATE_BIT (0x1 << 4)
2343 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2344 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2345 union ieee754sp fs, ft;
2347 /* This is an R6 only instruction */
2348 if (!cpu_has_mips_r6 ||
2349 (MIPSInst_FUNC(ir) & 0x20))
2352 /* fmt is w_fmt for single precision so fix it */
2354 /* default to false */
2358 SPFROMREG(fs, MIPSInst_FS(ir));
2359 SPFROMREG(ft, MIPSInst_FT(ir));
2361 /* positive predicates */
2362 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2363 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2365 rv.w = -1; /* true, all 1s */
2367 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2368 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2372 /* negative predicates */
2377 if (ieee754sp_cmp(fs, ft,
2378 negative_cmptab[cmpop],
2380 rv.w = -1; /* true, all 1s */
2382 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2383 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2388 /* Reserved R6 ops */
2389 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2400 if (!cpu_has_mips_3_4_5_64_r2_r6)
2403 DIFROMREG(bits, MIPSInst_FS(ir));
2405 switch (MIPSInst_FUNC(ir)) {
2407 /* convert long to single precision real */
2408 rv.s = ieee754sp_flong(bits);
2412 /* convert long to double precision real */
2413 rv.d = ieee754dp_flong(bits);
2417 /* Emulating the new CMP.condn.fmt R6 instruction */
2418 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2419 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2420 union ieee754dp fs, ft;
2422 if (!cpu_has_mips_r6 ||
2423 (MIPSInst_FUNC(ir) & 0x20))
2426 /* fmt is l_fmt for double precision so fix it */
2428 /* default to false */
2432 DPFROMREG(fs, MIPSInst_FS(ir));
2433 DPFROMREG(ft, MIPSInst_FT(ir));
2435 /* positive predicates */
2436 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2437 if (ieee754dp_cmp(fs, ft,
2438 cmptab[cmpop], sig))
2439 rv.l = -1LL; /* true, all 1s */
2441 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2442 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2446 /* negative predicates */
2451 if (ieee754dp_cmp(fs, ft,
2452 negative_cmptab[cmpop],
2454 rv.l = -1LL; /* true, all 1s */
2456 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2457 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2462 /* Reserved R6 ops */
2463 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2475 * Update the fpu CSR register for this operation.
2476 * If an exception is required, generate a tidy SIGFPE exception,
2477 * without updating the result register.
2478 * Note: cause exception bits do not accumulate, they are rewritten
2479 * for each op; only the flag/sticky bits accumulate.
2481 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2482 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2483 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2488 * Now we can safely write the result back to the register file.
2493 if (cpu_has_mips_4_5_r)
2494 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2496 cbit = FPU_CSR_COND;
2500 ctx->fcr31 &= ~cbit;
2504 DPTOREG(rv.d, MIPSInst_FD(ir));
2507 SPTOREG(rv.s, MIPSInst_FD(ir));
2510 SITOREG(rv.w, MIPSInst_FD(ir));
2513 if (!cpu_has_mips_3_4_5_64_r2_r6)
2516 DITOREG(rv.l, MIPSInst_FD(ir));
2525 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2526 int has_fpu, void *__user *fault_addr)
2528 unsigned long oldepc, prevepc;
2529 struct mm_decoded_insn dec_insn;
2534 oldepc = xcp->cp0_epc;
2536 prevepc = xcp->cp0_epc;
2538 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2540 * Get next 2 microMIPS instructions and convert them
2541 * into 32-bit instructions.
2543 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2544 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2545 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2546 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2547 MIPS_FPU_EMU_INC_STATS(errors);
2552 /* Get first instruction. */
2553 if (mm_insn_16bit(*instr_ptr)) {
2554 /* Duplicate the half-word. */
2555 dec_insn.insn = (*instr_ptr << 16) |
2557 /* 16-bit instruction. */
2558 dec_insn.pc_inc = 2;
2561 dec_insn.insn = (*instr_ptr << 16) |
2563 /* 32-bit instruction. */
2564 dec_insn.pc_inc = 4;
2567 /* Get second instruction. */
2568 if (mm_insn_16bit(*instr_ptr)) {
2569 /* Duplicate the half-word. */
2570 dec_insn.next_insn = (*instr_ptr << 16) |
2572 /* 16-bit instruction. */
2573 dec_insn.next_pc_inc = 2;
2575 dec_insn.next_insn = (*instr_ptr << 16) |
2577 /* 32-bit instruction. */
2578 dec_insn.next_pc_inc = 4;
2580 dec_insn.micro_mips_mode = 1;
2582 if ((get_user(dec_insn.insn,
2583 (mips_instruction __user *) xcp->cp0_epc)) ||
2584 (get_user(dec_insn.next_insn,
2585 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2586 MIPS_FPU_EMU_INC_STATS(errors);
2589 dec_insn.pc_inc = 4;
2590 dec_insn.next_pc_inc = 4;
2591 dec_insn.micro_mips_mode = 0;
2594 if ((dec_insn.insn == 0) ||
2595 ((dec_insn.pc_inc == 2) &&
2596 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2597 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2600 * The 'ieee754_csr' is an alias of ctx->fcr31.
2601 * No need to copy ctx->fcr31 to ieee754_csr.
2603 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2612 } while (xcp->cp0_epc > prevepc);
2614 /* SIGILL indicates a non-fpu instruction */
2615 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2616 /* but if EPC has advanced, then ignore it */