2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39 #include <linux/perf_event.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
49 #include <asm/uaccess.h>
50 #include <asm/branch.h>
54 /* Strap kernel emulator for full MIPS IV emulation */
61 /* Function which emulates a floating point instruction. */
63 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
66 #if __mips >= 4 && __mips != 32
67 static int fpux_emu(struct pt_regs *,
68 struct mips_fpu_struct *, mips_instruction, void *__user *);
71 /* Further private data for which no space exists in mips_fpu_struct */
73 #ifdef CONFIG_DEBUG_FS
74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
77 /* Control registers */
79 #define FPCREG_RID 0 /* $0 = revision id */
80 #define FPCREG_CSR 31 /* $31 = csr */
82 /* Determine rounding mode from the RM bits of the FCSR */
83 #define modeindex(v) ((v) & FPU_CSR_RM)
85 /* microMIPS bitfields */
86 #define MM_POOL32A_MINOR_MASK 0x3f
87 #define MM_POOL32A_MINOR_SHIFT 0x6
88 #define MM_MIPS32_COND_FC 0x30
90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
91 static const unsigned char ieee_rm[4] = {
92 [FPU_CSR_RN] = IEEE754_RN,
93 [FPU_CSR_RZ] = IEEE754_RZ,
94 [FPU_CSR_RU] = IEEE754_RU,
95 [FPU_CSR_RD] = IEEE754_RD,
97 /* Convert IEEE library modes to Mips rounding mode (0..3). */
98 static const unsigned char mips_rm[4] = {
99 [IEEE754_RN] = FPU_CSR_RN,
100 [IEEE754_RZ] = FPU_CSR_RZ,
101 [IEEE754_RD] = FPU_CSR_RD,
102 [IEEE754_RU] = FPU_CSR_RU,
106 /* convert condition code register number to csr bit */
107 static const unsigned int fpucondbit[8] = {
119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
120 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
123 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
124 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
125 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
126 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
129 * This functions translates a 32-bit microMIPS instruction
130 * into a 32-bit MIPS32 instruction. Returns 0 on success
131 * and SIGILL otherwise.
133 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
135 union mips_instruction insn = *insn_ptr;
136 union mips_instruction mips32_insn = insn;
139 switch (insn.mm_i_format.opcode) {
141 mips32_insn.mm_i_format.opcode = ldc1_op;
142 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
143 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
146 mips32_insn.mm_i_format.opcode = lwc1_op;
147 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
148 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
151 mips32_insn.mm_i_format.opcode = sdc1_op;
152 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
153 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
156 mips32_insn.mm_i_format.opcode = swc1_op;
157 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
158 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
161 /* NOTE: offset is << by 1 if in microMIPS mode. */
162 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
163 (insn.mm_i_format.rt == mm_bc1t_op)) {
164 mips32_insn.fb_format.opcode = cop1_op;
165 mips32_insn.fb_format.bc = bc_op;
166 mips32_insn.fb_format.flag =
167 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
172 switch (insn.mm_fp0_format.func) {
181 op = insn.mm_fp0_format.func;
182 if (op == mm_32f_01_op)
184 else if (op == mm_32f_11_op)
186 else if (op == mm_32f_02_op)
188 else if (op == mm_32f_12_op)
190 else if (op == mm_32f_41_op)
192 else if (op == mm_32f_51_op)
194 else if (op == mm_32f_42_op)
198 mips32_insn.fp6_format.opcode = cop1x_op;
199 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
200 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
201 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
202 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
203 mips32_insn.fp6_format.func = func;
206 func = -1; /* Invalid */
207 op = insn.mm_fp5_format.op & 0x7;
208 if (op == mm_ldxc1_op)
210 else if (op == mm_sdxc1_op)
212 else if (op == mm_lwxc1_op)
214 else if (op == mm_swxc1_op)
218 mips32_insn.r_format.opcode = cop1x_op;
219 mips32_insn.r_format.rs =
220 insn.mm_fp5_format.base;
221 mips32_insn.r_format.rt =
222 insn.mm_fp5_format.index;
223 mips32_insn.r_format.rd = 0;
224 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
225 mips32_insn.r_format.func = func;
230 op = -1; /* Invalid */
231 if (insn.mm_fp2_format.op == mm_fmovt_op)
233 else if (insn.mm_fp2_format.op == mm_fmovf_op)
236 mips32_insn.fp0_format.opcode = cop1_op;
237 mips32_insn.fp0_format.fmt =
238 sdps_format[insn.mm_fp2_format.fmt];
239 mips32_insn.fp0_format.ft =
240 (insn.mm_fp2_format.cc<<2) + op;
241 mips32_insn.fp0_format.fs =
242 insn.mm_fp2_format.fs;
243 mips32_insn.fp0_format.fd =
244 insn.mm_fp2_format.fd;
245 mips32_insn.fp0_format.func = fmovc_op;
250 func = -1; /* Invalid */
251 if (insn.mm_fp0_format.op == mm_fadd_op)
253 else if (insn.mm_fp0_format.op == mm_fsub_op)
255 else if (insn.mm_fp0_format.op == mm_fmul_op)
257 else if (insn.mm_fp0_format.op == mm_fdiv_op)
260 mips32_insn.fp0_format.opcode = cop1_op;
261 mips32_insn.fp0_format.fmt =
262 sdps_format[insn.mm_fp0_format.fmt];
263 mips32_insn.fp0_format.ft =
264 insn.mm_fp0_format.ft;
265 mips32_insn.fp0_format.fs =
266 insn.mm_fp0_format.fs;
267 mips32_insn.fp0_format.fd =
268 insn.mm_fp0_format.fd;
269 mips32_insn.fp0_format.func = func;
274 func = -1; /* Invalid */
275 if (insn.mm_fp0_format.op == mm_fmovn_op)
277 else if (insn.mm_fp0_format.op == mm_fmovz_op)
280 mips32_insn.fp0_format.opcode = cop1_op;
281 mips32_insn.fp0_format.fmt =
282 sdps_format[insn.mm_fp0_format.fmt];
283 mips32_insn.fp0_format.ft =
284 insn.mm_fp0_format.ft;
285 mips32_insn.fp0_format.fs =
286 insn.mm_fp0_format.fs;
287 mips32_insn.fp0_format.fd =
288 insn.mm_fp0_format.fd;
289 mips32_insn.fp0_format.func = func;
293 case mm_32f_73_op: /* POOL32FXF */
294 switch (insn.mm_fp1_format.op) {
299 if ((insn.mm_fp1_format.op & 0x7f) ==
304 mips32_insn.r_format.opcode = spec_op;
305 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
306 mips32_insn.r_format.rt =
307 (insn.mm_fp4_format.cc << 2) + op;
308 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
309 mips32_insn.r_format.re = 0;
310 mips32_insn.r_format.func = movc_op;
316 if ((insn.mm_fp1_format.op & 0x7f) ==
319 fmt = swl_format[insn.mm_fp3_format.fmt];
322 fmt = dwl_format[insn.mm_fp3_format.fmt];
324 mips32_insn.fp0_format.opcode = cop1_op;
325 mips32_insn.fp0_format.fmt = fmt;
326 mips32_insn.fp0_format.ft = 0;
327 mips32_insn.fp0_format.fs =
328 insn.mm_fp3_format.fs;
329 mips32_insn.fp0_format.fd =
330 insn.mm_fp3_format.rt;
331 mips32_insn.fp0_format.func = func;
339 if ((insn.mm_fp1_format.op & 0x7f) ==
342 else if ((insn.mm_fp1_format.op & 0x7f) ==
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sdps_format[insn.mm_fp3_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp3_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp3_format.rt;
355 mips32_insn.fp0_format.func = func;
367 if (insn.mm_fp1_format.op == mm_ffloorl_op)
369 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
371 else if (insn.mm_fp1_format.op == mm_fceill_op)
373 else if (insn.mm_fp1_format.op == mm_fceilw_op)
375 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
377 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
379 else if (insn.mm_fp1_format.op == mm_froundl_op)
381 else if (insn.mm_fp1_format.op == mm_froundw_op)
383 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
387 mips32_insn.fp0_format.opcode = cop1_op;
388 mips32_insn.fp0_format.fmt =
389 sd_format[insn.mm_fp1_format.fmt];
390 mips32_insn.fp0_format.ft = 0;
391 mips32_insn.fp0_format.fs =
392 insn.mm_fp1_format.fs;
393 mips32_insn.fp0_format.fd =
394 insn.mm_fp1_format.rt;
395 mips32_insn.fp0_format.func = func;
400 if (insn.mm_fp1_format.op == mm_frsqrt_op)
402 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
406 mips32_insn.fp0_format.opcode = cop1_op;
407 mips32_insn.fp0_format.fmt =
408 sdps_format[insn.mm_fp1_format.fmt];
409 mips32_insn.fp0_format.ft = 0;
410 mips32_insn.fp0_format.fs =
411 insn.mm_fp1_format.fs;
412 mips32_insn.fp0_format.fd =
413 insn.mm_fp1_format.rt;
414 mips32_insn.fp0_format.func = func;
422 if (insn.mm_fp1_format.op == mm_mfc1_op)
424 else if (insn.mm_fp1_format.op == mm_mtc1_op)
426 else if (insn.mm_fp1_format.op == mm_cfc1_op)
428 else if (insn.mm_fp1_format.op == mm_ctc1_op)
430 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
434 mips32_insn.fp1_format.opcode = cop1_op;
435 mips32_insn.fp1_format.op = op;
436 mips32_insn.fp1_format.rt =
437 insn.mm_fp1_format.rt;
438 mips32_insn.fp1_format.fs =
439 insn.mm_fp1_format.fs;
440 mips32_insn.fp1_format.fd = 0;
441 mips32_insn.fp1_format.func = 0;
447 case mm_32f_74_op: /* c.cond.fmt */
448 mips32_insn.fp0_format.opcode = cop1_op;
449 mips32_insn.fp0_format.fmt =
450 sdps_format[insn.mm_fp4_format.fmt];
451 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
452 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
453 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
454 mips32_insn.fp0_format.func =
455 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
465 *insn_ptr = mips32_insn;
469 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
470 unsigned long *contpc)
472 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
480 switch (insn.mm_i_format.opcode) {
482 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
484 switch (insn.mm_i_format.simmediate >>
485 MM_POOL32A_MINOR_SHIFT) {
490 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
491 regs->regs[insn.mm_i_format.rt] =
494 dec_insn.next_pc_inc;
495 *contpc = regs->regs[insn.mm_i_format.rs];
501 switch (insn.mm_i_format.rt) {
504 regs->regs[31] = regs->cp0_epc +
506 dec_insn.next_pc_inc;
509 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
510 *contpc = regs->cp0_epc +
512 (insn.mm_i_format.simmediate << 1);
514 *contpc = regs->cp0_epc +
516 dec_insn.next_pc_inc;
520 regs->regs[31] = regs->cp0_epc +
522 dec_insn.next_pc_inc;
525 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
526 *contpc = regs->cp0_epc +
528 (insn.mm_i_format.simmediate << 1);
530 *contpc = regs->cp0_epc +
532 dec_insn.next_pc_inc;
535 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
536 *contpc = regs->cp0_epc +
538 (insn.mm_i_format.simmediate << 1);
540 *contpc = regs->cp0_epc +
542 dec_insn.next_pc_inc;
545 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
546 *contpc = regs->cp0_epc +
548 (insn.mm_i_format.simmediate << 1);
550 *contpc = regs->cp0_epc +
552 dec_insn.next_pc_inc;
562 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
564 fcr31 = current->thread.fpu.fcr31;
570 bit = (insn.mm_i_format.rs >> 2);
573 if (fcr31 & (1 << bit))
574 *contpc = regs->cp0_epc +
576 (insn.mm_i_format.simmediate << 1);
578 *contpc = regs->cp0_epc +
579 dec_insn.pc_inc + dec_insn.next_pc_inc;
584 switch (insn.mm_i_format.rt) {
587 regs->regs[31] = regs->cp0_epc +
588 dec_insn.pc_inc + dec_insn.next_pc_inc;
591 *contpc = regs->regs[insn.mm_i_format.rs];
596 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
597 *contpc = regs->cp0_epc +
599 (insn.mm_b1_format.simmediate << 1);
601 *contpc = regs->cp0_epc +
602 dec_insn.pc_inc + dec_insn.next_pc_inc;
605 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
606 *contpc = regs->cp0_epc +
608 (insn.mm_b1_format.simmediate << 1);
610 *contpc = regs->cp0_epc +
611 dec_insn.pc_inc + dec_insn.next_pc_inc;
614 *contpc = regs->cp0_epc + dec_insn.pc_inc +
615 (insn.mm_b0_format.simmediate << 1);
618 if (regs->regs[insn.mm_i_format.rs] ==
619 regs->regs[insn.mm_i_format.rt])
620 *contpc = regs->cp0_epc +
622 (insn.mm_i_format.simmediate << 1);
624 *contpc = regs->cp0_epc +
626 dec_insn.next_pc_inc;
629 if (regs->regs[insn.mm_i_format.rs] !=
630 regs->regs[insn.mm_i_format.rt])
631 *contpc = regs->cp0_epc +
633 (insn.mm_i_format.simmediate << 1);
635 *contpc = regs->cp0_epc +
636 dec_insn.pc_inc + dec_insn.next_pc_inc;
639 regs->regs[31] = regs->cp0_epc +
640 dec_insn.pc_inc + dec_insn.next_pc_inc;
641 *contpc = regs->cp0_epc + dec_insn.pc_inc;
644 *contpc |= (insn.j_format.target << 2);
648 regs->regs[31] = regs->cp0_epc +
649 dec_insn.pc_inc + dec_insn.next_pc_inc;
652 *contpc = regs->cp0_epc + dec_insn.pc_inc;
655 *contpc |= (insn.j_format.target << 1);
656 set_isa16_mode(*contpc);
663 * Redundant with logic already in kernel/branch.c,
664 * embedded in compute_return_epc. At some point,
665 * a single subroutine should be used across both
668 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
669 unsigned long *contpc)
671 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
673 unsigned int bit = 0;
675 switch (insn.i_format.opcode) {
677 switch (insn.r_format.func) {
679 regs->regs[insn.r_format.rd] =
680 regs->cp0_epc + dec_insn.pc_inc +
681 dec_insn.next_pc_inc;
684 *contpc = regs->regs[insn.r_format.rs];
689 switch (insn.i_format.rt) {
692 regs->regs[31] = regs->cp0_epc +
694 dec_insn.next_pc_inc;
698 if ((long)regs->regs[insn.i_format.rs] < 0)
699 *contpc = regs->cp0_epc +
701 (insn.i_format.simmediate << 2);
703 *contpc = regs->cp0_epc +
705 dec_insn.next_pc_inc;
709 regs->regs[31] = regs->cp0_epc +
711 dec_insn.next_pc_inc;
715 if ((long)regs->regs[insn.i_format.rs] >= 0)
716 *contpc = regs->cp0_epc +
718 (insn.i_format.simmediate << 2);
720 *contpc = regs->cp0_epc +
722 dec_insn.next_pc_inc;
729 regs->regs[31] = regs->cp0_epc +
731 dec_insn.next_pc_inc;
734 *contpc = regs->cp0_epc + dec_insn.pc_inc;
737 *contpc |= (insn.j_format.target << 2);
738 /* Set microMIPS mode bit: XOR for jalx. */
743 if (regs->regs[insn.i_format.rs] ==
744 regs->regs[insn.i_format.rt])
745 *contpc = regs->cp0_epc +
747 (insn.i_format.simmediate << 2);
749 *contpc = regs->cp0_epc +
751 dec_insn.next_pc_inc;
755 if (regs->regs[insn.i_format.rs] !=
756 regs->regs[insn.i_format.rt])
757 *contpc = regs->cp0_epc +
759 (insn.i_format.simmediate << 2);
761 *contpc = regs->cp0_epc +
763 dec_insn.next_pc_inc;
767 if ((long)regs->regs[insn.i_format.rs] <= 0)
768 *contpc = regs->cp0_epc +
770 (insn.i_format.simmediate << 2);
772 *contpc = regs->cp0_epc +
774 dec_insn.next_pc_inc;
778 if ((long)regs->regs[insn.i_format.rs] > 0)
779 *contpc = regs->cp0_epc +
781 (insn.i_format.simmediate << 2);
783 *contpc = regs->cp0_epc +
785 dec_insn.next_pc_inc;
787 #ifdef CONFIG_CPU_CAVIUM_OCTEON
788 case lwc2_op: /* This is bbit0 on Octeon */
789 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
790 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
792 *contpc = regs->cp0_epc + 8;
794 case ldc2_op: /* This is bbit032 on Octeon */
795 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
796 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
798 *contpc = regs->cp0_epc + 8;
800 case swc2_op: /* This is bbit1 on Octeon */
801 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
802 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
804 *contpc = regs->cp0_epc + 8;
806 case sdc2_op: /* This is bbit132 on Octeon */
807 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
808 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
810 *contpc = regs->cp0_epc + 8;
817 if (insn.i_format.rs == bc_op) {
820 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
822 fcr31 = current->thread.fpu.fcr31;
825 bit = (insn.i_format.rt >> 2);
828 switch (insn.i_format.rt & 3) {
831 if (~fcr31 & (1 << bit))
832 *contpc = regs->cp0_epc +
834 (insn.i_format.simmediate << 2);
836 *contpc = regs->cp0_epc +
838 dec_insn.next_pc_inc;
842 if (fcr31 & (1 << bit))
843 *contpc = regs->cp0_epc +
845 (insn.i_format.simmediate << 2);
847 *contpc = regs->cp0_epc +
849 dec_insn.next_pc_inc;
859 * In the Linux kernel, we support selection of FPR format on the
860 * basis of the Status.FR bit. If an FPU is not present, the FR bit
861 * is hardwired to zero, which would imply a 32-bit FPU even for
862 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
863 * FPU emu is slow and bulky and optimizing this function offers fairly
864 * sizeable benefits so we try to be clever and make this function return
865 * a constant whenever possible, that is on 64-bit kernels without O32
866 * compatibility enabled and on 32-bit without 64-bit FPU support.
868 static inline int cop1_64bit(struct pt_regs *xcp)
870 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
872 #elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
875 return !test_thread_flag(TIF_32BIT_FPREGS);
879 #define SIFROMREG(si, x) do { \
880 if (cop1_64bit(xcp)) \
881 (si) = get_fpr32(&ctx->fpr[x], 0); \
883 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
886 #define SITOREG(si, x) do { \
887 if (cop1_64bit(xcp)) { \
889 set_fpr32(&ctx->fpr[x], 0, si); \
890 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
891 set_fpr32(&ctx->fpr[x], i, 0); \
893 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
897 #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
899 #define SITOHREG(si, x) do { \
901 set_fpr32(&ctx->fpr[x], 1, si); \
902 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
903 set_fpr32(&ctx->fpr[x], i, 0); \
906 #define DIFROMREG(di, x) \
907 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
909 #define DITOREG(di, x) do { \
911 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
912 set_fpr64(&ctx->fpr[fpr], 0, di); \
913 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
914 set_fpr64(&ctx->fpr[fpr], i, 0); \
917 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
918 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
919 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
920 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
923 * Emulate the single floating point instruction pointed at by EPC.
924 * Two instructions if the instruction is in a branch delay slot.
927 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
928 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
931 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
935 /* XXX NEC Vr54xx bug workaround */
936 if (xcp->cp0_cause & CAUSEF_BD) {
937 if (dec_insn.micro_mips_mode) {
938 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
939 xcp->cp0_cause &= ~CAUSEF_BD;
941 if (!isBranchInstr(xcp, dec_insn, &contpc))
942 xcp->cp0_cause &= ~CAUSEF_BD;
946 if (xcp->cp0_cause & CAUSEF_BD) {
948 * The instruction to be emulated is in a branch delay slot
949 * which means that we have to emulate the branch instruction
950 * BEFORE we do the cop1 instruction.
952 * This branch could be a COP1 branch, but in that case we
953 * would have had a trap for that instruction, and would not
954 * come through this route.
956 * Linux MIPS branch emulator operates on context, updating the
959 ir = dec_insn.next_insn; /* process delay slot instr */
960 pc_inc = dec_insn.next_pc_inc;
962 ir = dec_insn.insn; /* process current instr */
963 pc_inc = dec_insn.pc_inc;
967 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
968 * instructions, we want to convert microMIPS FPU instructions
969 * into MIPS32 instructions so that we could reuse all of the
970 * FPU emulation code.
972 * NOTE: We cannot do this for branch instructions since they
973 * are not a subset. Example: Cannot emulate a 16-bit
974 * aligned target address with a MIPS32 instruction.
976 if (dec_insn.micro_mips_mode) {
978 * If next instruction is a 16-bit instruction, then it
979 * it cannot be a FPU instruction. This could happen
980 * since we can be called for non-FPU instructions.
983 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
989 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
990 MIPS_FPU_EMU_INC_STATS(emulated);
991 switch (MIPSInst_OPCODE(ir)) {
993 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
997 MIPS_FPU_EMU_INC_STATS(loads);
999 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1000 MIPS_FPU_EMU_INC_STATS(errors);
1004 if (__get_user(val, va)) {
1005 MIPS_FPU_EMU_INC_STATS(errors);
1009 DITOREG(val, MIPSInst_RT(ir));
1014 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1018 MIPS_FPU_EMU_INC_STATS(stores);
1019 DIFROMREG(val, MIPSInst_RT(ir));
1020 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1021 MIPS_FPU_EMU_INC_STATS(errors);
1025 if (__put_user(val, va)) {
1026 MIPS_FPU_EMU_INC_STATS(errors);
1034 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1038 MIPS_FPU_EMU_INC_STATS(loads);
1039 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1040 MIPS_FPU_EMU_INC_STATS(errors);
1044 if (__get_user(val, va)) {
1045 MIPS_FPU_EMU_INC_STATS(errors);
1049 SITOREG(val, MIPSInst_RT(ir));
1054 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1058 MIPS_FPU_EMU_INC_STATS(stores);
1059 SIFROMREG(val, MIPSInst_RT(ir));
1060 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1061 MIPS_FPU_EMU_INC_STATS(errors);
1065 if (__put_user(val, va)) {
1066 MIPS_FPU_EMU_INC_STATS(errors);
1074 switch (MIPSInst_RS(ir)) {
1076 #if defined(__mips64)
1078 /* copregister fs -> gpr[rt] */
1079 if (MIPSInst_RT(ir) != 0) {
1080 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1086 /* copregister fs <- rt */
1087 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1092 if (!cpu_has_mips_r2)
1095 /* copregister rd -> gpr[rt] */
1096 if (MIPSInst_RT(ir) != 0) {
1097 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1103 if (!cpu_has_mips_r2)
1106 /* copregister rd <- gpr[rt] */
1107 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1111 /* copregister rd -> gpr[rt] */
1112 if (MIPSInst_RT(ir) != 0) {
1113 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1119 /* copregister rd <- rt */
1120 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1124 /* cop control register rd -> gpr[rt] */
1127 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1129 value = (value & ~FPU_CSR_RM) |
1130 mips_rm[modeindex(value)];
1132 printk("%p gpr[%d]<-csr=%08x\n",
1133 (void *) (xcp->cp0_epc),
1134 MIPSInst_RT(ir), value);
1137 else if (MIPSInst_RD(ir) == FPCREG_RID)
1141 if (MIPSInst_RT(ir))
1142 xcp->regs[MIPSInst_RT(ir)] = value;
1147 /* copregister rd <- rt */
1150 if (MIPSInst_RT(ir) == 0)
1153 value = xcp->regs[MIPSInst_RT(ir)];
1155 /* we only have one writable control reg
1157 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1159 printk("%p gpr[%d]->csr=%08x\n",
1160 (void *) (xcp->cp0_epc),
1161 MIPSInst_RT(ir), value);
1165 * Don't write reserved bits,
1166 * and convert to ieee library modes
1168 ctx->fcr31 = (value &
1169 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1170 ieee_rm[modeindex(value)];
1172 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1181 if (xcp->cp0_cause & CAUSEF_BD)
1185 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1187 cond = ctx->fcr31 & FPU_CSR_COND;
1189 switch (MIPSInst_RT(ir) & 3) {
1200 /* thats an illegal instruction */
1204 xcp->cp0_cause |= CAUSEF_BD;
1206 /* branch taken: emulate dslot
1209 xcp->cp0_epc += dec_insn.pc_inc;
1211 contpc = MIPSInst_SIMM(ir);
1212 ir = dec_insn.next_insn;
1213 if (dec_insn.micro_mips_mode) {
1214 contpc = (xcp->cp0_epc + (contpc << 1));
1216 /* If 16-bit instruction, not FPU. */
1217 if ((dec_insn.next_pc_inc == 2) ||
1218 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1221 * Since this instruction will
1222 * be put on the stack with
1223 * 32-bit words, get around
1224 * this problem by putting a
1225 * NOP16 as the second one.
1227 if (dec_insn.next_pc_inc == 2)
1228 ir = (ir & (~0xffff)) | MM_NOP16;
1231 * Single step the non-CP1
1232 * instruction in the dslot.
1234 return mips_dsemul(xcp, ir, contpc);
1237 contpc = (xcp->cp0_epc + (contpc << 2));
1239 switch (MIPSInst_OPCODE(ir)) {
1242 #if (__mips >= 2 || defined(__mips64))
1247 #if __mips >= 4 && __mips != 32
1250 /* its one of ours */
1254 if (MIPSInst_FUNC(ir) == movc_op)
1261 * Single step the non-cp1
1262 * instruction in the dslot
1264 return mips_dsemul(xcp, ir, contpc);
1267 /* branch not taken */
1270 * branch likely nullifies
1271 * dslot if not taken
1273 xcp->cp0_epc += dec_insn.pc_inc;
1274 contpc += dec_insn.pc_inc;
1276 * else continue & execute
1277 * dslot as normal insn
1285 if (!(MIPSInst_RS(ir) & 0x10))
1290 /* a real fpu computation instruction */
1291 if ((sig = fpu_emu(xcp, ctx, ir)))
1297 #if __mips >= 4 && __mips != 32
1299 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1308 if (MIPSInst_FUNC(ir) != movc_op)
1310 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1311 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1312 xcp->regs[MIPSInst_RD(ir)] =
1313 xcp->regs[MIPSInst_RS(ir)];
1323 xcp->cp0_epc = contpc;
1324 xcp->cp0_cause &= ~CAUSEF_BD;
1330 * Conversion table from MIPS compare ops 48-63
1331 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1333 static const unsigned char cmptab[8] = {
1334 0, /* cmp_0 (sig) cmp_sf */
1335 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1336 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1337 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1338 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1339 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1340 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1341 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1345 #if __mips >= 4 && __mips != 32
1348 * Additional MIPS4 instructions
1351 #define DEF3OP(name, p, f1, f2, f3) \
1352 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, union ieee754##p s, \
1353 union ieee754##p t) \
1355 struct _ieee754_csr ieee754_csr_save; \
1357 ieee754_csr_save = ieee754_csr; \
1359 ieee754_csr_save.cx |= ieee754_csr.cx; \
1360 ieee754_csr_save.sx |= ieee754_csr.sx; \
1362 ieee754_csr.cx |= ieee754_csr_save.cx; \
1363 ieee754_csr.sx |= ieee754_csr_save.sx; \
1367 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1369 return ieee754dp_div(ieee754dp_one(0), d);
1372 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1374 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1377 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1379 return ieee754sp_div(ieee754sp_one(0), s);
1382 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1384 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1387 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1388 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1389 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1390 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1391 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1392 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1393 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1394 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1396 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1397 mips_instruction ir, void *__user *fault_addr)
1399 unsigned rcsr = 0; /* resulting csr */
1401 MIPS_FPU_EMU_INC_STATS(cp1xops);
1403 switch (MIPSInst_FMA_FFMT(ir)) {
1404 case s_fmt:{ /* 0 */
1406 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1407 union ieee754sp fd, fr, fs, ft;
1411 switch (MIPSInst_FUNC(ir)) {
1413 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1414 xcp->regs[MIPSInst_FT(ir)]);
1416 MIPS_FPU_EMU_INC_STATS(loads);
1417 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1418 MIPS_FPU_EMU_INC_STATS(errors);
1422 if (__get_user(val, va)) {
1423 MIPS_FPU_EMU_INC_STATS(errors);
1427 SITOREG(val, MIPSInst_FD(ir));
1431 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1432 xcp->regs[MIPSInst_FT(ir)]);
1434 MIPS_FPU_EMU_INC_STATS(stores);
1436 SIFROMREG(val, MIPSInst_FS(ir));
1437 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1438 MIPS_FPU_EMU_INC_STATS(errors);
1442 if (put_user(val, va)) {
1443 MIPS_FPU_EMU_INC_STATS(errors);
1450 handler = fpemu_sp_madd;
1453 handler = fpemu_sp_msub;
1456 handler = fpemu_sp_nmadd;
1459 handler = fpemu_sp_nmsub;
1463 SPFROMREG(fr, MIPSInst_FR(ir));
1464 SPFROMREG(fs, MIPSInst_FS(ir));
1465 SPFROMREG(ft, MIPSInst_FT(ir));
1466 fd = (*handler) (fr, fs, ft);
1467 SPTOREG(fd, MIPSInst_FD(ir));
1470 if (ieee754_cxtest(IEEE754_INEXACT))
1471 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1472 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1473 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1474 if (ieee754_cxtest(IEEE754_OVERFLOW))
1475 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1476 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1477 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1479 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1480 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1481 /*printk ("SIGFPE: fpu csr = %08x\n",
1494 case d_fmt:{ /* 1 */
1495 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1496 union ieee754dp fd, fr, fs, ft;
1500 switch (MIPSInst_FUNC(ir)) {
1502 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1503 xcp->regs[MIPSInst_FT(ir)]);
1505 MIPS_FPU_EMU_INC_STATS(loads);
1506 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1507 MIPS_FPU_EMU_INC_STATS(errors);
1511 if (__get_user(val, va)) {
1512 MIPS_FPU_EMU_INC_STATS(errors);
1516 DITOREG(val, MIPSInst_FD(ir));
1520 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1521 xcp->regs[MIPSInst_FT(ir)]);
1523 MIPS_FPU_EMU_INC_STATS(stores);
1524 DIFROMREG(val, MIPSInst_FS(ir));
1525 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1526 MIPS_FPU_EMU_INC_STATS(errors);
1530 if (__put_user(val, va)) {
1531 MIPS_FPU_EMU_INC_STATS(errors);
1538 handler = fpemu_dp_madd;
1541 handler = fpemu_dp_msub;
1544 handler = fpemu_dp_nmadd;
1547 handler = fpemu_dp_nmsub;
1551 DPFROMREG(fr, MIPSInst_FR(ir));
1552 DPFROMREG(fs, MIPSInst_FS(ir));
1553 DPFROMREG(ft, MIPSInst_FT(ir));
1554 fd = (*handler) (fr, fs, ft);
1555 DPTOREG(fd, MIPSInst_FD(ir));
1565 if (MIPSInst_FUNC(ir) != pfetch_op)
1568 /* ignore prefx operation */
1582 * Emulate a single COP1 arithmetic instruction.
1584 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1585 mips_instruction ir)
1587 int rfmt; /* resulting format */
1588 unsigned rcsr = 0; /* resulting csr */
1597 } rv; /* resulting value */
1599 MIPS_FPU_EMU_INC_STATS(cp1ops);
1600 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1601 case s_fmt:{ /* 0 */
1603 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1604 union ieee754sp(*u) (union ieee754sp);
1607 switch (MIPSInst_FUNC(ir)) {
1610 handler.b = ieee754sp_add;
1613 handler.b = ieee754sp_sub;
1616 handler.b = ieee754sp_mul;
1619 handler.b = ieee754sp_div;
1623 #if __mips >= 2 || defined(__mips64)
1625 handler.u = ieee754sp_sqrt;
1628 #if __mips >= 4 && __mips != 32
1630 handler.u = fpemu_sp_rsqrt;
1633 handler.u = fpemu_sp_recip;
1638 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1639 if (((ctx->fcr31 & cond) != 0) !=
1640 ((MIPSInst_FT(ir) & 1) != 0))
1642 SPFROMREG(rv.s, MIPSInst_FS(ir));
1645 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1647 SPFROMREG(rv.s, MIPSInst_FS(ir));
1650 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1652 SPFROMREG(rv.s, MIPSInst_FS(ir));
1656 handler.u = ieee754sp_abs;
1659 handler.u = ieee754sp_neg;
1663 SPFROMREG(rv.s, MIPSInst_FS(ir));
1666 /* binary op on handler */
1669 union ieee754sp fs, ft;
1671 SPFROMREG(fs, MIPSInst_FS(ir));
1672 SPFROMREG(ft, MIPSInst_FT(ir));
1674 rv.s = (*handler.b) (fs, ft);
1681 SPFROMREG(fs, MIPSInst_FS(ir));
1682 rv.s = (*handler.u) (fs);
1686 if (ieee754_cxtest(IEEE754_INEXACT))
1687 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1688 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1689 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1690 if (ieee754_cxtest(IEEE754_OVERFLOW))
1691 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1692 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1693 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1694 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1695 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1698 /* unary conv ops */
1700 return SIGILL; /* not defined */
1704 SPFROMREG(fs, MIPSInst_FS(ir));
1705 rv.d = ieee754dp_fsp(fs);
1712 SPFROMREG(fs, MIPSInst_FS(ir));
1713 rv.w = ieee754sp_tint(fs);
1718 #if __mips >= 2 || defined(__mips64)
1723 unsigned int oldrm = ieee754_csr.rm;
1726 SPFROMREG(fs, MIPSInst_FS(ir));
1727 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1728 rv.w = ieee754sp_tint(fs);
1729 ieee754_csr.rm = oldrm;
1733 #endif /* __mips >= 2 */
1735 #if defined(__mips64)
1739 SPFROMREG(fs, MIPSInst_FS(ir));
1740 rv.l = ieee754sp_tlong(fs);
1749 unsigned int oldrm = ieee754_csr.rm;
1752 SPFROMREG(fs, MIPSInst_FS(ir));
1753 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1754 rv.l = ieee754sp_tlong(fs);
1755 ieee754_csr.rm = oldrm;
1759 #endif /* defined(__mips64) */
1762 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1763 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1764 union ieee754sp fs, ft;
1766 SPFROMREG(fs, MIPSInst_FS(ir));
1767 SPFROMREG(ft, MIPSInst_FT(ir));
1768 rv.w = ieee754sp_cmp(fs, ft,
1769 cmptab[cmpop & 0x7], cmpop & 0x8);
1771 if ((cmpop & 0x8) && ieee754_cxtest
1772 (IEEE754_INVALID_OPERATION))
1773 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1788 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1789 union ieee754dp(*u) (union ieee754dp);
1792 switch (MIPSInst_FUNC(ir)) {
1795 handler.b = ieee754dp_add;
1798 handler.b = ieee754dp_sub;
1801 handler.b = ieee754dp_mul;
1804 handler.b = ieee754dp_div;
1808 #if __mips >= 2 || defined(__mips64)
1810 handler.u = ieee754dp_sqrt;
1813 #if __mips >= 4 && __mips != 32
1815 handler.u = fpemu_dp_rsqrt;
1818 handler.u = fpemu_dp_recip;
1823 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1824 if (((ctx->fcr31 & cond) != 0) !=
1825 ((MIPSInst_FT(ir) & 1) != 0))
1827 DPFROMREG(rv.d, MIPSInst_FS(ir));
1830 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1832 DPFROMREG(rv.d, MIPSInst_FS(ir));
1835 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1837 DPFROMREG(rv.d, MIPSInst_FS(ir));
1841 handler.u = ieee754dp_abs;
1845 handler.u = ieee754dp_neg;
1850 DPFROMREG(rv.d, MIPSInst_FS(ir));
1853 /* binary op on handler */
1855 union ieee754dp fs, ft;
1857 DPFROMREG(fs, MIPSInst_FS(ir));
1858 DPFROMREG(ft, MIPSInst_FT(ir));
1860 rv.d = (*handler.b) (fs, ft);
1866 DPFROMREG(fs, MIPSInst_FS(ir));
1867 rv.d = (*handler.u) (fs);
1871 /* unary conv ops */
1875 DPFROMREG(fs, MIPSInst_FS(ir));
1876 rv.s = ieee754sp_fdp(fs);
1881 return SIGILL; /* not defined */
1886 DPFROMREG(fs, MIPSInst_FS(ir));
1887 rv.w = ieee754dp_tint(fs); /* wrong */
1892 #if __mips >= 2 || defined(__mips64)
1897 unsigned int oldrm = ieee754_csr.rm;
1900 DPFROMREG(fs, MIPSInst_FS(ir));
1901 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1902 rv.w = ieee754dp_tint(fs);
1903 ieee754_csr.rm = oldrm;
1909 #if defined(__mips64)
1913 DPFROMREG(fs, MIPSInst_FS(ir));
1914 rv.l = ieee754dp_tlong(fs);
1923 unsigned int oldrm = ieee754_csr.rm;
1926 DPFROMREG(fs, MIPSInst_FS(ir));
1927 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1928 rv.l = ieee754dp_tlong(fs);
1929 ieee754_csr.rm = oldrm;
1933 #endif /* __mips >= 3 */
1936 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1937 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1938 union ieee754dp fs, ft;
1940 DPFROMREG(fs, MIPSInst_FS(ir));
1941 DPFROMREG(ft, MIPSInst_FT(ir));
1942 rv.w = ieee754dp_cmp(fs, ft,
1943 cmptab[cmpop & 0x7], cmpop & 0x8);
1948 (IEEE754_INVALID_OPERATION))
1949 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1965 switch (MIPSInst_FUNC(ir)) {
1967 /* convert word to single precision real */
1968 SPFROMREG(fs, MIPSInst_FS(ir));
1969 rv.s = ieee754sp_fint(fs.bits);
1973 /* convert word to double precision real */
1974 SPFROMREG(fs, MIPSInst_FS(ir));
1975 rv.d = ieee754dp_fint(fs.bits);
1984 #if defined(__mips64)
1987 DIFROMREG(bits, MIPSInst_FS(ir));
1989 switch (MIPSInst_FUNC(ir)) {
1991 /* convert long to single precision real */
1992 rv.s = ieee754sp_flong(bits);
1996 /* convert long to double precision real */
1997 rv.d = ieee754dp_flong(bits);
2012 * Update the fpu CSR register for this operation.
2013 * If an exception is required, generate a tidy SIGFPE exception,
2014 * without updating the result register.
2015 * Note: cause exception bits do not accumulate, they are rewritten
2016 * for each op; only the flag/sticky bits accumulate.
2018 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2019 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2020 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
2025 * Now we can safely write the result back to the register file.
2030 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
2032 cond = FPU_CSR_COND;
2037 ctx->fcr31 &= ~cond;
2041 DPTOREG(rv.d, MIPSInst_FD(ir));
2044 SPTOREG(rv.s, MIPSInst_FD(ir));
2047 SITOREG(rv.w, MIPSInst_FD(ir));
2049 #if defined(__mips64)
2051 DITOREG(rv.l, MIPSInst_FD(ir));
2061 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2062 int has_fpu, void *__user *fault_addr)
2064 unsigned long oldepc, prevepc;
2065 struct mm_decoded_insn dec_insn;
2070 oldepc = xcp->cp0_epc;
2072 prevepc = xcp->cp0_epc;
2074 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2076 * Get next 2 microMIPS instructions and convert them
2077 * into 32-bit instructions.
2079 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2080 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2081 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2082 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2083 MIPS_FPU_EMU_INC_STATS(errors);
2088 /* Get first instruction. */
2089 if (mm_insn_16bit(*instr_ptr)) {
2090 /* Duplicate the half-word. */
2091 dec_insn.insn = (*instr_ptr << 16) |
2093 /* 16-bit instruction. */
2094 dec_insn.pc_inc = 2;
2097 dec_insn.insn = (*instr_ptr << 16) |
2099 /* 32-bit instruction. */
2100 dec_insn.pc_inc = 4;
2103 /* Get second instruction. */
2104 if (mm_insn_16bit(*instr_ptr)) {
2105 /* Duplicate the half-word. */
2106 dec_insn.next_insn = (*instr_ptr << 16) |
2108 /* 16-bit instruction. */
2109 dec_insn.next_pc_inc = 2;
2111 dec_insn.next_insn = (*instr_ptr << 16) |
2113 /* 32-bit instruction. */
2114 dec_insn.next_pc_inc = 4;
2116 dec_insn.micro_mips_mode = 1;
2118 if ((get_user(dec_insn.insn,
2119 (mips_instruction __user *) xcp->cp0_epc)) ||
2120 (get_user(dec_insn.next_insn,
2121 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2122 MIPS_FPU_EMU_INC_STATS(errors);
2125 dec_insn.pc_inc = 4;
2126 dec_insn.next_pc_inc = 4;
2127 dec_insn.micro_mips_mode = 0;
2130 if ((dec_insn.insn == 0) ||
2131 ((dec_insn.pc_inc == 2) &&
2132 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2133 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2136 * The 'ieee754_csr' is an alias of
2137 * ctx->fcr31. No need to copy ctx->fcr31 to
2138 * ieee754_csr. But ieee754_csr.rm is ieee
2139 * library modes. (not mips rounding mode)
2141 /* convert to ieee library modes */
2142 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
2143 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2144 /* revert to mips rounding mode */
2145 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
2154 } while (xcp->cp0_epc > prevepc);
2156 /* SIGILL indicates a non-fpu instruction */
2157 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2158 /* but if epc has advanced, then ignore it */
2164 #ifdef CONFIG_DEBUG_FS
2166 static int fpuemu_stat_get(void *data, u64 *val)
2169 unsigned long sum = 0;
2170 for_each_online_cpu(cpu) {
2171 struct mips_fpu_emulator_stats *ps;
2173 ps = &per_cpu(fpuemustats, cpu);
2174 pv = (void *)ps + (unsigned long)data;
2175 sum += local_read(pv);
2180 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2182 extern struct dentry *mips_debugfs_dir;
2183 static int __init debugfs_fpuemu(void)
2185 struct dentry *d, *dir;
2187 if (!mips_debugfs_dir)
2189 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
2193 #define FPU_STAT_CREATE(M) \
2195 d = debugfs_create_file(#M , S_IRUGO, dir, \
2196 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2197 &fops_fpuemu_stat); \
2202 FPU_STAT_CREATE(emulated);
2203 FPU_STAT_CREATE(loads);
2204 FPU_STAT_CREATE(stores);
2205 FPU_STAT_CREATE(cp1ops);
2206 FPU_STAT_CREATE(cp1xops);
2207 FPU_STAT_CREATE(errors);
2211 __initcall(debugfs_fpuemu);