2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
52 #include <asm/mips-r2-to-r6-emul.h>
56 /* Function which emulates a floating point instruction. */
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
64 /* Control registers */
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
101 switch (insn.mm_i_format.opcode) {
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
134 switch (insn.mm_fp0_format.func) {
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
146 else if (op == mm_32f_11_op)
148 else if (op == mm_32f_02_op)
150 else if (op == mm_32f_12_op)
152 else if (op == mm_32f_41_op)
154 else if (op == mm_32f_51_op)
156 else if (op == mm_32f_42_op)
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
172 else if (op == mm_sdxc1_op)
174 else if (op == mm_lwxc1_op)
176 else if (op == mm_swxc1_op)
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
261 if ((insn.mm_fp1_format.op & 0x7f) ==
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
278 if ((insn.mm_fp1_format.op & 0x7f) ==
281 fmt = swl_format[insn.mm_fp3_format.fmt];
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
301 if ((insn.mm_fp1_format.op & 0x7f) ==
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
427 *insn_ptr = mips32_insn;
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
442 unsigned int bit = 0;
444 switch (insn.i_format.opcode) {
446 switch (insn.r_format.func) {
448 regs->regs[insn.r_format.rd] =
449 regs->cp0_epc + dec_insn.pc_inc +
450 dec_insn.next_pc_inc;
453 /* For R6, JR already emulated in jalr_op */
454 if (NO_R6EMU && insn.r_format.func == jr_op)
456 *contpc = regs->regs[insn.r_format.rs];
461 switch (insn.i_format.rt) {
464 if (NO_R6EMU && (insn.i_format.rs ||
465 insn.i_format.rt == bltzall_op))
468 regs->regs[31] = regs->cp0_epc +
470 dec_insn.next_pc_inc;
476 if ((long)regs->regs[insn.i_format.rs] < 0)
477 *contpc = regs->cp0_epc +
479 (insn.i_format.simmediate << 2);
481 *contpc = regs->cp0_epc +
483 dec_insn.next_pc_inc;
487 if (NO_R6EMU && (insn.i_format.rs ||
488 insn.i_format.rt == bgezall_op))
491 regs->regs[31] = regs->cp0_epc +
493 dec_insn.next_pc_inc;
499 if ((long)regs->regs[insn.i_format.rs] >= 0)
500 *contpc = regs->cp0_epc +
502 (insn.i_format.simmediate << 2);
504 *contpc = regs->cp0_epc +
506 dec_insn.next_pc_inc;
513 regs->regs[31] = regs->cp0_epc +
515 dec_insn.next_pc_inc;
518 *contpc = regs->cp0_epc + dec_insn.pc_inc;
521 *contpc |= (insn.j_format.target << 2);
522 /* Set microMIPS mode bit: XOR for jalx. */
529 if (regs->regs[insn.i_format.rs] ==
530 regs->regs[insn.i_format.rt])
531 *contpc = regs->cp0_epc +
533 (insn.i_format.simmediate << 2);
535 *contpc = regs->cp0_epc +
537 dec_insn.next_pc_inc;
543 if (regs->regs[insn.i_format.rs] !=
544 regs->regs[insn.i_format.rt])
545 *contpc = regs->cp0_epc +
547 (insn.i_format.simmediate << 2);
549 *contpc = regs->cp0_epc +
551 dec_insn.next_pc_inc;
554 if (!insn.i_format.rt && NO_R6EMU)
559 * Compact branches for R6 for the
560 * blez and blezl opcodes.
561 * BLEZ | rs = 0 | rt != 0 == BLEZALC
562 * BLEZ | rs = rt != 0 == BGEZALC
563 * BLEZ | rs != 0 | rt != 0 == BGEUC
564 * BLEZL | rs = 0 | rt != 0 == BLEZC
565 * BLEZL | rs = rt != 0 == BGEZC
566 * BLEZL | rs != 0 | rt != 0 == BGEC
568 * For real BLEZ{,L}, rt is always 0.
570 if (cpu_has_mips_r6 && insn.i_format.rt) {
571 if ((insn.i_format.opcode == blez_op) &&
572 ((!insn.i_format.rs && insn.i_format.rt) ||
573 (insn.i_format.rs == insn.i_format.rt)))
574 regs->regs[31] = regs->cp0_epc +
576 *contpc = regs->cp0_epc + dec_insn.pc_inc +
577 dec_insn.next_pc_inc;
581 if ((long)regs->regs[insn.i_format.rs] <= 0)
582 *contpc = regs->cp0_epc +
584 (insn.i_format.simmediate << 2);
586 *contpc = regs->cp0_epc +
588 dec_insn.next_pc_inc;
591 if (!insn.i_format.rt && NO_R6EMU)
595 * Compact branches for R6 for the
596 * bgtz and bgtzl opcodes.
597 * BGTZ | rs = 0 | rt != 0 == BGTZALC
598 * BGTZ | rs = rt != 0 == BLTZALC
599 * BGTZ | rs != 0 | rt != 0 == BLTUC
600 * BGTZL | rs = 0 | rt != 0 == BGTZC
601 * BGTZL | rs = rt != 0 == BLTZC
602 * BGTZL | rs != 0 | rt != 0 == BLTC
604 * *ZALC varint for BGTZ &&& rt != 0
605 * For real GTZ{,L}, rt is always 0.
607 if (cpu_has_mips_r6 && insn.i_format.rt) {
608 if ((insn.i_format.opcode == blez_op) &&
609 ((!insn.i_format.rs && insn.i_format.rt) ||
610 (insn.i_format.rs == insn.i_format.rt)))
611 regs->regs[31] = regs->cp0_epc +
613 *contpc = regs->cp0_epc + dec_insn.pc_inc +
614 dec_insn.next_pc_inc;
619 if ((long)regs->regs[insn.i_format.rs] > 0)
620 *contpc = regs->cp0_epc +
622 (insn.i_format.simmediate << 2);
624 *contpc = regs->cp0_epc +
626 dec_insn.next_pc_inc;
630 if (!cpu_has_mips_r6)
632 if (insn.i_format.rt && !insn.i_format.rs)
633 regs->regs[31] = regs->cp0_epc + 4;
634 *contpc = regs->cp0_epc + dec_insn.pc_inc +
635 dec_insn.next_pc_inc;
638 #ifdef CONFIG_CPU_CAVIUM_OCTEON
639 case lwc2_op: /* This is bbit0 on Octeon */
640 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
641 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
643 *contpc = regs->cp0_epc + 8;
645 case ldc2_op: /* This is bbit032 on Octeon */
646 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
647 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
649 *contpc = regs->cp0_epc + 8;
651 case swc2_op: /* This is bbit1 on Octeon */
652 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
653 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
655 *contpc = regs->cp0_epc + 8;
657 case sdc2_op: /* This is bbit132 on Octeon */
658 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
659 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
661 *contpc = regs->cp0_epc + 8;
666 * Only valid for MIPS R6 but we can still end up
667 * here from a broken userland so just tell emulator
668 * this is not a branch and let it break later on.
670 if (!cpu_has_mips_r6)
672 *contpc = regs->cp0_epc + dec_insn.pc_inc +
673 dec_insn.next_pc_inc;
677 if (!cpu_has_mips_r6)
679 regs->regs[31] = regs->cp0_epc + 4;
680 *contpc = regs->cp0_epc + dec_insn.pc_inc +
681 dec_insn.next_pc_inc;
685 if (!cpu_has_mips_r6)
687 *contpc = regs->cp0_epc + dec_insn.pc_inc +
688 dec_insn.next_pc_inc;
692 if (!cpu_has_mips_r6)
694 if (!insn.i_format.rs)
695 regs->regs[31] = regs->cp0_epc + 4;
696 *contpc = regs->cp0_epc + dec_insn.pc_inc +
697 dec_insn.next_pc_inc;
703 /* Need to check for R6 bc1nez and bc1eqz branches */
704 if (cpu_has_mips_r6 &&
705 ((insn.i_format.rs == bc1eqz_op) ||
706 (insn.i_format.rs == bc1nez_op))) {
708 switch (insn.i_format.rs) {
710 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
714 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
719 *contpc = regs->cp0_epc +
721 (insn.i_format.simmediate << 2);
723 *contpc = regs->cp0_epc +
725 dec_insn.next_pc_inc;
729 /* R2/R6 compatible cop1 instruction. Fall through */
732 if (insn.i_format.rs == bc_op) {
735 fcr31 = read_32bit_cp1_register(CP1_STATUS);
737 fcr31 = current->thread.fpu.fcr31;
740 bit = (insn.i_format.rt >> 2);
743 switch (insn.i_format.rt & 3) {
746 if (~fcr31 & (1 << bit))
747 *contpc = regs->cp0_epc +
749 (insn.i_format.simmediate << 2);
751 *contpc = regs->cp0_epc +
753 dec_insn.next_pc_inc;
757 if (fcr31 & (1 << bit))
758 *contpc = regs->cp0_epc +
760 (insn.i_format.simmediate << 2);
762 *contpc = regs->cp0_epc +
764 dec_insn.next_pc_inc;
774 * In the Linux kernel, we support selection of FPR format on the
775 * basis of the Status.FR bit. If an FPU is not present, the FR bit
776 * is hardwired to zero, which would imply a 32-bit FPU even for
777 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
778 * FPU emu is slow and bulky and optimizing this function offers fairly
779 * sizeable benefits so we try to be clever and make this function return
780 * a constant whenever possible, that is on 64-bit kernels without O32
781 * compatibility enabled and on 32-bit without 64-bit FPU support.
783 static inline int cop1_64bit(struct pt_regs *xcp)
785 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
787 else if (config_enabled(CONFIG_32BIT) &&
788 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
791 return !test_thread_flag(TIF_32BIT_FPREGS);
794 static inline bool hybrid_fprs(void)
796 return test_thread_flag(TIF_HYBRID_FPREGS);
799 #define SIFROMREG(si, x) \
801 if (cop1_64bit(xcp) && !hybrid_fprs()) \
802 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
804 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
807 #define SITOREG(si, x) \
809 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
811 set_fpr32(&ctx->fpr[x], 0, si); \
812 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
813 set_fpr32(&ctx->fpr[x], i, 0); \
815 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
819 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
821 #define SITOHREG(si, x) \
824 set_fpr32(&ctx->fpr[x], 1, si); \
825 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
826 set_fpr32(&ctx->fpr[x], i, 0); \
829 #define DIFROMREG(di, x) \
830 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
832 #define DITOREG(di, x) \
835 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
836 set_fpr64(&ctx->fpr[fpr], 0, di); \
837 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
838 set_fpr64(&ctx->fpr[fpr], i, 0); \
841 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
842 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
843 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
844 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
847 * Emulate a CFC1 instruction.
849 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
852 u32 fcr31 = ctx->fcr31;
855 switch (MIPSInst_RD(ir)) {
858 pr_debug("%p gpr[%d]<-csr=%08x\n",
859 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
865 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
867 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
868 pr_debug("%p gpr[%d]<-enr=%08x\n",
869 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
875 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
876 pr_debug("%p gpr[%d]<-exr=%08x\n",
877 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
883 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
885 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
886 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
887 pr_debug("%p gpr[%d]<-ccr=%08x\n",
888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
892 value = boot_cpu_data.fpu_id;
900 xcp->regs[MIPSInst_RT(ir)] = value;
904 * Emulate a CTC1 instruction.
906 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
909 u32 fcr31 = ctx->fcr31;
913 if (MIPSInst_RT(ir) == 0)
916 value = xcp->regs[MIPSInst_RT(ir)];
918 switch (MIPSInst_RD(ir)) {
920 pr_debug("%p gpr[%d]->csr=%08x\n",
921 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
923 /* Preserve read-only bits. */
924 mask = boot_cpu_data.fpu_msk31;
925 fcr31 = (value & ~mask) | (fcr31 & mask);
931 pr_debug("%p gpr[%d]->enr=%08x\n",
932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
933 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
934 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
936 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
942 pr_debug("%p gpr[%d]->exr=%08x\n",
943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
944 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
945 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
951 pr_debug("%p gpr[%d]->ccr=%08x\n",
952 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
953 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
954 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
956 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
968 * Emulate the single floating point instruction pointed at by EPC.
969 * Two instructions if the instruction is in a branch delay slot.
972 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
973 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
975 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
976 unsigned int cond, cbit;
986 * These are giving gcc a gentle hint about what to expect in
987 * dec_inst in order to do better optimization.
989 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
992 /* XXX NEC Vr54xx bug workaround */
993 if (delay_slot(xcp)) {
994 if (dec_insn.micro_mips_mode) {
995 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
996 clear_delay_slot(xcp);
998 if (!isBranchInstr(xcp, dec_insn, &contpc))
999 clear_delay_slot(xcp);
1003 if (delay_slot(xcp)) {
1005 * The instruction to be emulated is in a branch delay slot
1006 * which means that we have to emulate the branch instruction
1007 * BEFORE we do the cop1 instruction.
1009 * This branch could be a COP1 branch, but in that case we
1010 * would have had a trap for that instruction, and would not
1011 * come through this route.
1013 * Linux MIPS branch emulator operates on context, updating the
1016 ir = dec_insn.next_insn; /* process delay slot instr */
1017 pc_inc = dec_insn.next_pc_inc;
1019 ir = dec_insn.insn; /* process current instr */
1020 pc_inc = dec_insn.pc_inc;
1024 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1025 * instructions, we want to convert microMIPS FPU instructions
1026 * into MIPS32 instructions so that we could reuse all of the
1027 * FPU emulation code.
1029 * NOTE: We cannot do this for branch instructions since they
1030 * are not a subset. Example: Cannot emulate a 16-bit
1031 * aligned target address with a MIPS32 instruction.
1033 if (dec_insn.micro_mips_mode) {
1035 * If next instruction is a 16-bit instruction, then it
1036 * it cannot be a FPU instruction. This could happen
1037 * since we can be called for non-FPU instructions.
1039 if ((pc_inc == 2) ||
1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1046 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1047 MIPS_FPU_EMU_INC_STATS(emulated);
1048 switch (MIPSInst_OPCODE(ir)) {
1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1052 MIPS_FPU_EMU_INC_STATS(loads);
1054 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1055 MIPS_FPU_EMU_INC_STATS(errors);
1059 if (__get_user(dval, dva)) {
1060 MIPS_FPU_EMU_INC_STATS(errors);
1064 DITOREG(dval, MIPSInst_RT(ir));
1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1070 MIPS_FPU_EMU_INC_STATS(stores);
1071 DIFROMREG(dval, MIPSInst_RT(ir));
1072 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1073 MIPS_FPU_EMU_INC_STATS(errors);
1077 if (__put_user(dval, dva)) {
1078 MIPS_FPU_EMU_INC_STATS(errors);
1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1087 MIPS_FPU_EMU_INC_STATS(loads);
1088 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1089 MIPS_FPU_EMU_INC_STATS(errors);
1093 if (__get_user(wval, wva)) {
1094 MIPS_FPU_EMU_INC_STATS(errors);
1098 SITOREG(wval, MIPSInst_RT(ir));
1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1104 MIPS_FPU_EMU_INC_STATS(stores);
1105 SIFROMREG(wval, MIPSInst_RT(ir));
1106 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1107 MIPS_FPU_EMU_INC_STATS(errors);
1111 if (__put_user(wval, wva)) {
1112 MIPS_FPU_EMU_INC_STATS(errors);
1119 switch (MIPSInst_RS(ir)) {
1121 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1124 /* copregister fs -> gpr[rt] */
1125 if (MIPSInst_RT(ir) != 0) {
1126 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1132 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1135 /* copregister fs <- rt */
1136 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1140 if (!cpu_has_mips_r2_r6)
1143 /* copregister rd -> gpr[rt] */
1144 if (MIPSInst_RT(ir) != 0) {
1145 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1151 if (!cpu_has_mips_r2_r6)
1154 /* copregister rd <- gpr[rt] */
1155 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1159 /* copregister rd -> gpr[rt] */
1160 if (MIPSInst_RT(ir) != 0) {
1161 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1167 /* copregister rd <- rt */
1168 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1172 /* cop control register rd -> gpr[rt] */
1173 cop1_cfc(xcp, ctx, ir);
1177 /* copregister rd <- rt */
1178 cop1_ctc(xcp, ctx, ir);
1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1186 if (!cpu_has_mips_r6 || delay_slot(xcp))
1190 switch (MIPSInst_RS(ir)) {
1192 if (get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1196 if (!(get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1203 if (delay_slot(xcp))
1206 if (cpu_has_mips_4_5_r)
1207 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1209 cbit = FPU_CSR_COND;
1210 cond = ctx->fcr31 & cbit;
1213 switch (MIPSInst_RT(ir) & 3) {
1215 if (cpu_has_mips_2_3_4_5_r)
1222 if (cpu_has_mips_2_3_4_5_r)
1229 set_delay_slot(xcp);
1232 * Branch taken: emulate dslot instruction
1237 * Remember EPC at the branch to point back
1238 * at so that any delay-slot instruction
1239 * signal is not silently ignored.
1241 bcpc = xcp->cp0_epc;
1242 xcp->cp0_epc += dec_insn.pc_inc;
1244 contpc = MIPSInst_SIMM(ir);
1245 ir = dec_insn.next_insn;
1246 if (dec_insn.micro_mips_mode) {
1247 contpc = (xcp->cp0_epc + (contpc << 1));
1249 /* If 16-bit instruction, not FPU. */
1250 if ((dec_insn.next_pc_inc == 2) ||
1251 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1254 * Since this instruction will
1255 * be put on the stack with
1256 * 32-bit words, get around
1257 * this problem by putting a
1258 * NOP16 as the second one.
1260 if (dec_insn.next_pc_inc == 2)
1261 ir = (ir & (~0xffff)) | MM_NOP16;
1264 * Single step the non-CP1
1265 * instruction in the dslot.
1267 sig = mips_dsemul(xcp, ir,
1270 xcp->cp0_epc = bcpc;
1272 * SIGILL forces out of
1273 * the emulation loop.
1275 return sig ? sig : SIGILL;
1278 contpc = (xcp->cp0_epc + (contpc << 2));
1280 switch (MIPSInst_OPCODE(ir)) {
1287 if (cpu_has_mips_2_3_4_5_r)
1296 if (cpu_has_mips_4_5_64_r2_r6)
1297 /* its one of ours */
1303 switch (MIPSInst_FUNC(ir)) {
1305 if (cpu_has_mips_4_5_r)
1313 xcp->cp0_epc = bcpc;
1318 * Single step the non-cp1
1319 * instruction in the dslot
1321 sig = mips_dsemul(xcp, ir, contpc);
1323 xcp->cp0_epc = bcpc;
1324 /* SIGILL forces out of the emulation loop. */
1325 return sig ? sig : SIGILL;
1326 } else if (likely) { /* branch not taken */
1328 * branch likely nullifies
1329 * dslot if not taken
1331 xcp->cp0_epc += dec_insn.pc_inc;
1332 contpc += dec_insn.pc_inc;
1334 * else continue & execute
1335 * dslot as normal insn
1341 if (!(MIPSInst_RS(ir) & 0x10))
1344 /* a real fpu computation instruction */
1345 if ((sig = fpu_emu(xcp, ctx, ir)))
1351 if (!cpu_has_mips_4_5_64_r2_r6)
1354 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1360 if (!cpu_has_mips_4_5_r)
1363 if (MIPSInst_FUNC(ir) != movc_op)
1365 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1366 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1367 xcp->regs[MIPSInst_RD(ir)] =
1368 xcp->regs[MIPSInst_RS(ir)];
1376 xcp->cp0_epc = contpc;
1377 clear_delay_slot(xcp);
1383 * Conversion table from MIPS compare ops 48-63
1384 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1386 static const unsigned char cmptab[8] = {
1387 0, /* cmp_0 (sig) cmp_sf */
1388 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1389 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1390 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1391 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1392 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1393 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1394 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1397 static const unsigned char negative_cmptab[8] = {
1399 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1400 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1401 IEEE754_CLT | IEEE754_CGT,
1407 * Additional MIPS4 instructions
1410 #define DEF3OP(name, p, f1, f2, f3) \
1411 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1412 union ieee754##p s, union ieee754##p t) \
1414 struct _ieee754_csr ieee754_csr_save; \
1416 ieee754_csr_save = ieee754_csr; \
1418 ieee754_csr_save.cx |= ieee754_csr.cx; \
1419 ieee754_csr_save.sx |= ieee754_csr.sx; \
1421 ieee754_csr.cx |= ieee754_csr_save.cx; \
1422 ieee754_csr.sx |= ieee754_csr_save.sx; \
1426 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1428 return ieee754dp_div(ieee754dp_one(0), d);
1431 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1433 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1436 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1438 return ieee754sp_div(ieee754sp_one(0), s);
1441 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1443 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1446 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1447 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1448 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1449 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1450 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1451 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1452 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1453 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1455 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1456 mips_instruction ir, void *__user *fault_addr)
1458 unsigned rcsr = 0; /* resulting csr */
1460 MIPS_FPU_EMU_INC_STATS(cp1xops);
1462 switch (MIPSInst_FMA_FFMT(ir)) {
1463 case s_fmt:{ /* 0 */
1465 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1466 union ieee754sp fd, fr, fs, ft;
1470 switch (MIPSInst_FUNC(ir)) {
1472 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1473 xcp->regs[MIPSInst_FT(ir)]);
1475 MIPS_FPU_EMU_INC_STATS(loads);
1476 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1477 MIPS_FPU_EMU_INC_STATS(errors);
1481 if (__get_user(val, va)) {
1482 MIPS_FPU_EMU_INC_STATS(errors);
1486 SITOREG(val, MIPSInst_FD(ir));
1490 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1491 xcp->regs[MIPSInst_FT(ir)]);
1493 MIPS_FPU_EMU_INC_STATS(stores);
1495 SIFROMREG(val, MIPSInst_FS(ir));
1496 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1497 MIPS_FPU_EMU_INC_STATS(errors);
1501 if (put_user(val, va)) {
1502 MIPS_FPU_EMU_INC_STATS(errors);
1509 handler = fpemu_sp_madd;
1512 handler = fpemu_sp_msub;
1515 handler = fpemu_sp_nmadd;
1518 handler = fpemu_sp_nmsub;
1522 SPFROMREG(fr, MIPSInst_FR(ir));
1523 SPFROMREG(fs, MIPSInst_FS(ir));
1524 SPFROMREG(ft, MIPSInst_FT(ir));
1525 fd = (*handler) (fr, fs, ft);
1526 SPTOREG(fd, MIPSInst_FD(ir));
1529 if (ieee754_cxtest(IEEE754_INEXACT)) {
1530 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1531 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1533 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1534 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1535 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1537 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1538 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1539 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1541 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1542 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1543 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1546 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1547 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1548 /*printk ("SIGFPE: FPU csr = %08x\n",
1561 case d_fmt:{ /* 1 */
1562 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1563 union ieee754dp fd, fr, fs, ft;
1567 switch (MIPSInst_FUNC(ir)) {
1569 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1570 xcp->regs[MIPSInst_FT(ir)]);
1572 MIPS_FPU_EMU_INC_STATS(loads);
1573 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1574 MIPS_FPU_EMU_INC_STATS(errors);
1578 if (__get_user(val, va)) {
1579 MIPS_FPU_EMU_INC_STATS(errors);
1583 DITOREG(val, MIPSInst_FD(ir));
1587 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1588 xcp->regs[MIPSInst_FT(ir)]);
1590 MIPS_FPU_EMU_INC_STATS(stores);
1591 DIFROMREG(val, MIPSInst_FS(ir));
1592 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1593 MIPS_FPU_EMU_INC_STATS(errors);
1597 if (__put_user(val, va)) {
1598 MIPS_FPU_EMU_INC_STATS(errors);
1605 handler = fpemu_dp_madd;
1608 handler = fpemu_dp_msub;
1611 handler = fpemu_dp_nmadd;
1614 handler = fpemu_dp_nmsub;
1618 DPFROMREG(fr, MIPSInst_FR(ir));
1619 DPFROMREG(fs, MIPSInst_FS(ir));
1620 DPFROMREG(ft, MIPSInst_FT(ir));
1621 fd = (*handler) (fr, fs, ft);
1622 DPTOREG(fd, MIPSInst_FD(ir));
1632 if (MIPSInst_FUNC(ir) != pfetch_op)
1635 /* ignore prefx operation */
1648 * Emulate a single COP1 arithmetic instruction.
1650 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1651 mips_instruction ir)
1653 int rfmt; /* resulting format */
1654 unsigned rcsr = 0; /* resulting csr */
1663 } rv; /* resulting value */
1666 MIPS_FPU_EMU_INC_STATS(cp1ops);
1667 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1668 case s_fmt: { /* 0 */
1670 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1671 union ieee754sp(*u) (union ieee754sp);
1673 union ieee754sp fs, ft;
1675 switch (MIPSInst_FUNC(ir)) {
1678 handler.b = ieee754sp_add;
1681 handler.b = ieee754sp_sub;
1684 handler.b = ieee754sp_mul;
1687 handler.b = ieee754sp_div;
1692 if (!cpu_has_mips_2_3_4_5_r)
1695 handler.u = ieee754sp_sqrt;
1699 * Note that on some MIPS IV implementations such as the
1700 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1701 * achieve full IEEE-754 accuracy - however this emulator does.
1704 if (!cpu_has_mips_4_5_64_r2_r6)
1707 handler.u = fpemu_sp_rsqrt;
1711 if (!cpu_has_mips_4_5_64_r2_r6)
1714 handler.u = fpemu_sp_recip;
1718 if (!cpu_has_mips_4_5_r)
1721 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1722 if (((ctx->fcr31 & cond) != 0) !=
1723 ((MIPSInst_FT(ir) & 1) != 0))
1725 SPFROMREG(rv.s, MIPSInst_FS(ir));
1729 if (!cpu_has_mips_4_5_r)
1732 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1734 SPFROMREG(rv.s, MIPSInst_FS(ir));
1738 if (!cpu_has_mips_4_5_r)
1741 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1743 SPFROMREG(rv.s, MIPSInst_FS(ir));
1747 if (!cpu_has_mips_r6)
1750 SPFROMREG(rv.s, MIPSInst_FT(ir));
1754 SPFROMREG(rv.s, MIPSInst_FS(ir));
1758 if (!cpu_has_mips_r6)
1761 SPFROMREG(rv.s, MIPSInst_FT(ir));
1763 SPFROMREG(rv.s, MIPSInst_FS(ir));
1769 union ieee754sp ft, fs, fd;
1771 if (!cpu_has_mips_r6)
1774 SPFROMREG(ft, MIPSInst_FT(ir));
1775 SPFROMREG(fs, MIPSInst_FS(ir));
1776 SPFROMREG(fd, MIPSInst_FD(ir));
1777 rv.s = ieee754sp_maddf(fd, fs, ft);
1782 union ieee754sp ft, fs, fd;
1784 if (!cpu_has_mips_r6)
1787 SPFROMREG(ft, MIPSInst_FT(ir));
1788 SPFROMREG(fs, MIPSInst_FS(ir));
1789 SPFROMREG(fd, MIPSInst_FD(ir));
1790 rv.s = ieee754sp_msubf(fd, fs, ft);
1797 if (!cpu_has_mips_r6)
1800 SPFROMREG(fs, MIPSInst_FS(ir));
1801 rv.l = ieee754sp_tlong(fs);
1802 rv.s = ieee754sp_flong(rv.l);
1809 if (!cpu_has_mips_r6)
1812 SPFROMREG(fs, MIPSInst_FS(ir));
1813 rv.w = ieee754sp_2008class(fs);
1819 union ieee754sp fs, ft;
1821 if (!cpu_has_mips_r6)
1824 SPFROMREG(ft, MIPSInst_FT(ir));
1825 SPFROMREG(fs, MIPSInst_FS(ir));
1826 rv.s = ieee754sp_fmin(fs, ft);
1831 union ieee754sp fs, ft;
1833 if (!cpu_has_mips_r6)
1836 SPFROMREG(ft, MIPSInst_FT(ir));
1837 SPFROMREG(fs, MIPSInst_FS(ir));
1838 rv.s = ieee754sp_fmina(fs, ft);
1843 union ieee754sp fs, ft;
1845 if (!cpu_has_mips_r6)
1848 SPFROMREG(ft, MIPSInst_FT(ir));
1849 SPFROMREG(fs, MIPSInst_FS(ir));
1850 rv.s = ieee754sp_fmax(fs, ft);
1855 union ieee754sp fs, ft;
1857 if (!cpu_has_mips_r6)
1860 SPFROMREG(ft, MIPSInst_FT(ir));
1861 SPFROMREG(fs, MIPSInst_FS(ir));
1862 rv.s = ieee754sp_fmaxa(fs, ft);
1867 handler.u = ieee754sp_abs;
1871 handler.u = ieee754sp_neg;
1876 SPFROMREG(rv.s, MIPSInst_FS(ir));
1879 /* binary op on handler */
1881 SPFROMREG(fs, MIPSInst_FS(ir));
1882 SPFROMREG(ft, MIPSInst_FT(ir));
1884 rv.s = (*handler.b) (fs, ft);
1887 SPFROMREG(fs, MIPSInst_FS(ir));
1888 rv.s = (*handler.u) (fs);
1891 if (ieee754_cxtest(IEEE754_INEXACT)) {
1892 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1893 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1895 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1896 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1897 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1899 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1900 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1901 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1903 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1904 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1905 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1907 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1908 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1909 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1913 /* unary conv ops */
1915 return SIGILL; /* not defined */
1918 SPFROMREG(fs, MIPSInst_FS(ir));
1919 rv.d = ieee754dp_fsp(fs);
1924 SPFROMREG(fs, MIPSInst_FS(ir));
1925 rv.w = ieee754sp_tint(fs);
1933 if (!cpu_has_mips_2_3_4_5_r)
1936 oldrm = ieee754_csr.rm;
1937 SPFROMREG(fs, MIPSInst_FS(ir));
1938 ieee754_csr.rm = MIPSInst_FUNC(ir);
1939 rv.w = ieee754sp_tint(fs);
1940 ieee754_csr.rm = oldrm;
1945 if (!cpu_has_mips_3_4_5_64_r2_r6)
1948 SPFROMREG(fs, MIPSInst_FS(ir));
1949 rv.l = ieee754sp_tlong(fs);
1957 if (!cpu_has_mips_3_4_5_64_r2_r6)
1960 oldrm = ieee754_csr.rm;
1961 SPFROMREG(fs, MIPSInst_FS(ir));
1962 ieee754_csr.rm = MIPSInst_FUNC(ir);
1963 rv.l = ieee754sp_tlong(fs);
1964 ieee754_csr.rm = oldrm;
1969 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1970 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1971 union ieee754sp fs, ft;
1973 SPFROMREG(fs, MIPSInst_FS(ir));
1974 SPFROMREG(ft, MIPSInst_FT(ir));
1975 rv.w = ieee754sp_cmp(fs, ft,
1976 cmptab[cmpop & 0x7], cmpop & 0x8);
1978 if ((cmpop & 0x8) && ieee754_cxtest
1979 (IEEE754_INVALID_OPERATION))
1980 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1992 union ieee754dp fs, ft;
1994 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1995 union ieee754dp(*u) (union ieee754dp);
1998 switch (MIPSInst_FUNC(ir)) {
2001 handler.b = ieee754dp_add;
2004 handler.b = ieee754dp_sub;
2007 handler.b = ieee754dp_mul;
2010 handler.b = ieee754dp_div;
2015 if (!cpu_has_mips_2_3_4_5_r)
2018 handler.u = ieee754dp_sqrt;
2021 * Note that on some MIPS IV implementations such as the
2022 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2023 * achieve full IEEE-754 accuracy - however this emulator does.
2026 if (!cpu_has_mips_4_5_64_r2_r6)
2029 handler.u = fpemu_dp_rsqrt;
2032 if (!cpu_has_mips_4_5_64_r2_r6)
2035 handler.u = fpemu_dp_recip;
2038 if (!cpu_has_mips_4_5_r)
2041 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2042 if (((ctx->fcr31 & cond) != 0) !=
2043 ((MIPSInst_FT(ir) & 1) != 0))
2045 DPFROMREG(rv.d, MIPSInst_FS(ir));
2048 if (!cpu_has_mips_4_5_r)
2051 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2053 DPFROMREG(rv.d, MIPSInst_FS(ir));
2056 if (!cpu_has_mips_4_5_r)
2059 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2061 DPFROMREG(rv.d, MIPSInst_FS(ir));
2065 if (!cpu_has_mips_r6)
2068 DPFROMREG(rv.d, MIPSInst_FT(ir));
2072 DPFROMREG(rv.d, MIPSInst_FS(ir));
2076 if (!cpu_has_mips_r6)
2079 DPFROMREG(rv.d, MIPSInst_FT(ir));
2081 DPFROMREG(rv.d, MIPSInst_FS(ir));
2087 union ieee754dp ft, fs, fd;
2089 if (!cpu_has_mips_r6)
2092 DPFROMREG(ft, MIPSInst_FT(ir));
2093 DPFROMREG(fs, MIPSInst_FS(ir));
2094 DPFROMREG(fd, MIPSInst_FD(ir));
2095 rv.d = ieee754dp_maddf(fd, fs, ft);
2100 union ieee754dp ft, fs, fd;
2102 if (!cpu_has_mips_r6)
2105 DPFROMREG(ft, MIPSInst_FT(ir));
2106 DPFROMREG(fs, MIPSInst_FS(ir));
2107 DPFROMREG(fd, MIPSInst_FD(ir));
2108 rv.d = ieee754dp_msubf(fd, fs, ft);
2115 if (!cpu_has_mips_r6)
2118 DPFROMREG(fs, MIPSInst_FS(ir));
2119 rv.l = ieee754dp_tlong(fs);
2120 rv.d = ieee754dp_flong(rv.l);
2127 if (!cpu_has_mips_r6)
2130 DPFROMREG(fs, MIPSInst_FS(ir));
2131 rv.w = ieee754dp_2008class(fs);
2137 union ieee754dp fs, ft;
2139 if (!cpu_has_mips_r6)
2142 DPFROMREG(ft, MIPSInst_FT(ir));
2143 DPFROMREG(fs, MIPSInst_FS(ir));
2144 rv.d = ieee754dp_fmin(fs, ft);
2149 union ieee754dp fs, ft;
2151 if (!cpu_has_mips_r6)
2154 DPFROMREG(ft, MIPSInst_FT(ir));
2155 DPFROMREG(fs, MIPSInst_FS(ir));
2156 rv.d = ieee754dp_fmina(fs, ft);
2161 union ieee754dp fs, ft;
2163 if (!cpu_has_mips_r6)
2166 DPFROMREG(ft, MIPSInst_FT(ir));
2167 DPFROMREG(fs, MIPSInst_FS(ir));
2168 rv.d = ieee754dp_fmax(fs, ft);
2173 union ieee754dp fs, ft;
2175 if (!cpu_has_mips_r6)
2178 DPFROMREG(ft, MIPSInst_FT(ir));
2179 DPFROMREG(fs, MIPSInst_FS(ir));
2180 rv.d = ieee754dp_fmaxa(fs, ft);
2185 handler.u = ieee754dp_abs;
2189 handler.u = ieee754dp_neg;
2194 DPFROMREG(rv.d, MIPSInst_FS(ir));
2197 /* binary op on handler */
2199 DPFROMREG(fs, MIPSInst_FS(ir));
2200 DPFROMREG(ft, MIPSInst_FT(ir));
2202 rv.d = (*handler.b) (fs, ft);
2205 DPFROMREG(fs, MIPSInst_FS(ir));
2206 rv.d = (*handler.u) (fs);
2213 DPFROMREG(fs, MIPSInst_FS(ir));
2214 rv.s = ieee754sp_fdp(fs);
2219 return SIGILL; /* not defined */
2222 DPFROMREG(fs, MIPSInst_FS(ir));
2223 rv.w = ieee754dp_tint(fs); /* wrong */
2231 if (!cpu_has_mips_2_3_4_5_r)
2234 oldrm = ieee754_csr.rm;
2235 DPFROMREG(fs, MIPSInst_FS(ir));
2236 ieee754_csr.rm = MIPSInst_FUNC(ir);
2237 rv.w = ieee754dp_tint(fs);
2238 ieee754_csr.rm = oldrm;
2243 if (!cpu_has_mips_3_4_5_64_r2_r6)
2246 DPFROMREG(fs, MIPSInst_FS(ir));
2247 rv.l = ieee754dp_tlong(fs);
2255 if (!cpu_has_mips_3_4_5_64_r2_r6)
2258 oldrm = ieee754_csr.rm;
2259 DPFROMREG(fs, MIPSInst_FS(ir));
2260 ieee754_csr.rm = MIPSInst_FUNC(ir);
2261 rv.l = ieee754dp_tlong(fs);
2262 ieee754_csr.rm = oldrm;
2267 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2268 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2269 union ieee754dp fs, ft;
2271 DPFROMREG(fs, MIPSInst_FS(ir));
2272 DPFROMREG(ft, MIPSInst_FT(ir));
2273 rv.w = ieee754dp_cmp(fs, ft,
2274 cmptab[cmpop & 0x7], cmpop & 0x8);
2279 (IEEE754_INVALID_OPERATION))
2280 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2296 switch (MIPSInst_FUNC(ir)) {
2298 /* convert word to single precision real */
2299 SPFROMREG(fs, MIPSInst_FS(ir));
2300 rv.s = ieee754sp_fint(fs.bits);
2304 /* convert word to double precision real */
2305 SPFROMREG(fs, MIPSInst_FS(ir));
2306 rv.d = ieee754dp_fint(fs.bits);
2310 /* Emulating the new CMP.condn.fmt R6 instruction */
2311 #define CMPOP_MASK 0x7
2312 #define SIGN_BIT (0x1 << 3)
2313 #define PREDICATE_BIT (0x1 << 4)
2315 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2316 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2317 union ieee754sp fs, ft;
2319 /* This is an R6 only instruction */
2320 if (!cpu_has_mips_r6 ||
2321 (MIPSInst_FUNC(ir) & 0x20))
2324 /* fmt is w_fmt for single precision so fix it */
2326 /* default to false */
2330 SPFROMREG(fs, MIPSInst_FS(ir));
2331 SPFROMREG(ft, MIPSInst_FT(ir));
2333 /* positive predicates */
2334 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2335 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2337 rv.w = -1; /* true, all 1s */
2339 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2340 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2344 /* negative predicates */
2349 if (ieee754sp_cmp(fs, ft,
2350 negative_cmptab[cmpop],
2352 rv.w = -1; /* true, all 1s */
2354 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2355 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2360 /* Reserved R6 ops */
2361 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2372 if (!cpu_has_mips_3_4_5_64_r2_r6)
2375 DIFROMREG(bits, MIPSInst_FS(ir));
2377 switch (MIPSInst_FUNC(ir)) {
2379 /* convert long to single precision real */
2380 rv.s = ieee754sp_flong(bits);
2384 /* convert long to double precision real */
2385 rv.d = ieee754dp_flong(bits);
2389 /* Emulating the new CMP.condn.fmt R6 instruction */
2390 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2391 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2392 union ieee754dp fs, ft;
2394 if (!cpu_has_mips_r6 ||
2395 (MIPSInst_FUNC(ir) & 0x20))
2398 /* fmt is l_fmt for double precision so fix it */
2400 /* default to false */
2404 DPFROMREG(fs, MIPSInst_FS(ir));
2405 DPFROMREG(ft, MIPSInst_FT(ir));
2407 /* positive predicates */
2408 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2409 if (ieee754dp_cmp(fs, ft,
2410 cmptab[cmpop], sig))
2411 rv.l = -1LL; /* true, all 1s */
2413 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2414 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2418 /* negative predicates */
2423 if (ieee754dp_cmp(fs, ft,
2424 negative_cmptab[cmpop],
2426 rv.l = -1LL; /* true, all 1s */
2428 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2429 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2434 /* Reserved R6 ops */
2435 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2447 * Update the fpu CSR register for this operation.
2448 * If an exception is required, generate a tidy SIGFPE exception,
2449 * without updating the result register.
2450 * Note: cause exception bits do not accumulate, they are rewritten
2451 * for each op; only the flag/sticky bits accumulate.
2453 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2454 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2455 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2460 * Now we can safely write the result back to the register file.
2465 if (cpu_has_mips_4_5_r)
2466 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2468 cbit = FPU_CSR_COND;
2472 ctx->fcr31 &= ~cbit;
2476 DPTOREG(rv.d, MIPSInst_FD(ir));
2479 SPTOREG(rv.s, MIPSInst_FD(ir));
2482 SITOREG(rv.w, MIPSInst_FD(ir));
2485 if (!cpu_has_mips_3_4_5_64_r2_r6)
2488 DITOREG(rv.l, MIPSInst_FD(ir));
2497 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2498 int has_fpu, void *__user *fault_addr)
2500 unsigned long oldepc, prevepc;
2501 struct mm_decoded_insn dec_insn;
2506 oldepc = xcp->cp0_epc;
2508 prevepc = xcp->cp0_epc;
2510 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2512 * Get next 2 microMIPS instructions and convert them
2513 * into 32-bit instructions.
2515 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2516 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2517 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2518 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2519 MIPS_FPU_EMU_INC_STATS(errors);
2524 /* Get first instruction. */
2525 if (mm_insn_16bit(*instr_ptr)) {
2526 /* Duplicate the half-word. */
2527 dec_insn.insn = (*instr_ptr << 16) |
2529 /* 16-bit instruction. */
2530 dec_insn.pc_inc = 2;
2533 dec_insn.insn = (*instr_ptr << 16) |
2535 /* 32-bit instruction. */
2536 dec_insn.pc_inc = 4;
2539 /* Get second instruction. */
2540 if (mm_insn_16bit(*instr_ptr)) {
2541 /* Duplicate the half-word. */
2542 dec_insn.next_insn = (*instr_ptr << 16) |
2544 /* 16-bit instruction. */
2545 dec_insn.next_pc_inc = 2;
2547 dec_insn.next_insn = (*instr_ptr << 16) |
2549 /* 32-bit instruction. */
2550 dec_insn.next_pc_inc = 4;
2552 dec_insn.micro_mips_mode = 1;
2554 if ((get_user(dec_insn.insn,
2555 (mips_instruction __user *) xcp->cp0_epc)) ||
2556 (get_user(dec_insn.next_insn,
2557 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2558 MIPS_FPU_EMU_INC_STATS(errors);
2561 dec_insn.pc_inc = 4;
2562 dec_insn.next_pc_inc = 4;
2563 dec_insn.micro_mips_mode = 0;
2566 if ((dec_insn.insn == 0) ||
2567 ((dec_insn.pc_inc == 2) &&
2568 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2569 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2572 * The 'ieee754_csr' is an alias of ctx->fcr31.
2573 * No need to copy ctx->fcr31 to ieee754_csr.
2575 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2584 } while (xcp->cp0_epc > prevepc);
2586 /* SIGILL indicates a non-fpu instruction */
2587 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2588 /* but if EPC has advanced, then ignore it */