1 #include <asm/branch.h>
2 #include <asm/cacheflush.h>
3 #include <asm/fpu_emulator.h>
5 #include <asm/mipsregs.h>
6 #include <asm/uaccess.h>
10 /* Strap kernel emulator for full MIPS IV emulation */
18 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
19 * we have to emulate the instruction in a COP1 branch delay slot. Do
20 * not change cp0_epc due to the instruction
22 * According to the spec:
23 * 1) it shouldn't be a branch :-)
24 * 2) it can be a COP instruction :-(
25 * 3) if we are tring to run a protected memory space we must take
26 * special care on memory access instructions :-(
30 * "Trampoline" return routine to catch exception following
31 * execution of delay-slot instruction execution.
35 mips_instruction emul;
36 mips_instruction badinst;
37 mips_instruction cookie;
41 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
43 extern asmlinkage void handle_dsemulret(void);
44 struct emuframe __user *fr;
47 if ((get_isa16_mode(regs->cp0_epc) && ((ir >> 16) == MM_NOP16)) ||
51 clear_delay_slot(regs);
55 printk("dsemul %lx %lx\n", regs->cp0_epc, cpc);
60 * The strategy is to push the instruction onto the user stack
61 * and put a trap after it which we can catch and jump to
62 * the required address any alternative apart from full
63 * instruction emulation!!.
65 * Algorithmics used a system call instruction, and
66 * borrowed that vector. MIPS/Linux version is a bit
67 * more heavyweight in the interests of portability and
68 * multiprocessor support. For Linux we generate a
69 * an unaligned access and force an address error exception.
71 * For embedded systems (stand-alone) we prefer to use a
72 * non-existing CP1 instruction. This prevents us from emulating
73 * branches, but gives us a cleaner interface to the exception
74 * handler (single entry point).
77 /* Ensure that the two instructions are in the same cache line */
78 fr = (struct emuframe __user *)
79 ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
81 /* Verify that the stack pointer is not competely insane */
82 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
85 if (get_isa16_mode(regs->cp0_epc)) {
86 err = __put_user(ir >> 16, (u16 __user *)(&fr->emul));
87 err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2));
88 err |= __put_user(BREAK_MATH >> 16, (u16 __user *)(&fr->badinst));
89 err |= __put_user(BREAK_MATH & 0xffff, (u16 __user *)((long)(&fr->badinst) + 2));
91 err = __put_user(ir, &fr->emul);
92 err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst);
95 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
96 err |= __put_user(cpc, &fr->epc);
99 MIPS_FPU_EMU_INC_STATS(errors);
103 regs->cp0_epc = ((unsigned long) &fr->emul) |
104 get_isa16_mode(regs->cp0_epc);
106 flush_cache_sigtramp((unsigned long)&fr->badinst);
108 return SIGILL; /* force out of emulation loop */
111 int do_dsemulret(struct pt_regs *xcp)
113 struct emuframe __user *fr;
119 fr = (struct emuframe __user *)
120 (msk_isa16_mode(xcp->cp0_epc) - sizeof(mips_instruction));
123 * If we can't even access the area, something is very wrong, but we'll
124 * leave that to the default handling
126 if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe)))
130 * Do some sanity checking on the stackframe:
132 * - Is the instruction pointed to by the EPC an BREAK_MATH?
133 * - Is the following memory word the BD_COOKIE?
135 if (get_isa16_mode(xcp->cp0_epc)) {
136 err = __get_user(instr[0], (u16 __user *)(&fr->badinst));
137 err |= __get_user(instr[1], (u16 __user *)((long)(&fr->badinst) + 2));
138 insn = (instr[0] << 16) | instr[1];
140 err = __get_user(insn, &fr->badinst);
142 err |= __get_user(cookie, &fr->cookie);
144 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
145 MIPS_FPU_EMU_INC_STATS(errors);
150 * At this point, we are satisfied that it's a BD emulation trap. Yes,
151 * a user might have deliberately put two malformed and useless
152 * instructions in a row in his program, in which case he's in for a
153 * nasty surprise - the next instruction will be treated as a
154 * continuation address! Alas, this seems to be the only way that we
155 * can handle signals, recursion, and longjmps() in the context of
156 * emulating the branch delay instruction.
160 printk("dsemulret\n");
162 if (__get_user(epc, &fr->epc)) { /* Saved EPC */
163 /* This is not a good situation to be in */
164 force_sig(SIGBUS, current);
169 /* Set EPC to return to post-branch instruction */