1 #include <asm/branch.h>
2 #include <asm/cacheflush.h>
3 #include <asm/fpu_emulator.h>
5 #include <asm/mipsregs.h>
6 #include <asm/uaccess.h>
11 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
12 * we have to emulate the instruction in a COP1 branch delay slot. Do
13 * not change cp0_epc due to the instruction
15 * According to the spec:
16 * 1) it shouldn't be a branch :-)
17 * 2) it can be a COP instruction :-(
18 * 3) if we are tring to run a protected memory space we must take
19 * special care on memory access instructions :-(
23 * "Trampoline" return routine to catch exception following
24 * execution of delay-slot instruction execution.
28 mips_instruction emul;
29 mips_instruction badinst;
30 mips_instruction cookie;
35 * Set up an emulation frame for instruction IR, from a delay slot of
36 * a branch jumping to CPC. Return 0 if successful, -1 if no emulation
37 * required, otherwise a signal number causing a frame setup failure.
39 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
41 mips_instruction break_math;
42 struct emuframe __user *fr;
49 /* microMIPS instructions */
50 if (get_isa16_mode(regs->cp0_epc)) {
51 union mips_instruction insn = { .word = ir };
53 /* NOP16 aka MOVE16 $0, $0 */
54 if ((ir >> 16) == MM_NOP16)
58 if (insn.mm_a_format.opcode == mm_addiupc_op) {
62 rs = (((insn.mm_a_format.rs + 0x1e) & 0xf) + 2);
63 v = regs->cp0_epc & ~3;
64 v += insn.mm_a_format.simmediate << 2;
65 regs->regs[rs] = (long)v;
70 pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc);
73 * The strategy is to push the instruction onto the user stack
74 * and put a trap after it which we can catch and jump to
75 * the required address any alternative apart from full
76 * instruction emulation!!.
78 * Algorithmics used a system call instruction, and
79 * borrowed that vector. MIPS/Linux version is a bit
80 * more heavyweight in the interests of portability and
81 * multiprocessor support. For Linux we use a BREAK 514
82 * instruction causing a breakpoint exception.
84 break_math = BREAK_MATH(get_isa16_mode(regs->cp0_epc));
86 /* Ensure that the two instructions are in the same cache line */
87 fr = (struct emuframe __user *)
88 ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
90 /* Verify that the stack pointer is not competely insane */
91 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
94 if (get_isa16_mode(regs->cp0_epc)) {
95 err = __put_user(ir >> 16,
96 (u16 __user *)(&fr->emul));
97 err |= __put_user(ir & 0xffff,
98 (u16 __user *)((long)(&fr->emul) + 2));
99 err |= __put_user(break_math >> 16,
100 (u16 __user *)(&fr->badinst));
101 err |= __put_user(break_math & 0xffff,
102 (u16 __user *)((long)(&fr->badinst) + 2));
104 err = __put_user(ir, &fr->emul);
105 err |= __put_user(break_math, &fr->badinst);
108 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
109 err |= __put_user(cpc, &fr->epc);
112 MIPS_FPU_EMU_INC_STATS(errors);
116 regs->cp0_epc = ((unsigned long) &fr->emul) |
117 get_isa16_mode(regs->cp0_epc);
119 flush_cache_sigtramp((unsigned long)&fr->emul);
124 int do_dsemulret(struct pt_regs *xcp)
126 struct emuframe __user *fr;
132 fr = (struct emuframe __user *)
133 (msk_isa16_mode(xcp->cp0_epc) - sizeof(mips_instruction));
136 * If we can't even access the area, something is very wrong, but we'll
137 * leave that to the default handling
139 if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe)))
143 * Do some sanity checking on the stackframe:
145 * - Is the instruction pointed to by the EPC an BREAK_MATH?
146 * - Is the following memory word the BD_COOKIE?
148 if (get_isa16_mode(xcp->cp0_epc)) {
149 err = __get_user(instr[0],
150 (u16 __user *)(&fr->badinst));
151 err |= __get_user(instr[1],
152 (u16 __user *)((long)(&fr->badinst) + 2));
153 insn = (instr[0] << 16) | instr[1];
155 err = __get_user(insn, &fr->badinst);
157 err |= __get_user(cookie, &fr->cookie);
159 if (unlikely(err || insn != BREAK_MATH(get_isa16_mode(xcp->cp0_epc)) ||
160 cookie != BD_COOKIE)) {
161 MIPS_FPU_EMU_INC_STATS(errors);
166 * At this point, we are satisfied that it's a BD emulation trap. Yes,
167 * a user might have deliberately put two malformed and useless
168 * instructions in a row in his program, in which case he's in for a
169 * nasty surprise - the next instruction will be treated as a
170 * continuation address! Alas, this seems to be the only way that we
171 * can handle signals, recursion, and longjmps() in the context of
172 * emulating the branch delay instruction.
175 pr_debug("dsemulret\n");
177 if (__get_user(epc, &fr->epc)) { /* Saved EPC */
178 /* This is not a good situation to be in */
179 force_sig(SIGBUS, current);
184 /* Set EPC to return to post-branch instruction */
186 MIPS_FPU_EMU_INC_STATS(ds_emul);