2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/smp.h>
15 #include <linux/hugetlb.h>
18 #include <asm/bootinfo.h>
19 #include <asm/mmu_context.h>
20 #include <asm/pgtable.h>
21 #include <asm/tlbmisc.h>
23 extern void build_tlb_refill_handler(void);
26 * Make sure all entries differ. If they're not different
27 * MIPS32 will take revenge ...
29 #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
31 /* Atomicity and interruptability */
32 #ifdef CONFIG_MIPS_MT_SMTC
35 #include <asm/mipsmtregs.h>
37 #define ENTER_CRITICAL(flags) \
39 unsigned int mvpflags; \
40 local_irq_save(flags);\
42 #define EXIT_CRITICAL(flags) \
44 local_irq_restore(flags); \
48 #define ENTER_CRITICAL(flags) local_irq_save(flags)
49 #define EXIT_CRITICAL(flags) local_irq_restore(flags)
51 #endif /* CONFIG_MIPS_MT_SMTC */
53 #if defined(CONFIG_CPU_LOONGSON2)
55 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
56 * unfortrunately, itlb is not totally transparent to software.
58 #define FLUSH_ITLB write_c0_diag(4);
60 #define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
65 #define FLUSH_ITLB_VM(vma)
69 void local_flush_tlb_all(void)
72 unsigned long old_ctx;
75 ENTER_CRITICAL(flags);
76 /* Save old context and create impossible VPN2 value */
77 old_ctx = read_c0_entryhi();
81 entry = read_c0_wired();
83 /* Blast 'em all away. */
84 while (entry < current_cpu_data.tlbsize) {
85 /* Make sure all entries differ. */
86 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
87 write_c0_index(entry);
93 write_c0_entryhi(old_ctx);
98 /* All entries common to a mm share an asid. To effectively flush
99 these entries, we just bump the asid. */
100 void local_flush_tlb_mm(struct mm_struct *mm)
106 cpu = smp_processor_id();
108 if (cpu_context(cpu, mm) != 0) {
109 drop_mmu_context(mm, cpu);
115 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
118 struct mm_struct *mm = vma->vm_mm;
119 int cpu = smp_processor_id();
121 if (cpu_context(cpu, mm) != 0) {
122 unsigned long size, flags;
123 int huge = is_vm_hugetlb_page(vma);
125 ENTER_CRITICAL(flags);
127 start = round_down(start, HPAGE_SIZE);
128 end = round_up(end, HPAGE_SIZE);
129 size = (end - start) >> HPAGE_SHIFT;
131 start = round_down(start, PAGE_SIZE << 1);
132 end = round_up(end, PAGE_SIZE << 1);
133 size = (end - start) >> (PAGE_SHIFT + 1);
135 if (size <= current_cpu_data.tlbsize/2) {
136 int oldpid = read_c0_entryhi();
137 int newpid = cpu_asid(cpu, mm);
139 while (start < end) {
142 write_c0_entryhi(start | newpid);
146 start += (PAGE_SIZE << 1);
150 idx = read_c0_index();
151 write_c0_entrylo0(0);
152 write_c0_entrylo1(0);
155 /* Make sure all entries differ. */
156 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
161 write_c0_entryhi(oldpid);
163 drop_mmu_context(mm, cpu);
166 EXIT_CRITICAL(flags);
170 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
172 unsigned long size, flags;
174 ENTER_CRITICAL(flags);
175 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
176 size = (size + 1) >> 1;
177 if (size <= current_cpu_data.tlbsize / 2) {
178 int pid = read_c0_entryhi();
180 start &= (PAGE_MASK << 1);
181 end += ((PAGE_SIZE << 1) - 1);
182 end &= (PAGE_MASK << 1);
184 while (start < end) {
187 write_c0_entryhi(start);
188 start += (PAGE_SIZE << 1);
192 idx = read_c0_index();
193 write_c0_entrylo0(0);
194 write_c0_entrylo1(0);
197 /* Make sure all entries differ. */
198 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
203 write_c0_entryhi(pid);
205 local_flush_tlb_all();
208 EXIT_CRITICAL(flags);
211 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
213 int cpu = smp_processor_id();
215 if (cpu_context(cpu, vma->vm_mm) != 0) {
217 int oldpid, newpid, idx;
219 newpid = cpu_asid(cpu, vma->vm_mm);
220 page &= (PAGE_MASK << 1);
221 ENTER_CRITICAL(flags);
222 oldpid = read_c0_entryhi();
223 write_c0_entryhi(page | newpid);
227 idx = read_c0_index();
228 write_c0_entrylo0(0);
229 write_c0_entrylo1(0);
232 /* Make sure all entries differ. */
233 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
239 write_c0_entryhi(oldpid);
241 EXIT_CRITICAL(flags);
246 * This one is only used for pages with the global bit set so we don't care
247 * much about the ASID.
249 void local_flush_tlb_one(unsigned long page)
254 ENTER_CRITICAL(flags);
255 oldpid = read_c0_entryhi();
256 page &= (PAGE_MASK << 1);
257 write_c0_entryhi(page);
261 idx = read_c0_index();
262 write_c0_entrylo0(0);
263 write_c0_entrylo1(0);
265 /* Make sure all entries differ. */
266 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
271 write_c0_entryhi(oldpid);
273 EXIT_CRITICAL(flags);
277 * We will need multiple versions of update_mmu_cache(), one that just
278 * updates the TLB with the new pte(s), and another which also checks
279 * for the R4k "end of page" hardware bug and does the needy.
281 void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
291 * Handle debugger faulting in for debugee.
293 if (current->active_mm != vma->vm_mm)
296 ENTER_CRITICAL(flags);
298 pid = read_c0_entryhi() & ASID_MASK;
299 address &= (PAGE_MASK << 1);
300 write_c0_entryhi(address | pid);
301 pgdp = pgd_offset(vma->vm_mm, address);
305 pudp = pud_offset(pgdp, address);
306 pmdp = pmd_offset(pudp, address);
307 idx = read_c0_index();
308 #ifdef CONFIG_HUGETLB_PAGE
309 /* this could be a huge page */
310 if (pmd_huge(*pmdp)) {
312 write_c0_pagemask(PM_HUGE_MASK);
313 ptep = (pte_t *)pmdp;
314 lo = pte_to_entrylo(pte_val(*ptep));
315 write_c0_entrylo0(lo);
316 write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
324 write_c0_pagemask(PM_DEFAULT_MASK);
328 ptep = pte_offset_map(pmdp, address);
330 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
331 write_c0_entrylo0(ptep->pte_high);
333 write_c0_entrylo1(ptep->pte_high);
335 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
336 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
346 EXIT_CRITICAL(flags);
349 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
350 unsigned long entryhi, unsigned long pagemask)
354 unsigned long old_pagemask;
355 unsigned long old_ctx;
357 ENTER_CRITICAL(flags);
358 /* Save old context and create impossible VPN2 value */
359 old_ctx = read_c0_entryhi();
360 old_pagemask = read_c0_pagemask();
361 wired = read_c0_wired();
362 write_c0_wired(wired + 1);
363 write_c0_index(wired);
364 tlbw_use_hazard(); /* What is the hazard here? */
365 write_c0_pagemask(pagemask);
366 write_c0_entryhi(entryhi);
367 write_c0_entrylo0(entrylo0);
368 write_c0_entrylo1(entrylo1);
373 write_c0_entryhi(old_ctx);
374 tlbw_use_hazard(); /* What is the hazard here? */
375 write_c0_pagemask(old_pagemask);
376 local_flush_tlb_all();
377 EXIT_CRITICAL(flags);
380 static int __cpuinitdata ntlb;
381 static int __init set_ntlb(char *str)
383 get_option(&str, &ntlb);
387 __setup("ntlb=", set_ntlb);
389 void __cpuinit tlb_init(void)
392 * You should never change this register:
393 * - On R4600 1.7 the tlbp never hits for pages smaller than
394 * the value in the c0_pagemask register.
395 * - The entire mm handling assumes the c0_pagemask register to
396 * be set to fixed-size pages.
398 write_c0_pagemask(PM_DEFAULT_MASK);
400 if (current_cpu_type() == CPU_R10000 ||
401 current_cpu_type() == CPU_R12000 ||
402 current_cpu_type() == CPU_R14000)
403 write_c0_framemask(0);
407 * Enable the no read, no exec bits, and enable large virtual
410 u32 pg = PG_RIE | PG_XIE;
414 write_c0_pagegrain(pg);
417 /* From this point on the ARC firmware is dead. */
418 local_flush_tlb_all();
420 /* Did I tell you that ARC SUCKS? */
423 if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
424 int wired = current_cpu_data.tlbsize - ntlb;
425 write_c0_wired(wired);
426 write_c0_index(wired-1);
427 printk("Restricting TLB to %d entries\n", ntlb);
429 printk("Ignoring invalid argument ntlb=%d\n", ntlb);
432 build_tlb_refill_handler();