2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/smp.h>
15 #include <linux/hugetlb.h>
16 #include <linux/module.h>
19 #include <asm/cpu-type.h>
20 #include <asm/bootinfo.h>
21 #include <asm/mmu_context.h>
22 #include <asm/pgtable.h>
23 #include <asm/tlbmisc.h>
25 extern void build_tlb_refill_handler(void);
28 * Make sure all entries differ. If they're not different
29 * MIPS32 will take revenge ...
31 #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
33 /* Atomicity and interruptability */
34 #ifdef CONFIG_MIPS_MT_SMTC
37 #include <asm/mipsmtregs.h>
39 #define ENTER_CRITICAL(flags) \
41 unsigned int mvpflags; \
42 local_irq_save(flags);\
44 #define EXIT_CRITICAL(flags) \
46 local_irq_restore(flags); \
50 #define ENTER_CRITICAL(flags) local_irq_save(flags)
51 #define EXIT_CRITICAL(flags) local_irq_restore(flags)
53 #endif /* CONFIG_MIPS_MT_SMTC */
55 #if defined(CONFIG_CPU_LOONGSON2)
57 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
58 * unfortrunately, itlb is not totally transparent to software.
60 #define FLUSH_ITLB write_c0_diag(4);
62 #define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
67 #define FLUSH_ITLB_VM(vma)
71 void local_flush_tlb_all(void)
74 unsigned long old_ctx;
77 ENTER_CRITICAL(flags);
78 /* Save old context and create impossible VPN2 value */
79 old_ctx = read_c0_entryhi();
83 entry = read_c0_wired();
85 /* Blast 'em all away. */
86 while (entry < current_cpu_data.tlbsize) {
87 /* Make sure all entries differ. */
88 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
89 write_c0_index(entry);
95 write_c0_entryhi(old_ctx);
99 EXPORT_SYMBOL(local_flush_tlb_all);
101 /* All entries common to a mm share an asid. To effectively flush
102 these entries, we just bump the asid. */
103 void local_flush_tlb_mm(struct mm_struct *mm)
109 cpu = smp_processor_id();
111 if (cpu_context(cpu, mm) != 0) {
112 drop_mmu_context(mm, cpu);
118 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
121 struct mm_struct *mm = vma->vm_mm;
122 int cpu = smp_processor_id();
124 if (cpu_context(cpu, mm) != 0) {
125 unsigned long size, flags;
127 ENTER_CRITICAL(flags);
128 start = round_down(start, PAGE_SIZE << 1);
129 end = round_up(end, PAGE_SIZE << 1);
130 size = (end - start) >> (PAGE_SHIFT + 1);
131 if (size <= current_cpu_data.tlbsize/2) {
132 int oldpid = read_c0_entryhi();
133 int newpid = cpu_asid(cpu, mm);
135 while (start < end) {
138 write_c0_entryhi(start | newpid);
139 start += (PAGE_SIZE << 1);
143 idx = read_c0_index();
144 write_c0_entrylo0(0);
145 write_c0_entrylo1(0);
148 /* Make sure all entries differ. */
149 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
154 write_c0_entryhi(oldpid);
156 drop_mmu_context(mm, cpu);
159 EXIT_CRITICAL(flags);
163 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
165 unsigned long size, flags;
167 ENTER_CRITICAL(flags);
168 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
169 size = (size + 1) >> 1;
170 if (size <= current_cpu_data.tlbsize / 2) {
171 int pid = read_c0_entryhi();
173 start &= (PAGE_MASK << 1);
174 end += ((PAGE_SIZE << 1) - 1);
175 end &= (PAGE_MASK << 1);
177 while (start < end) {
180 write_c0_entryhi(start);
181 start += (PAGE_SIZE << 1);
185 idx = read_c0_index();
186 write_c0_entrylo0(0);
187 write_c0_entrylo1(0);
190 /* Make sure all entries differ. */
191 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
196 write_c0_entryhi(pid);
198 local_flush_tlb_all();
201 EXIT_CRITICAL(flags);
204 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
206 int cpu = smp_processor_id();
208 if (cpu_context(cpu, vma->vm_mm) != 0) {
210 int oldpid, newpid, idx;
212 newpid = cpu_asid(cpu, vma->vm_mm);
213 page &= (PAGE_MASK << 1);
214 ENTER_CRITICAL(flags);
215 oldpid = read_c0_entryhi();
216 write_c0_entryhi(page | newpid);
220 idx = read_c0_index();
221 write_c0_entrylo0(0);
222 write_c0_entrylo1(0);
225 /* Make sure all entries differ. */
226 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
232 write_c0_entryhi(oldpid);
234 EXIT_CRITICAL(flags);
239 * This one is only used for pages with the global bit set so we don't care
240 * much about the ASID.
242 void local_flush_tlb_one(unsigned long page)
247 ENTER_CRITICAL(flags);
248 oldpid = read_c0_entryhi();
249 page &= (PAGE_MASK << 1);
250 write_c0_entryhi(page);
254 idx = read_c0_index();
255 write_c0_entrylo0(0);
256 write_c0_entrylo1(0);
258 /* Make sure all entries differ. */
259 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
264 write_c0_entryhi(oldpid);
266 EXIT_CRITICAL(flags);
270 * We will need multiple versions of update_mmu_cache(), one that just
271 * updates the TLB with the new pte(s), and another which also checks
272 * for the R4k "end of page" hardware bug and does the needy.
274 void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
284 * Handle debugger faulting in for debugee.
286 if (current->active_mm != vma->vm_mm)
289 ENTER_CRITICAL(flags);
291 pid = read_c0_entryhi() & ASID_MASK;
292 address &= (PAGE_MASK << 1);
293 write_c0_entryhi(address | pid);
294 pgdp = pgd_offset(vma->vm_mm, address);
298 pudp = pud_offset(pgdp, address);
299 pmdp = pmd_offset(pudp, address);
300 idx = read_c0_index();
301 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
302 /* this could be a huge page */
303 if (pmd_huge(*pmdp)) {
305 write_c0_pagemask(PM_HUGE_MASK);
306 ptep = (pte_t *)pmdp;
307 lo = pte_to_entrylo(pte_val(*ptep));
308 write_c0_entrylo0(lo);
309 write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
317 write_c0_pagemask(PM_DEFAULT_MASK);
321 ptep = pte_offset_map(pmdp, address);
323 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
324 write_c0_entrylo0(ptep->pte_high);
326 write_c0_entrylo1(ptep->pte_high);
328 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
329 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
339 EXIT_CRITICAL(flags);
342 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
343 unsigned long entryhi, unsigned long pagemask)
347 unsigned long old_pagemask;
348 unsigned long old_ctx;
350 ENTER_CRITICAL(flags);
351 /* Save old context and create impossible VPN2 value */
352 old_ctx = read_c0_entryhi();
353 old_pagemask = read_c0_pagemask();
354 wired = read_c0_wired();
355 write_c0_wired(wired + 1);
356 write_c0_index(wired);
357 tlbw_use_hazard(); /* What is the hazard here? */
358 write_c0_pagemask(pagemask);
359 write_c0_entryhi(entryhi);
360 write_c0_entrylo0(entrylo0);
361 write_c0_entrylo1(entrylo1);
366 write_c0_entryhi(old_ctx);
367 tlbw_use_hazard(); /* What is the hazard here? */
368 write_c0_pagemask(old_pagemask);
369 local_flush_tlb_all();
370 EXIT_CRITICAL(flags);
373 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
375 int __init has_transparent_hugepage(void)
380 ENTER_CRITICAL(flags);
381 write_c0_pagemask(PM_HUGE_MASK);
382 back_to_back_c0_hazard();
383 mask = read_c0_pagemask();
384 write_c0_pagemask(PM_DEFAULT_MASK);
386 EXIT_CRITICAL(flags);
388 return mask == PM_HUGE_MASK;
391 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
394 static int __init set_ntlb(char *str)
396 get_option(&str, &ntlb);
400 __setup("ntlb=", set_ntlb);
405 * You should never change this register:
406 * - On R4600 1.7 the tlbp never hits for pages smaller than
407 * the value in the c0_pagemask register.
408 * - The entire mm handling assumes the c0_pagemask register to
409 * be set to fixed-size pages.
411 write_c0_pagemask(PM_DEFAULT_MASK);
413 if (current_cpu_type() == CPU_R10000 ||
414 current_cpu_type() == CPU_R12000 ||
415 current_cpu_type() == CPU_R14000)
416 write_c0_framemask(0);
420 * Enable the no read, no exec bits, and enable large virtual
423 u32 pg = PG_RIE | PG_XIE;
427 write_c0_pagegrain(pg);
430 /* From this point on the ARC firmware is dead. */
431 local_flush_tlb_all();
433 /* Did I tell you that ARC SUCKS? */
436 if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
437 int wired = current_cpu_data.tlbsize - ntlb;
438 write_c0_wired(wired);
439 write_c0_index(wired-1);
440 printk("Restricting TLB to %d entries\n", ntlb);
442 printk("Ignoring invalid argument ntlb=%d\n", ntlb);
445 build_tlb_refill_handler();