2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completely out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/cache.h>
31 #include <asm/cacheflush.h>
32 #include <asm/cpu-type.h>
33 #include <asm/pgtable.h>
36 #include <asm/setup.h>
38 static int mips_xpa_disabled;
40 static int __init xpa_disable(char *s)
42 mips_xpa_disabled = 1;
47 __setup("noxpa", xpa_disable);
50 * TLB load/store/modify handlers.
52 * Only the fastpath gets synthesized at runtime, the slowpath for
53 * do_page_fault remains normal asm.
55 extern void tlb_do_page_fault_0(void);
56 extern void tlb_do_page_fault_1(void);
58 struct work_registers {
67 } ____cacheline_aligned_in_smp;
69 static struct tlb_reg_save handler_reg_save[NR_CPUS];
71 static inline int r45k_bvahwbug(void)
73 /* XXX: We should probe for the presence of this bug, but we don't. */
77 static inline int r4k_250MHZhwbug(void)
79 /* XXX: We should probe for the presence of this bug, but we don't. */
83 static inline int __maybe_unused bcm1250_m3_war(void)
85 return BCM1250_M3_WAR;
88 static inline int __maybe_unused r10000_llsc_war(void)
90 return R10000_LLSC_WAR;
93 static int use_bbit_insns(void)
95 switch (current_cpu_type()) {
96 case CPU_CAVIUM_OCTEON:
97 case CPU_CAVIUM_OCTEON_PLUS:
98 case CPU_CAVIUM_OCTEON2:
99 case CPU_CAVIUM_OCTEON3:
106 static int use_lwx_insns(void)
108 switch (current_cpu_type()) {
109 case CPU_CAVIUM_OCTEON2:
110 case CPU_CAVIUM_OCTEON3:
116 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
117 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
118 static bool scratchpad_available(void)
122 static int scratchpad_offset(int i)
125 * CVMSEG starts at address -32768 and extends for
126 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
128 i += 1; /* Kernel use starts at the top and works down. */
129 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
132 static bool scratchpad_available(void)
136 static int scratchpad_offset(int i)
139 /* Really unreachable, but evidently some GCC want this. */
144 * Found by experiment: At least some revisions of the 4kc throw under
145 * some circumstances a machine check exception, triggered by invalid
146 * values in the index register. Delaying the tlbp instruction until
147 * after the next branch, plus adding an additional nop in front of
148 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
149 * why; it's not an issue caused by the core RTL.
152 static int m4kc_tlbp_war(void)
154 return (current_cpu_data.processor_id & 0xffff00) ==
155 (PRID_COMP_MIPS | PRID_IMP_4KC);
158 /* Handle labels (which must be positive integers). */
160 label_second_part = 1,
165 label_split = label_tlbw_hazard_0 + 8,
166 label_tlbl_goaround1,
167 label_tlbl_goaround2,
171 label_smp_pgtable_change,
172 label_r3000_write_probe_fail,
173 label_large_segbits_fault,
174 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
175 label_tlb_huge_update,
179 UASM_L_LA(_second_part)
182 UASM_L_LA(_vmalloc_done)
183 /* _tlbw_hazard_x is handled differently. */
185 UASM_L_LA(_tlbl_goaround1)
186 UASM_L_LA(_tlbl_goaround2)
187 UASM_L_LA(_nopage_tlbl)
188 UASM_L_LA(_nopage_tlbs)
189 UASM_L_LA(_nopage_tlbm)
190 UASM_L_LA(_smp_pgtable_change)
191 UASM_L_LA(_r3000_write_probe_fail)
192 UASM_L_LA(_large_segbits_fault)
193 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
194 UASM_L_LA(_tlb_huge_update)
197 static int hazard_instance;
199 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
203 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
210 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
214 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
222 * pgtable bits are assigned dynamically depending on processor feature
223 * and statically based on kernel configuration. This spits out the actual
224 * values the kernel is using. Required to make sense from disassembled
225 * TLB exception handlers.
227 static void output_pgtable_bits_defines(void)
229 #define pr_define(fmt, ...) \
230 pr_debug("#define " fmt, ##__VA_ARGS__)
232 pr_debug("#include <asm/asm.h>\n");
233 pr_debug("#include <asm/regdef.h>\n");
236 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
237 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
238 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
239 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
240 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
241 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
242 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
244 #ifdef _PAGE_NO_EXEC_SHIFT
246 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
248 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
249 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
250 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
251 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
255 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
259 pr_debug("LEAF(%s)\n", symbol);
261 pr_debug("\t.set push\n");
262 pr_debug("\t.set noreorder\n");
264 for (i = 0; i < count; i++)
265 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
267 pr_debug("\t.set\tpop\n");
269 pr_debug("\tEND(%s)\n", symbol);
272 /* The only general purpose registers allowed in TLB handlers. */
276 /* Some CP0 registers */
277 #define C0_INDEX 0, 0
278 #define C0_ENTRYLO0 2, 0
279 #define C0_TCBIND 2, 2
280 #define C0_ENTRYLO1 3, 0
281 #define C0_CONTEXT 4, 0
282 #define C0_PAGEMASK 5, 0
283 #define C0_PWBASE 5, 5
284 #define C0_PWFIELD 5, 6
285 #define C0_PWSIZE 5, 7
286 #define C0_PWCTL 6, 6
287 #define C0_BADVADDR 8, 0
289 #define C0_ENTRYHI 10, 0
291 #define C0_XCONTEXT 20, 0
294 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
296 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
299 /* The worst case length of the handler is around 18 instructions for
300 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
301 * Maximum space available is 32 instructions for R3000 and 64
302 * instructions for R4000.
304 * We deliberately chose a buffer size of 128, so we won't scribble
305 * over anything important on overflow before we panic.
307 static u32 tlb_handler[128];
309 /* simply assume worst case size for labels and relocs */
310 static struct uasm_label labels[128];
311 static struct uasm_reloc relocs[128];
313 static int check_for_high_segbits;
314 static bool fill_includes_sw_bits;
316 static unsigned int kscratch_used_mask;
318 static inline int __maybe_unused c0_kscratch(void)
320 switch (current_cpu_type()) {
329 static int allocate_kscratch(void)
332 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
339 r--; /* make it zero based */
341 kscratch_used_mask |= (1 << r);
346 static int scratch_reg;
348 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
350 static struct work_registers build_get_work_registers(u32 **p)
352 struct work_registers r;
354 if (scratch_reg >= 0) {
355 /* Save in CPU local C0_KScratch? */
356 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
363 if (num_possible_cpus() > 1) {
364 /* Get smp_processor_id */
365 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
366 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
368 /* handler_reg_save index in K0 */
369 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
371 UASM_i_LA(p, K1, (long)&handler_reg_save);
372 UASM_i_ADDU(p, K0, K0, K1);
374 UASM_i_LA(p, K0, (long)&handler_reg_save);
376 /* K0 now points to save area, save $1 and $2 */
377 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
378 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
386 static void build_restore_work_registers(u32 **p)
388 if (scratch_reg >= 0) {
389 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
392 /* K0 already points to save area, restore $1 and $2 */
393 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
394 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
397 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
400 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
401 * we cannot do r3000 under these circumstances.
403 * Declare pgd_current here instead of including mmu_context.h to avoid type
404 * conflicts for tlbmiss_handler_setup_pgd
406 extern unsigned long pgd_current[];
409 * The R3000 TLB handler is simple.
411 static void build_r3000_tlb_refill_handler(void)
413 long pgdc = (long)pgd_current;
416 memset(tlb_handler, 0, sizeof(tlb_handler));
419 uasm_i_mfc0(&p, K0, C0_BADVADDR);
420 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
421 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
422 uasm_i_srl(&p, K0, K0, 22); /* load delay */
423 uasm_i_sll(&p, K0, K0, 2);
424 uasm_i_addu(&p, K1, K1, K0);
425 uasm_i_mfc0(&p, K0, C0_CONTEXT);
426 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
427 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
428 uasm_i_addu(&p, K1, K1, K0);
429 uasm_i_lw(&p, K0, 0, K1);
430 uasm_i_nop(&p); /* load delay */
431 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
432 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
433 uasm_i_tlbwr(&p); /* cp0 delay */
435 uasm_i_rfe(&p); /* branch delay */
437 if (p > tlb_handler + 32)
438 panic("TLB refill handler space exceeded");
440 pr_debug("Wrote TLB refill handler (%u instructions).\n",
441 (unsigned int)(p - tlb_handler));
443 memcpy((void *)ebase, tlb_handler, 0x80);
444 local_flush_icache_range(ebase, ebase + 0x80);
446 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
448 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
451 * The R4000 TLB handler is much more complicated. We have two
452 * consecutive handler areas with 32 instructions space each.
453 * Since they aren't used at the same time, we can overflow in the
454 * other one.To keep things simple, we first assume linear space,
455 * then we relocate it to the final handler layout as needed.
457 static u32 final_handler[64];
462 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
463 * 2. A timing hazard exists for the TLBP instruction.
465 * stalling_instruction
468 * The JTLB is being read for the TLBP throughout the stall generated by the
469 * previous instruction. This is not really correct as the stalling instruction
470 * can modify the address used to access the JTLB. The failure symptom is that
471 * the TLBP instruction will use an address created for the stalling instruction
472 * and not the address held in C0_ENHI and thus report the wrong results.
474 * The software work-around is to not allow the instruction preceding the TLBP
475 * to stall - make it an NOP or some other instruction guaranteed not to stall.
477 * Errata 2 will not be fixed. This errata is also on the R5000.
479 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
481 static void __maybe_unused build_tlb_probe_entry(u32 **p)
483 switch (current_cpu_type()) {
484 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
500 * Write random or indexed TLB entry, and care about the hazards from
501 * the preceding mtc0 and for the following eret.
503 enum tlb_write_entry { tlb_random, tlb_indexed };
505 static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
506 struct uasm_reloc **r,
507 enum tlb_write_entry wmode)
509 void(*tlbw)(u32 **) = NULL;
512 case tlb_random: tlbw = uasm_i_tlbwr; break;
513 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
516 if (cpu_has_mips_r2_r6) {
517 if (cpu_has_mips_r2_exec_hazard)
523 switch (current_cpu_type()) {
531 * This branch uses up a mtc0 hazard nop slot and saves
532 * two nops after the tlbw instruction.
534 uasm_bgezl_hazard(p, r, hazard_instance);
536 uasm_bgezl_label(l, p, hazard_instance);
550 uasm_i_nop(p); /* QED specifies 2 nops hazard */
551 uasm_i_nop(p); /* QED specifies 2 nops hazard */
625 panic("No TLB refill handler yet (CPU type: %d)",
631 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
634 if (_PAGE_GLOBAL_SHIFT == 0) {
635 /* pte_t is already in EntryLo format */
639 if (cpu_has_rixi && _PAGE_NO_EXEC) {
640 if (fill_includes_sw_bits) {
641 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
643 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
644 UASM_i_ROTR(p, reg, reg,
645 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
648 #ifdef CONFIG_PHYS_ADDR_T_64BIT
649 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
651 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
656 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
658 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
659 unsigned int tmp, enum label_id lid,
662 if (restore_scratch) {
663 /* Reset default page size */
664 if (PM_DEFAULT_MASK >> 16) {
665 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
666 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
667 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
668 uasm_il_b(p, r, lid);
669 } else if (PM_DEFAULT_MASK) {
670 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
671 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
672 uasm_il_b(p, r, lid);
674 uasm_i_mtc0(p, 0, C0_PAGEMASK);
675 uasm_il_b(p, r, lid);
677 if (scratch_reg >= 0)
678 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
680 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
682 /* Reset default page size */
683 if (PM_DEFAULT_MASK >> 16) {
684 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
685 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
686 uasm_il_b(p, r, lid);
687 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
688 } else if (PM_DEFAULT_MASK) {
689 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
690 uasm_il_b(p, r, lid);
691 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
693 uasm_il_b(p, r, lid);
694 uasm_i_mtc0(p, 0, C0_PAGEMASK);
699 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
700 struct uasm_reloc **r,
702 enum tlb_write_entry wmode,
705 /* Set huge page tlb entry size */
706 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
707 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
708 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
710 build_tlb_write_entry(p, l, r, wmode);
712 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
716 * Check if Huge PTE is present, if so then jump to LABEL.
719 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
720 unsigned int pmd, int lid)
722 UASM_i_LW(p, tmp, 0, pmd);
723 if (use_bbit_insns()) {
724 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
726 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
727 uasm_il_bnez(p, r, tmp, lid);
731 static void build_huge_update_entries(u32 **p, unsigned int pte,
737 * A huge PTE describes an area the size of the
738 * configured huge page size. This is twice the
739 * of the large TLB entry size we intend to use.
740 * A TLB entry half the size of the configured
741 * huge page size is configured into entrylo0
742 * and entrylo1 to cover the contiguous huge PTE
745 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
747 /* We can clobber tmp. It isn't used after this.*/
749 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
751 build_convert_pte_to_entrylo(p, pte);
752 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
753 /* convert to entrylo1 */
755 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
757 UASM_i_ADDU(p, pte, pte, tmp);
759 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
762 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
763 struct uasm_label **l,
768 UASM_i_SC(p, pte, 0, ptr);
769 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
770 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
772 UASM_i_SW(p, pte, 0, ptr);
774 build_huge_update_entries(p, pte, ptr);
775 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
777 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
781 * TMP and PTR are scratch.
782 * TMP will be clobbered, PTR will hold the pmd entry.
785 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
786 unsigned int tmp, unsigned int ptr)
788 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
789 long pgdc = (long)pgd_current;
792 * The vmalloc handling is not in the hotpath.
794 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
796 if (check_for_high_segbits) {
798 * The kernel currently implicitely assumes that the
799 * MIPS SEGBITS parameter for the processor is
800 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
801 * allocate virtual addresses outside the maximum
802 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
803 * that doesn't prevent user code from accessing the
804 * higher xuseg addresses. Here, we make sure that
805 * everything but the lower xuseg addresses goes down
806 * the module_alloc/vmalloc path.
808 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
809 uasm_il_bnez(p, r, ptr, label_vmalloc);
811 uasm_il_bltz(p, r, tmp, label_vmalloc);
813 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
816 /* pgd is in pgd_reg */
818 UASM_i_MFC0(p, ptr, C0_PWBASE);
820 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
822 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
824 * &pgd << 11 stored in CONTEXT [23..63].
826 UASM_i_MFC0(p, ptr, C0_CONTEXT);
828 /* Clear lower 23 bits of context. */
829 uasm_i_dins(p, ptr, 0, 0, 23);
831 /* 1 0 1 0 1 << 6 xkphys cached */
832 uasm_i_ori(p, ptr, ptr, 0x540);
833 uasm_i_drotr(p, ptr, ptr, 11);
834 #elif defined(CONFIG_SMP)
835 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
836 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
837 UASM_i_LA_mostly(p, tmp, pgdc);
838 uasm_i_daddu(p, ptr, ptr, tmp);
839 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
840 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
842 UASM_i_LA_mostly(p, ptr, pgdc);
843 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
847 uasm_l_vmalloc_done(l, *p);
849 /* get pgd offset in bytes */
850 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
852 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
853 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
854 #ifndef __PAGETABLE_PMD_FOLDED
855 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
856 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
857 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
858 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
859 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
864 * BVADDR is the faulting address, PTR is scratch.
865 * PTR will hold the pgd for vmalloc.
868 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
869 unsigned int bvaddr, unsigned int ptr,
870 enum vmalloc64_mode mode)
872 long swpd = (long)swapper_pg_dir;
873 int single_insn_swpd;
874 int did_vmalloc_branch = 0;
876 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
878 uasm_l_vmalloc(l, *p);
880 if (mode != not_refill && check_for_high_segbits) {
881 if (single_insn_swpd) {
882 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
883 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
884 did_vmalloc_branch = 1;
887 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
890 if (!did_vmalloc_branch) {
891 if (single_insn_swpd) {
892 uasm_il_b(p, r, label_vmalloc_done);
893 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
895 UASM_i_LA_mostly(p, ptr, swpd);
896 uasm_il_b(p, r, label_vmalloc_done);
897 if (uasm_in_compat_space_p(swpd))
898 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
900 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
903 if (mode != not_refill && check_for_high_segbits) {
904 uasm_l_large_segbits_fault(l, *p);
906 * We get here if we are an xsseg address, or if we are
907 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
909 * Ignoring xsseg (assume disabled so would generate
910 * (address errors?), the only remaining possibility
911 * is the upper xuseg addresses. On processors with
912 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
913 * addresses would have taken an address error. We try
914 * to mimic that here by taking a load/istream page
917 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
920 if (mode == refill_scratch) {
921 if (scratch_reg >= 0)
922 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
924 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
931 #else /* !CONFIG_64BIT */
934 * TMP and PTR are scratch.
935 * TMP will be clobbered, PTR will hold the pgd entry.
937 static void __maybe_unused
938 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
941 /* pgd is in pgd_reg */
942 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
943 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
945 long pgdc = (long)pgd_current;
947 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
949 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
950 UASM_i_LA_mostly(p, tmp, pgdc);
951 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
952 uasm_i_addu(p, ptr, tmp, ptr);
954 UASM_i_LA_mostly(p, ptr, pgdc);
956 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
957 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
959 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
960 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
961 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
964 #endif /* !CONFIG_64BIT */
966 static void build_adjust_context(u32 **p, unsigned int ctx)
968 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
969 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
971 switch (current_cpu_type()) {
988 UASM_i_SRL(p, ctx, ctx, shift);
989 uasm_i_andi(p, ctx, ctx, mask);
992 static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
995 * Bug workaround for the Nevada. It seems as if under certain
996 * circumstances the move from cp0_context might produce a
997 * bogus result when the mfc0 instruction and its consumer are
998 * in a different cacheline or a load instruction, probably any
999 * memory reference, is between them.
1001 switch (current_cpu_type()) {
1003 UASM_i_LW(p, ptr, 0, ptr);
1004 GET_CONTEXT(p, tmp); /* get context reg */
1008 GET_CONTEXT(p, tmp); /* get context reg */
1009 UASM_i_LW(p, ptr, 0, ptr);
1013 build_adjust_context(p, tmp);
1014 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1017 static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1019 int pte_off_even = 0;
1020 int pte_off_odd = sizeof(pte_t);
1022 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1023 /* The low 32 bits of EntryLo is stored in pte_high */
1024 pte_off_even += offsetof(pte_t, pte_high);
1025 pte_off_odd += offsetof(pte_t, pte_high);
1028 if (IS_ENABLED(CONFIG_XPA)) {
1029 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1030 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1031 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1033 if (cpu_has_xpa && !mips_xpa_disabled) {
1034 uasm_i_lw(p, tmp, 0, ptep);
1035 uasm_i_ext(p, tmp, tmp, 0, 24);
1036 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1039 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
1040 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1041 UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
1043 if (cpu_has_xpa && !mips_xpa_disabled) {
1044 uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
1045 uasm_i_ext(p, tmp, tmp, 0, 24);
1046 uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
1051 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
1052 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
1053 if (r45k_bvahwbug())
1054 build_tlb_probe_entry(p);
1055 build_convert_pte_to_entrylo(p, tmp);
1056 if (r4k_250MHZhwbug())
1057 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1058 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1059 build_convert_pte_to_entrylo(p, ptep);
1060 if (r45k_bvahwbug())
1061 uasm_i_mfc0(p, tmp, C0_INDEX);
1062 if (r4k_250MHZhwbug())
1063 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1064 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1067 struct mips_huge_tlb_info {
1069 int restore_scratch;
1070 bool need_reload_pte;
1073 static struct mips_huge_tlb_info
1074 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1075 struct uasm_reloc **r, unsigned int tmp,
1076 unsigned int ptr, int c0_scratch_reg)
1078 struct mips_huge_tlb_info rv;
1079 unsigned int even, odd;
1080 int vmalloc_branch_delay_filled = 0;
1081 const int scratch = 1; /* Our extra working register */
1083 rv.huge_pte = scratch;
1084 rv.restore_scratch = 0;
1085 rv.need_reload_pte = false;
1087 if (check_for_high_segbits) {
1088 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1091 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1093 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1095 if (c0_scratch_reg >= 0)
1096 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1098 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1100 uasm_i_dsrl_safe(p, scratch, tmp,
1101 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1102 uasm_il_bnez(p, r, scratch, label_vmalloc);
1104 if (pgd_reg == -1) {
1105 vmalloc_branch_delay_filled = 1;
1106 /* Clear lower 23 bits of context. */
1107 uasm_i_dins(p, ptr, 0, 0, 23);
1111 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1113 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1115 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1117 if (c0_scratch_reg >= 0)
1118 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1120 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1123 /* Clear lower 23 bits of context. */
1124 uasm_i_dins(p, ptr, 0, 0, 23);
1126 uasm_il_bltz(p, r, tmp, label_vmalloc);
1129 if (pgd_reg == -1) {
1130 vmalloc_branch_delay_filled = 1;
1131 /* 1 0 1 0 1 << 6 xkphys cached */
1132 uasm_i_ori(p, ptr, ptr, 0x540);
1133 uasm_i_drotr(p, ptr, ptr, 11);
1136 #ifdef __PAGETABLE_PMD_FOLDED
1137 #define LOC_PTEP scratch
1139 #define LOC_PTEP ptr
1142 if (!vmalloc_branch_delay_filled)
1143 /* get pgd offset in bytes */
1144 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1146 uasm_l_vmalloc_done(l, *p);
1150 * fall-through case = badvaddr *pgd_current
1151 * vmalloc case = badvaddr swapper_pg_dir
1154 if (vmalloc_branch_delay_filled)
1155 /* get pgd offset in bytes */
1156 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1158 #ifdef __PAGETABLE_PMD_FOLDED
1159 GET_CONTEXT(p, tmp); /* get context reg */
1161 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1163 if (use_lwx_insns()) {
1164 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1166 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1167 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1170 #ifndef __PAGETABLE_PMD_FOLDED
1171 /* get pmd offset in bytes */
1172 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1173 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1174 GET_CONTEXT(p, tmp); /* get context reg */
1176 if (use_lwx_insns()) {
1177 UASM_i_LWX(p, scratch, scratch, ptr);
1179 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1180 UASM_i_LW(p, scratch, 0, ptr);
1183 /* Adjust the context during the load latency. */
1184 build_adjust_context(p, tmp);
1186 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1187 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1189 * The in the LWX case we don't want to do the load in the
1190 * delay slot. It cannot issue in the same cycle and may be
1191 * speculative and unneeded.
1193 if (use_lwx_insns())
1195 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1198 /* build_update_entries */
1199 if (use_lwx_insns()) {
1202 UASM_i_LWX(p, even, scratch, tmp);
1203 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1204 UASM_i_LWX(p, odd, scratch, tmp);
1206 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1209 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1210 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1213 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1214 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1215 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1217 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1218 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1219 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1221 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1223 if (c0_scratch_reg >= 0) {
1224 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1225 build_tlb_write_entry(p, l, r, tlb_random);
1226 uasm_l_leave(l, *p);
1227 rv.restore_scratch = 1;
1228 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1229 build_tlb_write_entry(p, l, r, tlb_random);
1230 uasm_l_leave(l, *p);
1231 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1233 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1234 build_tlb_write_entry(p, l, r, tlb_random);
1235 uasm_l_leave(l, *p);
1236 rv.restore_scratch = 1;
1239 uasm_i_eret(p); /* return from trap */
1245 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1246 * because EXL == 0. If we wrap, we can also use the 32 instruction
1247 * slots before the XTLB refill exception handler which belong to the
1248 * unused TLB refill exception.
1250 #define MIPS64_REFILL_INSNS 32
1252 static void build_r4000_tlb_refill_handler(void)
1254 u32 *p = tlb_handler;
1255 struct uasm_label *l = labels;
1256 struct uasm_reloc *r = relocs;
1258 unsigned int final_len;
1259 struct mips_huge_tlb_info htlb_info __maybe_unused;
1260 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1262 memset(tlb_handler, 0, sizeof(tlb_handler));
1263 memset(labels, 0, sizeof(labels));
1264 memset(relocs, 0, sizeof(relocs));
1265 memset(final_handler, 0, sizeof(final_handler));
1267 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1268 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1270 vmalloc_mode = refill_scratch;
1272 htlb_info.huge_pte = K0;
1273 htlb_info.restore_scratch = 0;
1274 htlb_info.need_reload_pte = true;
1275 vmalloc_mode = refill_noscratch;
1277 * create the plain linear handler
1279 if (bcm1250_m3_war()) {
1280 unsigned int segbits = 44;
1282 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1283 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1284 uasm_i_xor(&p, K0, K0, K1);
1285 uasm_i_dsrl_safe(&p, K1, K0, 62);
1286 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1287 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1288 uasm_i_or(&p, K0, K0, K1);
1289 uasm_il_bnez(&p, &r, K0, label_leave);
1290 /* No need for uasm_i_nop */
1294 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1296 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1299 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1300 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1303 build_get_ptep(&p, K0, K1);
1304 build_update_entries(&p, K0, K1);
1305 build_tlb_write_entry(&p, &l, &r, tlb_random);
1306 uasm_l_leave(&l, p);
1307 uasm_i_eret(&p); /* return from trap */
1309 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1310 uasm_l_tlb_huge_update(&l, p);
1311 if (htlb_info.need_reload_pte)
1312 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1313 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1314 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1315 htlb_info.restore_scratch);
1319 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1323 * Overflow check: For the 64bit handler, we need at least one
1324 * free instruction slot for the wrap-around branch. In worst
1325 * case, if the intended insertion point is a delay slot, we
1326 * need three, with the second nop'ed and the third being
1329 switch (boot_cpu_type()) {
1331 if (sizeof(long) == 4) {
1333 /* Loongson2 ebase is different than r4k, we have more space */
1334 if ((p - tlb_handler) > 64)
1335 panic("TLB refill handler space exceeded");
1337 * Now fold the handler in the TLB refill handler space.
1340 /* Simplest case, just copy the handler. */
1341 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1342 final_len = p - tlb_handler;
1345 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1346 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1347 && uasm_insn_has_bdelay(relocs,
1348 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1349 panic("TLB refill handler space exceeded");
1351 * Now fold the handler in the TLB refill handler space.
1353 f = final_handler + MIPS64_REFILL_INSNS;
1354 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1355 /* Just copy the handler. */
1356 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1357 final_len = p - tlb_handler;
1359 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1360 const enum label_id ls = label_tlb_huge_update;
1362 const enum label_id ls = label_vmalloc;
1368 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1370 BUG_ON(i == ARRAY_SIZE(labels));
1371 split = labels[i].addr;
1374 * See if we have overflown one way or the other.
1376 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1377 split < p - MIPS64_REFILL_INSNS)
1382 * Split two instructions before the end. One
1383 * for the branch and one for the instruction
1384 * in the delay slot.
1386 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1389 * If the branch would fall in a delay slot,
1390 * we must back up an additional instruction
1391 * so that it is no longer in a delay slot.
1393 if (uasm_insn_has_bdelay(relocs, split - 1))
1396 /* Copy first part of the handler. */
1397 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1398 f += split - tlb_handler;
1401 /* Insert branch. */
1402 uasm_l_split(&l, final_handler);
1403 uasm_il_b(&f, &r, label_split);
1404 if (uasm_insn_has_bdelay(relocs, split))
1407 uasm_copy_handler(relocs, labels,
1408 split, split + 1, f);
1409 uasm_move_labels(labels, f, f + 1, -1);
1415 /* Copy the rest of the handler. */
1416 uasm_copy_handler(relocs, labels, split, p, final_handler);
1417 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1424 uasm_resolve_relocs(relocs, labels);
1425 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1428 memcpy((void *)ebase, final_handler, 0x100);
1429 local_flush_icache_range(ebase, ebase + 0x100);
1431 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1434 static void setup_pw(void)
1436 unsigned long pgd_i, pgd_w;
1437 #ifndef __PAGETABLE_PMD_FOLDED
1438 unsigned long pmd_i, pmd_w;
1440 unsigned long pt_i, pt_w;
1441 unsigned long pte_i, pte_w;
1442 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1445 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
1447 pgd_i = PGDIR_SHIFT; /* 1st level PGD */
1448 #ifndef __PAGETABLE_PMD_FOLDED
1449 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
1451 pmd_i = PMD_SHIFT; /* 2nd level PMD */
1452 pmd_w = PMD_SHIFT - PAGE_SHIFT;
1454 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
1457 pt_i = PAGE_SHIFT; /* 3rd level PTE */
1458 pt_w = PAGE_SHIFT - 3;
1460 pte_i = ilog2(_PAGE_GLOBAL);
1463 #ifndef __PAGETABLE_PMD_FOLDED
1464 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
1465 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
1467 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
1468 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
1471 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1472 write_c0_pwctl(1 << 6 | psn);
1474 write_c0_kpgd(swapper_pg_dir);
1475 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
1478 static void build_loongson3_tlb_refill_handler(void)
1480 u32 *p = tlb_handler;
1481 struct uasm_label *l = labels;
1482 struct uasm_reloc *r = relocs;
1484 memset(labels, 0, sizeof(labels));
1485 memset(relocs, 0, sizeof(relocs));
1486 memset(tlb_handler, 0, sizeof(tlb_handler));
1488 if (check_for_high_segbits) {
1489 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1490 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1491 uasm_il_beqz(&p, &r, K1, label_vmalloc);
1494 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
1496 uasm_l_vmalloc(&l, p);
1499 uasm_i_dmfc0(&p, K1, C0_PGD);
1501 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
1502 #ifndef __PAGETABLE_PMD_FOLDED
1503 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
1505 uasm_i_ldpte(&p, K1, 0); /* even */
1506 uasm_i_ldpte(&p, K1, 1); /* odd */
1509 /* restore page mask */
1510 if (PM_DEFAULT_MASK >> 16) {
1511 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
1512 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
1513 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1514 } else if (PM_DEFAULT_MASK) {
1515 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
1516 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1518 uasm_i_mtc0(&p, 0, C0_PAGEMASK);
1523 if (check_for_high_segbits) {
1524 uasm_l_large_segbits_fault(&l, p);
1525 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
1530 uasm_resolve_relocs(relocs, labels);
1531 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
1532 local_flush_icache_range(ebase + 0x80, ebase + 0x100);
1533 dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32);
1536 extern u32 handle_tlbl[], handle_tlbl_end[];
1537 extern u32 handle_tlbs[], handle_tlbs_end[];
1538 extern u32 handle_tlbm[], handle_tlbm_end[];
1539 extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
1540 extern u32 tlbmiss_handler_setup_pgd_end[];
1542 static void build_setup_pgd(void)
1545 const int __maybe_unused a1 = 5;
1546 const int __maybe_unused a2 = 6;
1547 u32 *p = tlbmiss_handler_setup_pgd_start;
1548 const int tlbmiss_handler_setup_pgd_size =
1549 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1550 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1551 long pgdc = (long)pgd_current;
1554 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1555 sizeof(tlbmiss_handler_setup_pgd[0]));
1556 memset(labels, 0, sizeof(labels));
1557 memset(relocs, 0, sizeof(relocs));
1558 pgd_reg = allocate_kscratch();
1559 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1560 if (pgd_reg == -1) {
1561 struct uasm_label *l = labels;
1562 struct uasm_reloc *r = relocs;
1564 /* PGD << 11 in c0_Context */
1566 * If it is a ckseg0 address, convert to a physical
1567 * address. Shifting right by 29 and adding 4 will
1568 * result in zero for these addresses.
1571 UASM_i_SRA(&p, a1, a0, 29);
1572 UASM_i_ADDIU(&p, a1, a1, 4);
1573 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1575 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1576 uasm_l_tlbl_goaround1(&l, p);
1577 UASM_i_SLL(&p, a0, a0, 11);
1579 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1581 /* PGD in c0_KScratch */
1584 UASM_i_MTC0(&p, a0, C0_PWBASE);
1586 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1590 /* Save PGD to pgd_current[smp_processor_id()] */
1591 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1592 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1593 UASM_i_LA_mostly(&p, a2, pgdc);
1594 UASM_i_ADDU(&p, a2, a2, a1);
1595 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1597 UASM_i_LA_mostly(&p, a2, pgdc);
1598 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1602 /* if pgd_reg is allocated, save PGD also to scratch register */
1604 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1608 if (p >= tlbmiss_handler_setup_pgd_end)
1609 panic("tlbmiss_handler_setup_pgd space exceeded");
1611 uasm_resolve_relocs(relocs, labels);
1612 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1613 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1615 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1616 tlbmiss_handler_setup_pgd_size);
1620 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1623 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1625 uasm_i_lld(p, pte, 0, ptr);
1628 UASM_i_LL(p, pte, 0, ptr);
1630 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1632 uasm_i_ld(p, pte, 0, ptr);
1635 UASM_i_LW(p, pte, 0, ptr);
1640 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1641 unsigned int mode, unsigned int scratch)
1643 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1644 unsigned int swmode = mode & ~hwmode;
1646 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
1647 uasm_i_lui(p, scratch, swmode >> 16);
1648 uasm_i_or(p, pte, pte, scratch);
1649 BUG_ON(swmode & 0xffff);
1651 uasm_i_ori(p, pte, pte, mode);
1655 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1657 uasm_i_scd(p, pte, 0, ptr);
1660 UASM_i_SC(p, pte, 0, ptr);
1662 if (r10000_llsc_war())
1663 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1665 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1667 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1668 if (!cpu_has_64bits) {
1669 /* no uasm_i_nop needed */
1670 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1671 uasm_i_ori(p, pte, pte, hwmode);
1672 BUG_ON(hwmode & ~0xffff);
1673 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1674 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1675 /* no uasm_i_nop needed */
1676 uasm_i_lw(p, pte, 0, ptr);
1683 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1685 uasm_i_sd(p, pte, 0, ptr);
1688 UASM_i_SW(p, pte, 0, ptr);
1690 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1691 if (!cpu_has_64bits) {
1692 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1693 uasm_i_ori(p, pte, pte, hwmode);
1694 BUG_ON(hwmode & ~0xffff);
1695 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1696 uasm_i_lw(p, pte, 0, ptr);
1703 * Check if PTE is present, if not then jump to LABEL. PTR points to
1704 * the page table where this PTE is located, PTE will be re-loaded
1705 * with it's original value.
1708 build_pte_present(u32 **p, struct uasm_reloc **r,
1709 int pte, int ptr, int scratch, enum label_id lid)
1711 int t = scratch >= 0 ? scratch : pte;
1715 if (use_bbit_insns()) {
1716 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1719 if (_PAGE_PRESENT_SHIFT) {
1720 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1723 uasm_i_andi(p, t, cur, 1);
1724 uasm_il_beqz(p, r, t, lid);
1726 /* You lose the SMP race :-(*/
1727 iPTE_LW(p, pte, ptr);
1730 if (_PAGE_PRESENT_SHIFT) {
1731 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1734 uasm_i_andi(p, t, cur,
1735 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
1736 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
1737 uasm_il_bnez(p, r, t, lid);
1739 /* You lose the SMP race :-(*/
1740 iPTE_LW(p, pte, ptr);
1744 /* Make PTE valid, store result in PTR. */
1746 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1747 unsigned int ptr, unsigned int scratch)
1749 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1751 iPTE_SW(p, r, pte, ptr, mode, scratch);
1755 * Check if PTE can be written to, if not branch to LABEL. Regardless
1756 * restore PTE with value from PTR when done.
1759 build_pte_writable(u32 **p, struct uasm_reloc **r,
1760 unsigned int pte, unsigned int ptr, int scratch,
1763 int t = scratch >= 0 ? scratch : pte;
1766 if (_PAGE_PRESENT_SHIFT) {
1767 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1770 uasm_i_andi(p, t, cur,
1771 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1772 uasm_i_xori(p, t, t,
1773 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1774 uasm_il_bnez(p, r, t, lid);
1776 /* You lose the SMP race :-(*/
1777 iPTE_LW(p, pte, ptr);
1782 /* Make PTE writable, update software status bits as well, then store
1786 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1787 unsigned int ptr, unsigned int scratch)
1789 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1792 iPTE_SW(p, r, pte, ptr, mode, scratch);
1796 * Check if PTE can be modified, if not branch to LABEL. Regardless
1797 * restore PTE with value from PTR when done.
1800 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1801 unsigned int pte, unsigned int ptr, int scratch,
1804 if (use_bbit_insns()) {
1805 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1808 int t = scratch >= 0 ? scratch : pte;
1809 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1810 uasm_i_andi(p, t, t, 1);
1811 uasm_il_beqz(p, r, t, lid);
1813 /* You lose the SMP race :-(*/
1814 iPTE_LW(p, pte, ptr);
1818 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1822 * R3000 style TLB load/store/modify handlers.
1826 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1830 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1832 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1833 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1836 uasm_i_rfe(p); /* branch delay */
1840 * This places the pte into ENTRYLO0 and writes it with tlbwi
1841 * or tlbwr as appropriate. This is because the index register
1842 * may have the probe fail bit set as a result of a trap on a
1843 * kseg2 access, i.e. without refill. Then it returns.
1846 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1847 struct uasm_reloc **r, unsigned int pte,
1850 uasm_i_mfc0(p, tmp, C0_INDEX);
1851 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1852 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1853 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1854 uasm_i_tlbwi(p); /* cp0 delay */
1856 uasm_i_rfe(p); /* branch delay */
1857 uasm_l_r3000_write_probe_fail(l, *p);
1858 uasm_i_tlbwr(p); /* cp0 delay */
1860 uasm_i_rfe(p); /* branch delay */
1864 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1867 long pgdc = (long)pgd_current;
1869 uasm_i_mfc0(p, pte, C0_BADVADDR);
1870 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1871 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1872 uasm_i_srl(p, pte, pte, 22); /* load delay */
1873 uasm_i_sll(p, pte, pte, 2);
1874 uasm_i_addu(p, ptr, ptr, pte);
1875 uasm_i_mfc0(p, pte, C0_CONTEXT);
1876 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1877 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1878 uasm_i_addu(p, ptr, ptr, pte);
1879 uasm_i_lw(p, pte, 0, ptr);
1880 uasm_i_tlbp(p); /* load delay */
1883 static void build_r3000_tlb_load_handler(void)
1885 u32 *p = handle_tlbl;
1886 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1887 struct uasm_label *l = labels;
1888 struct uasm_reloc *r = relocs;
1890 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1891 memset(labels, 0, sizeof(labels));
1892 memset(relocs, 0, sizeof(relocs));
1894 build_r3000_tlbchange_handler_head(&p, K0, K1);
1895 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1896 uasm_i_nop(&p); /* load delay */
1897 build_make_valid(&p, &r, K0, K1, -1);
1898 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1900 uasm_l_nopage_tlbl(&l, p);
1901 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1904 if (p >= handle_tlbl_end)
1905 panic("TLB load handler fastpath space exceeded");
1907 uasm_resolve_relocs(relocs, labels);
1908 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1909 (unsigned int)(p - handle_tlbl));
1911 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1914 static void build_r3000_tlb_store_handler(void)
1916 u32 *p = handle_tlbs;
1917 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1918 struct uasm_label *l = labels;
1919 struct uasm_reloc *r = relocs;
1921 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1922 memset(labels, 0, sizeof(labels));
1923 memset(relocs, 0, sizeof(relocs));
1925 build_r3000_tlbchange_handler_head(&p, K0, K1);
1926 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1927 uasm_i_nop(&p); /* load delay */
1928 build_make_write(&p, &r, K0, K1, -1);
1929 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1931 uasm_l_nopage_tlbs(&l, p);
1932 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1935 if (p >= handle_tlbs_end)
1936 panic("TLB store handler fastpath space exceeded");
1938 uasm_resolve_relocs(relocs, labels);
1939 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1940 (unsigned int)(p - handle_tlbs));
1942 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1945 static void build_r3000_tlb_modify_handler(void)
1947 u32 *p = handle_tlbm;
1948 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1949 struct uasm_label *l = labels;
1950 struct uasm_reloc *r = relocs;
1952 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1953 memset(labels, 0, sizeof(labels));
1954 memset(relocs, 0, sizeof(relocs));
1956 build_r3000_tlbchange_handler_head(&p, K0, K1);
1957 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1958 uasm_i_nop(&p); /* load delay */
1959 build_make_write(&p, &r, K0, K1, -1);
1960 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1962 uasm_l_nopage_tlbm(&l, p);
1963 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1966 if (p >= handle_tlbm_end)
1967 panic("TLB modify handler fastpath space exceeded");
1969 uasm_resolve_relocs(relocs, labels);
1970 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1971 (unsigned int)(p - handle_tlbm));
1973 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1975 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1978 * R4000 style TLB load/store/modify handlers.
1980 static struct work_registers
1981 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1982 struct uasm_reloc **r)
1984 struct work_registers wr = build_get_work_registers(p);
1987 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1989 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1992 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1994 * For huge tlb entries, pmd doesn't contain an address but
1995 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1996 * see if we need to jump to huge tlb processing.
1998 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
2001 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
2002 UASM_i_LW(p, wr.r2, 0, wr.r2);
2003 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
2004 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
2005 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
2008 uasm_l_smp_pgtable_change(l, *p);
2010 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
2011 if (!m4kc_tlbp_war()) {
2012 build_tlb_probe_entry(p);
2014 /* race condition happens, leaving */
2016 uasm_i_mfc0(p, wr.r3, C0_INDEX);
2017 uasm_il_bltz(p, r, wr.r3, label_leave);
2025 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
2026 struct uasm_reloc **r, unsigned int tmp,
2029 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
2030 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
2031 build_update_entries(p, tmp, ptr);
2032 build_tlb_write_entry(p, l, r, tlb_indexed);
2033 uasm_l_leave(l, *p);
2034 build_restore_work_registers(p);
2035 uasm_i_eret(p); /* return from trap */
2038 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
2042 static void build_r4000_tlb_load_handler(void)
2044 u32 *p = handle_tlbl;
2045 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
2046 struct uasm_label *l = labels;
2047 struct uasm_reloc *r = relocs;
2048 struct work_registers wr;
2050 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
2051 memset(labels, 0, sizeof(labels));
2052 memset(relocs, 0, sizeof(relocs));
2054 if (bcm1250_m3_war()) {
2055 unsigned int segbits = 44;
2057 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
2058 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
2059 uasm_i_xor(&p, K0, K0, K1);
2060 uasm_i_dsrl_safe(&p, K1, K0, 62);
2061 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
2062 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
2063 uasm_i_or(&p, K0, K0, K1);
2064 uasm_il_bnez(&p, &r, K0, label_leave);
2065 /* No need for uasm_i_nop */
2068 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2069 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2070 if (m4kc_tlbp_war())
2071 build_tlb_probe_entry(&p);
2073 if (cpu_has_rixi && !cpu_has_rixiex) {
2075 * If the page is not _PAGE_VALID, RI or XI could not
2076 * have triggered it. Skip the expensive test..
2078 if (use_bbit_insns()) {
2079 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2080 label_tlbl_goaround1);
2082 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2083 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
2089 switch (current_cpu_type()) {
2091 if (cpu_has_mips_r2_exec_hazard) {
2094 case CPU_CAVIUM_OCTEON:
2095 case CPU_CAVIUM_OCTEON_PLUS:
2096 case CPU_CAVIUM_OCTEON2:
2101 /* Examine entrylo 0 or 1 based on ptr. */
2102 if (use_bbit_insns()) {
2103 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2105 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2106 uasm_i_beqz(&p, wr.r3, 8);
2108 /* load it in the delay slot*/
2109 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2110 /* load it if ptr is odd */
2111 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2113 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2114 * XI must have triggered it.
2116 if (use_bbit_insns()) {
2117 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2119 uasm_l_tlbl_goaround1(&l, p);
2121 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2122 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2125 uasm_l_tlbl_goaround1(&l, p);
2127 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
2128 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2130 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2132 * This is the entry point when build_r4000_tlbchange_handler_head
2133 * spots a huge page.
2135 uasm_l_tlb_huge_update(&l, p);
2136 iPTE_LW(&p, wr.r1, wr.r2);
2137 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2138 build_tlb_probe_entry(&p);
2140 if (cpu_has_rixi && !cpu_has_rixiex) {
2142 * If the page is not _PAGE_VALID, RI or XI could not
2143 * have triggered it. Skip the expensive test..
2145 if (use_bbit_insns()) {
2146 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2147 label_tlbl_goaround2);
2149 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2150 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2156 switch (current_cpu_type()) {
2158 if (cpu_has_mips_r2_exec_hazard) {
2161 case CPU_CAVIUM_OCTEON:
2162 case CPU_CAVIUM_OCTEON_PLUS:
2163 case CPU_CAVIUM_OCTEON2:
2168 /* Examine entrylo 0 or 1 based on ptr. */
2169 if (use_bbit_insns()) {
2170 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2172 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2173 uasm_i_beqz(&p, wr.r3, 8);
2175 /* load it in the delay slot*/
2176 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2177 /* load it if ptr is odd */
2178 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2180 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2181 * XI must have triggered it.
2183 if (use_bbit_insns()) {
2184 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2186 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2187 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2189 if (PM_DEFAULT_MASK == 0)
2192 * We clobbered C0_PAGEMASK, restore it. On the other branch
2193 * it is restored in build_huge_tlb_write_entry.
2195 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2197 uasm_l_tlbl_goaround2(&l, p);
2199 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2200 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2203 uasm_l_nopage_tlbl(&l, p);
2204 build_restore_work_registers(&p);
2205 #ifdef CONFIG_CPU_MICROMIPS
2206 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2207 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2208 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2212 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2215 if (p >= handle_tlbl_end)
2216 panic("TLB load handler fastpath space exceeded");
2218 uasm_resolve_relocs(relocs, labels);
2219 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2220 (unsigned int)(p - handle_tlbl));
2222 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2225 static void build_r4000_tlb_store_handler(void)
2227 u32 *p = handle_tlbs;
2228 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2229 struct uasm_label *l = labels;
2230 struct uasm_reloc *r = relocs;
2231 struct work_registers wr;
2233 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2234 memset(labels, 0, sizeof(labels));
2235 memset(relocs, 0, sizeof(relocs));
2237 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2238 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2239 if (m4kc_tlbp_war())
2240 build_tlb_probe_entry(&p);
2241 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2242 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2244 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2246 * This is the entry point when
2247 * build_r4000_tlbchange_handler_head spots a huge page.
2249 uasm_l_tlb_huge_update(&l, p);
2250 iPTE_LW(&p, wr.r1, wr.r2);
2251 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2252 build_tlb_probe_entry(&p);
2253 uasm_i_ori(&p, wr.r1, wr.r1,
2254 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2255 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2258 uasm_l_nopage_tlbs(&l, p);
2259 build_restore_work_registers(&p);
2260 #ifdef CONFIG_CPU_MICROMIPS
2261 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2262 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2263 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2267 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2270 if (p >= handle_tlbs_end)
2271 panic("TLB store handler fastpath space exceeded");
2273 uasm_resolve_relocs(relocs, labels);
2274 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2275 (unsigned int)(p - handle_tlbs));
2277 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2280 static void build_r4000_tlb_modify_handler(void)
2282 u32 *p = handle_tlbm;
2283 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2284 struct uasm_label *l = labels;
2285 struct uasm_reloc *r = relocs;
2286 struct work_registers wr;
2288 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2289 memset(labels, 0, sizeof(labels));
2290 memset(relocs, 0, sizeof(relocs));
2292 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2293 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2294 if (m4kc_tlbp_war())
2295 build_tlb_probe_entry(&p);
2296 /* Present and writable bits set, set accessed and dirty bits. */
2297 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2298 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2300 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2302 * This is the entry point when
2303 * build_r4000_tlbchange_handler_head spots a huge page.
2305 uasm_l_tlb_huge_update(&l, p);
2306 iPTE_LW(&p, wr.r1, wr.r2);
2307 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2308 build_tlb_probe_entry(&p);
2309 uasm_i_ori(&p, wr.r1, wr.r1,
2310 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2311 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2314 uasm_l_nopage_tlbm(&l, p);
2315 build_restore_work_registers(&p);
2316 #ifdef CONFIG_CPU_MICROMIPS
2317 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2318 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2319 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2323 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2326 if (p >= handle_tlbm_end)
2327 panic("TLB modify handler fastpath space exceeded");
2329 uasm_resolve_relocs(relocs, labels);
2330 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2331 (unsigned int)(p - handle_tlbm));
2333 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2336 static void flush_tlb_handlers(void)
2338 local_flush_icache_range((unsigned long)handle_tlbl,
2339 (unsigned long)handle_tlbl_end);
2340 local_flush_icache_range((unsigned long)handle_tlbs,
2341 (unsigned long)handle_tlbs_end);
2342 local_flush_icache_range((unsigned long)handle_tlbm,
2343 (unsigned long)handle_tlbm_end);
2344 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2345 (unsigned long)tlbmiss_handler_setup_pgd_end);
2348 static void print_htw_config(void)
2350 unsigned long config;
2352 const int field = 2 * sizeof(unsigned long);
2354 config = read_c0_pwfield();
2355 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2357 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2358 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2359 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2360 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2361 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2363 config = read_c0_pwsize();
2364 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2366 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
2367 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2368 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2369 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2370 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2371 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2373 pwctl = read_c0_pwctl();
2374 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2376 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2377 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2378 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2379 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
2380 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2381 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2382 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2385 static void config_htw_params(void)
2387 unsigned long pwfield, pwsize, ptei;
2388 unsigned int config;
2391 * We are using 2-level page tables, so we only need to
2392 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2393 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2394 * write values less than 0xc in these fields because the entire
2395 * write will be dropped. As a result of which, we must preserve
2396 * the original reset values and overwrite only what we really want.
2399 pwfield = read_c0_pwfield();
2400 /* re-initialize the GDI field */
2401 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2402 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2403 /* re-initialize the PTI field including the even/odd bit */
2404 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2405 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2406 if (CONFIG_PGTABLE_LEVELS >= 3) {
2407 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2408 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2410 /* Set the PTEI right shift */
2411 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2413 write_c0_pwfield(pwfield);
2414 /* Check whether the PTEI value is supported */
2415 back_to_back_c0_hazard();
2416 pwfield = read_c0_pwfield();
2417 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2419 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2422 * Drop option to avoid HTW being enabled via another path
2425 current_cpu_data.options &= ~MIPS_CPU_HTW;
2429 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2430 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2431 if (CONFIG_PGTABLE_LEVELS >= 3)
2432 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2434 /* Set pointer size to size of directory pointers */
2435 if (IS_ENABLED(CONFIG_64BIT))
2436 pwsize |= MIPS_PWSIZE_PS_MASK;
2437 /* PTEs may be multiple pointers long (e.g. with XPA) */
2438 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2439 & MIPS_PWSIZE_PTEW_MASK;
2441 write_c0_pwsize(pwsize);
2443 /* Make sure everything is set before we enable the HTW */
2444 back_to_back_c0_hazard();
2447 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2450 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2451 if (IS_ENABLED(CONFIG_64BIT))
2452 config |= MIPS_PWCTL_XU_MASK;
2453 write_c0_pwctl(config);
2454 pr_info("Hardware Page Table Walker enabled\n");
2459 static void config_xpa_params(void)
2462 unsigned int pagegrain;
2464 if (mips_xpa_disabled) {
2465 pr_info("Extended Physical Addressing (XPA) disabled\n");
2469 pagegrain = read_c0_pagegrain();
2470 write_c0_pagegrain(pagegrain | PG_ELPA);
2471 back_to_back_c0_hazard();
2472 pagegrain = read_c0_pagegrain();
2474 if (pagegrain & PG_ELPA)
2475 pr_info("Extended Physical Addressing (XPA) enabled\n");
2477 panic("Extended Physical Addressing (XPA) disabled");
2481 static void check_pabits(void)
2483 unsigned long entry;
2484 unsigned pabits, fillbits;
2486 if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2488 * We'll only be making use of the fact that we can rotate bits
2489 * into the fill if the CPU supports RIXI, so don't bother
2490 * probing this for CPUs which don't.
2495 write_c0_entrylo0(~0ul);
2496 back_to_back_c0_hazard();
2497 entry = read_c0_entrylo0();
2499 /* clear all non-PFN bits */
2500 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2501 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2503 /* find a lower bound on PABITS, and upper bound on fill bits */
2504 pabits = fls_long(entry) + 6;
2505 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2507 /* minus the RI & XI bits */
2508 fillbits -= min_t(unsigned, fillbits, 2);
2510 if (fillbits >= ilog2(_PAGE_NO_EXEC))
2511 fill_includes_sw_bits = true;
2513 pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2516 void build_tlb_refill_handler(void)
2519 * The refill handler is generated per-CPU, multi-node systems
2520 * may have local storage for it. The other handlers are only
2523 static int run_once = 0;
2525 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
2526 panic("Kernels supporting XPA currently require CPUs with RIXI");
2528 output_pgtable_bits_defines();
2532 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2535 switch (current_cpu_type()) {
2543 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2544 if (cpu_has_local_ebase)
2545 build_r3000_tlb_refill_handler();
2547 if (!cpu_has_local_ebase)
2548 build_r3000_tlb_refill_handler();
2550 build_r3000_tlb_load_handler();
2551 build_r3000_tlb_store_handler();
2552 build_r3000_tlb_modify_handler();
2553 flush_tlb_handlers();
2557 panic("No R3000 TLB refill handler");
2563 panic("No R6000 TLB refill handler yet");
2567 panic("No R8000 TLB refill handler yet");
2575 scratch_reg = allocate_kscratch();
2577 build_r4000_tlb_load_handler();
2578 build_r4000_tlb_store_handler();
2579 build_r4000_tlb_modify_handler();
2581 build_loongson3_tlb_refill_handler();
2582 else if (!cpu_has_local_ebase)
2583 build_r4000_tlb_refill_handler();
2584 flush_tlb_handlers();
2587 if (cpu_has_local_ebase)
2588 build_r4000_tlb_refill_handler();
2590 config_xpa_params();
2592 config_htw_params();