2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
37 #define IMM_MASK 0xffff
39 #define JIMM_MASK 0x3ffffff
41 #define FUNC_MASK 0x3f
46 #define SIMM9_MASK 0x1ff
50 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
51 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
52 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
53 insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
54 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
55 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
56 insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
57 insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,
58 insn_mthc0, insn_mul, insn_or, insn_ori, insn_pref, insn_rfe,
59 insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_slt,
60 insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu,
61 insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi,
62 insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield,
63 insn_lddir, insn_ldpte,
72 static inline u32 build_rs(u32 arg)
74 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
76 return (arg & RS_MASK) << RS_SH;
79 static inline u32 build_rt(u32 arg)
81 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
83 return (arg & RT_MASK) << RT_SH;
86 static inline u32 build_rd(u32 arg)
88 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
90 return (arg & RD_MASK) << RD_SH;
93 static inline u32 build_re(u32 arg)
95 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
97 return (arg & RE_MASK) << RE_SH;
100 static inline u32 build_simm(s32 arg)
102 WARN(arg > 0x7fff || arg < -0x8000,
103 KERN_WARNING "Micro-assembler field overflow\n");
108 static inline u32 build_uimm(u32 arg)
110 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
112 return arg & IMM_MASK;
115 static inline u32 build_scimm(u32 arg)
117 WARN(arg & ~SCIMM_MASK,
118 KERN_WARNING "Micro-assembler field overflow\n");
120 return (arg & SCIMM_MASK) << SCIMM_SH;
123 static inline u32 build_scimm9(s32 arg)
125 WARN((arg > 0xff || arg < -0x100),
126 KERN_WARNING "Micro-assembler field overflow\n");
128 return (arg & SIMM9_MASK) << SIMM9_SH;
131 static inline u32 build_func(u32 arg)
133 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
135 return arg & FUNC_MASK;
138 static inline u32 build_set(u32 arg)
140 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
142 return arg & SET_MASK;
145 static void build_insn(u32 **buf, enum opcode opc, ...);
147 #define I_u1u2u3(op) \
150 build_insn(buf, insn##op, a, b, c); \
152 UASM_EXPORT_SYMBOL(uasm_i##op);
154 #define I_s3s1s2(op) \
157 build_insn(buf, insn##op, b, c, a); \
159 UASM_EXPORT_SYMBOL(uasm_i##op);
161 #define I_u2u1u3(op) \
164 build_insn(buf, insn##op, b, a, c); \
166 UASM_EXPORT_SYMBOL(uasm_i##op);
168 #define I_u3u2u1(op) \
171 build_insn(buf, insn##op, c, b, a); \
173 UASM_EXPORT_SYMBOL(uasm_i##op);
175 #define I_u3u1u2(op) \
178 build_insn(buf, insn##op, b, c, a); \
180 UASM_EXPORT_SYMBOL(uasm_i##op);
182 #define I_u1u2s3(op) \
185 build_insn(buf, insn##op, a, b, c); \
187 UASM_EXPORT_SYMBOL(uasm_i##op);
189 #define I_u2s3u1(op) \
192 build_insn(buf, insn##op, c, a, b); \
194 UASM_EXPORT_SYMBOL(uasm_i##op);
196 #define I_u2u1s3(op) \
199 build_insn(buf, insn##op, b, a, c); \
201 UASM_EXPORT_SYMBOL(uasm_i##op);
203 #define I_u2u1msbu3(op) \
206 build_insn(buf, insn##op, b, a, c+d-1, c); \
208 UASM_EXPORT_SYMBOL(uasm_i##op);
210 #define I_u2u1msb32u3(op) \
213 build_insn(buf, insn##op, b, a, c+d-33, c); \
215 UASM_EXPORT_SYMBOL(uasm_i##op);
217 #define I_u2u1msbdu3(op) \
220 build_insn(buf, insn##op, b, a, d-1, c); \
222 UASM_EXPORT_SYMBOL(uasm_i##op);
227 build_insn(buf, insn##op, a, b); \
229 UASM_EXPORT_SYMBOL(uasm_i##op);
234 build_insn(buf, insn##op, b, a); \
236 UASM_EXPORT_SYMBOL(uasm_i##op);
241 build_insn(buf, insn##op, a, b); \
243 UASM_EXPORT_SYMBOL(uasm_i##op);
248 build_insn(buf, insn##op, a); \
250 UASM_EXPORT_SYMBOL(uasm_i##op);
255 build_insn(buf, insn##op); \
257 UASM_EXPORT_SYMBOL(uasm_i##op);
333 I_u2u1msb32u3(_dinsm);
342 #ifdef CONFIG_CPU_CAVIUM_OCTEON
343 #include <asm/octeon/octeon.h>
344 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
347 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
349 * As per erratum Core-14449, replace prefetches 0-4,
350 * 6-24 with 'pref 28'.
352 build_insn(buf, insn_pref, c, 28, b);
354 build_insn(buf, insn_pref, c, a, b);
356 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
362 void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
368 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
370 int ISAFUNC(uasm_in_compat_space_p)(long addr)
372 /* Is this address in 32bit compat space? */
374 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
379 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
381 static int uasm_rel_highest(long val)
384 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
390 static int uasm_rel_higher(long val)
393 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
399 int ISAFUNC(uasm_rel_hi)(long val)
401 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
403 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
405 int ISAFUNC(uasm_rel_lo)(long val)
407 return ((val & 0xffff) ^ 0x8000) - 0x8000;
409 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
411 void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
413 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
414 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
415 if (uasm_rel_higher(addr))
416 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
417 if (ISAFUNC(uasm_rel_hi(addr))) {
418 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
419 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
420 ISAFUNC(uasm_rel_hi)(addr));
421 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
423 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
425 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
427 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
429 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
431 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
432 if (ISAFUNC(uasm_rel_lo(addr))) {
433 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
434 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
435 ISAFUNC(uasm_rel_lo(addr)));
437 ISAFUNC(uasm_i_addiu)(buf, rs, rs,
438 ISAFUNC(uasm_rel_lo(addr)));
441 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
443 /* Handle relocations. */
444 void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
447 (*rel)->type = R_MIPS_PC16;
451 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
453 static inline void __resolve_relocs(struct uasm_reloc *rel,
454 struct uasm_label *lab);
456 void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
457 struct uasm_label *lab)
459 struct uasm_label *l;
461 for (; rel->lab != UASM_LABEL_INVALID; rel++)
462 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
463 if (rel->lab == l->lab)
464 __resolve_relocs(rel, l);
466 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
468 void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
471 for (; rel->lab != UASM_LABEL_INVALID; rel++)
472 if (rel->addr >= first && rel->addr < end)
475 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
477 void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
480 for (; lab->lab != UASM_LABEL_INVALID; lab++)
481 if (lab->addr >= first && lab->addr < end)
484 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
486 void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
487 u32 *first, u32 *end, u32 *target)
489 long off = (long)(target - first);
491 memcpy(target, first, (end - first) * sizeof(u32));
493 ISAFUNC(uasm_move_relocs(rel, first, end, off));
494 ISAFUNC(uasm_move_labels(lab, first, end, off));
496 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
498 int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
500 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
501 if (rel->addr == addr
502 && (rel->type == R_MIPS_PC16
503 || rel->type == R_MIPS_26))
509 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
511 /* Convenience functions for labeled branches. */
512 void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
515 uasm_r_mips_pc16(r, *p, lid);
516 ISAFUNC(uasm_i_bltz)(p, reg, 0);
518 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
520 void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
522 uasm_r_mips_pc16(r, *p, lid);
523 ISAFUNC(uasm_i_b)(p, 0);
525 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
527 void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
528 unsigned int r2, int lid)
530 uasm_r_mips_pc16(r, *p, lid);
531 ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
533 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
535 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
538 uasm_r_mips_pc16(r, *p, lid);
539 ISAFUNC(uasm_i_beqz)(p, reg, 0);
541 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
543 void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
546 uasm_r_mips_pc16(r, *p, lid);
547 ISAFUNC(uasm_i_beqzl)(p, reg, 0);
549 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
551 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
552 unsigned int reg2, int lid)
554 uasm_r_mips_pc16(r, *p, lid);
555 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
557 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
559 void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
562 uasm_r_mips_pc16(r, *p, lid);
563 ISAFUNC(uasm_i_bnez)(p, reg, 0);
565 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
567 void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
570 uasm_r_mips_pc16(r, *p, lid);
571 ISAFUNC(uasm_i_bgezl)(p, reg, 0);
573 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
575 void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
578 uasm_r_mips_pc16(r, *p, lid);
579 ISAFUNC(uasm_i_bgez)(p, reg, 0);
581 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
583 void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
584 unsigned int bit, int lid)
586 uasm_r_mips_pc16(r, *p, lid);
587 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
589 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
591 void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
592 unsigned int bit, int lid)
594 uasm_r_mips_pc16(r, *p, lid);
595 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
597 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));