arch/mips/mti-malta/malta-init.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * PROM library initialisation code.
   7  *
   8  * Copyright (C) 1999,2000,2004,2005,2012  MIPS Technologies, Inc.
   9  * All rights reserved.
  10  * Authors: Carsten Langgaard <carstenl@mips.com>
  11  *         Maciej W. Rozycki <macro@mips.com>
  12  *          Steven J. Hill <sjhill@mips.com>
  13  */
  14 #include <linux/init.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci_regs.h>
  18 #include <linux/serial_core.h>
  19
  20 #include <asm/cacheflush.h>
  21 #include <asm/smp-ops.h>
  22 #include <asm/traps.h>
  23 #include <asm/fw/fw.h>
  24 #include <asm/mips-cm.h>
  25 #include <asm/mips-cpc.h>
  26 #include <asm/mips-boards/generic.h>
  27 #include <asm/mips-boards/malta.h>
  28
  29 static int mips_revision_corid;
  30 int mips_revision_sconid;
  31
  32 /* Bonito64 system controller register base. */
  33 unsigned long _pcictrl_bonito;
  34 unsigned long _pcictrl_bonito_pcicfg;
  35
  36 /* GT64120 system controller register base */
  37 unsigned long _pcictrl_gt64120;
  38
  39 /* MIPS System controller register base */
  40 unsigned long _pcictrl_msc;
  41
  42 #ifdef CONFIG_SERIAL_8250_CONSOLE
  43 static void __init console_config(void)
  44 {
  45         char console_string[40];
  46         int baud = 0;
  47         char parity = '\0', bits = '\0', flow = '\0';
  48         char *s;
  49
  50         s = fw_getenv("modetty0");
  51         if (s) {
  52                 while (*s >= '0' && *s <= '9')
  53                         baud = baud*10 + *s++ - '0';
  54                 if (*s == ',')
  55                         s++;
  56                 if (*s)
  57                         parity = *s++;
  58                 if (*s == ',')
  59                         s++;
  60                 if (*s)
  61                         bits = *s++;
  62                 if (*s == ',')
  63                         s++;
  64                 if (*s == 'h')
  65                         flow = 'r';
  66         }
  67         if (baud == 0)
  68                 baud = 38400;
  69         if (parity != 'n' && parity != 'o' && parity != 'e')
  70                 parity = 'n';
  71         if (bits != '7' && bits != '8')
  72                 bits = '8';
  73         if (flow == '\0')
  74                 flow = 'r';
  75
  76         if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) {
  77                 sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud,
  78                         parity, bits);
  79                 setup_earlycon(console_string);
  80         }
  81
  82         if ((strstr(fw_getcmdline(), "console=")) == NULL) {
  83                 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
  84                         parity, bits, flow);
  85                 strcat(fw_getcmdline(), console_string);
  86                 pr_info("Config serial console:%s\n", console_string);
  87         }
  88 }
  89 #endif
  90
  91 static void __init mips_nmi_setup(void)
  92 {
  93         void *base;
  94         extern char except_vec_nmi;
  95
  96         base = cpu_has_veic ?
  97                 (void *)(CAC_BASE + 0xa80) :
  98                 (void *)(CAC_BASE + 0x380);
  99         memcpy(base, &except_vec_nmi, 0x80);
 100         flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 101 }
 102
 103 static void __init mips_ejtag_setup(void)
 104 {
 105         void *base;
 106         extern char except_vec_ejtag_debug;
 107
 108         base = cpu_has_veic ?
 109                 (void *)(CAC_BASE + 0xa00) :
 110                 (void *)(CAC_BASE + 0x300);
 111         memcpy(base, &except_vec_ejtag_debug, 0x80);
 112         flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 113 }
 114
 115 phys_addr_t mips_cpc_default_phys_base(void)
 116 {
 117         return CPC_BASE_ADDR;
 118 }
 119
 120 void __init prom_init(void)
 121 {
 122         mips_display_message("LINUX");
 123
 124         /*
 125          * early setup of _pcictrl_bonito so that we can determine
 126          * the system controller on a CORE_EMUL board
 127          */
 128         _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
 129
 130         mips_revision_corid = MIPS_REVISION_CORID;
 131
 132         if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
 133                 if (BONITO_PCIDID == 0x0001df53 ||
 134                     BONITO_PCIDID == 0x0003df53)
 135                         mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
 136                 else
 137                         mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
 138         }
 139
 140         mips_revision_sconid = MIPS_REVISION_SCONID;
 141         if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
 142                 switch (mips_revision_corid) {
 143                 case MIPS_REVISION_CORID_QED_RM5261:
 144                 case MIPS_REVISION_CORID_CORE_LV:
 145                 case MIPS_REVISION_CORID_CORE_FPGA:
 146                 case MIPS_REVISION_CORID_CORE_FPGAR2:
 147                         mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
 148                         break;
 149                 case MIPS_REVISION_CORID_CORE_EMUL_BON:
 150                 case MIPS_REVISION_CORID_BONITO64:
 151                 case MIPS_REVISION_CORID_CORE_20K:
 152                         mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
 153                         break;
 154                 case MIPS_REVISION_CORID_CORE_MSC:
 155                 case MIPS_REVISION_CORID_CORE_FPGA2:
 156                 case MIPS_REVISION_CORID_CORE_24K:
 157                         /*
 158                          * SOCit/ROCit support is essentially identical
 159                          * but make an attempt to distinguish them
 160                          */
 161                         mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
 162                         break;
 163                 case MIPS_REVISION_CORID_CORE_FPGA3:
 164                 case MIPS_REVISION_CORID_CORE_FPGA4:
 165                 case MIPS_REVISION_CORID_CORE_FPGA5:
 166                 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 167                 default:
 168                         /* See above */
 169                         mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
 170                         break;
 171                 }
 172         }
 173
 174         switch (mips_revision_sconid) {
 175                 u32 start, map, mask, data;
 176
 177         case MIPS_REVISION_SCON_GT64120:
 178                 /*
 179                  * Setup the North bridge to do Master byte-lane swapping
 180                  * when running in bigendian.
 181                  */
 182                 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
 183
 184 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 185                 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
 186                          GT_PCI0_CMD_SBYTESWAP_BIT);
 187 #else
 188                 GT_WRITE(GT_PCI0_CMD_OFS, 0);
 189 #endif
 190                 /* Fix up PCI I/O mapping if necessary (for Atlas).  */
 191                 start = GT_READ(GT_PCI0IOLD_OFS);
 192                 map = GT_READ(GT_PCI0IOREMAP_OFS);
 193                 if ((start & map) != 0) {
 194                         map &= ~start;
 195                         GT_WRITE(GT_PCI0IOREMAP_OFS, map);
 196                 }
 197
 198                 set_io_port_base(MALTA_GT_PORT_BASE);
 199                 break;
 200
 201         case MIPS_REVISION_SCON_BONITO:
 202                 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
 203
 204                 /*
 205                  * Disable Bonito IOBC.
 206                  */
 207                 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 208                         ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 209                           BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 210
 211                 /*
 212                  * Setup the North bridge to do Master byte-lane swapping
 213                  * when running in bigendian.
 214                  */
 215 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 216                 BONITO_BONGENCFG = BONITO_BONGENCFG &
 217                         ~(BONITO_BONGENCFG_MSTRBYTESWAP |
 218                           BONITO_BONGENCFG_BYTESWAP);
 219 #else
 220                 BONITO_BONGENCFG = BONITO_BONGENCFG |
 221                         BONITO_BONGENCFG_MSTRBYTESWAP |
 222                         BONITO_BONGENCFG_BYTESWAP;
 223 #endif
 224
 225                 set_io_port_base(MALTA_BONITO_PORT_BASE);
 226                 break;
 227
 228         case MIPS_REVISION_SCON_SOCIT:
 229         case MIPS_REVISION_SCON_ROCIT:
 230                 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
 231 mips_pci_controller:
 232                 mb();
 233                 MSC_READ(MSC01_PCI_CFG, data);
 234                 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
 235                 wmb();
 236
 237                 /* Fix up lane swapping.  */
 238 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 239                 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
 240 #else
 241                 MSC_WRITE(MSC01_PCI_SWAP,
 242                           MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
 243                           MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
 244                           MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
 245 #endif
 246
 247                 /*
 248                  * Setup the Malta max (2GB) memory for PCI DMA in host bridge
 249                  * in transparent addressing mode.
 250                  */
 251                 mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH;
 252                 MSC_WRITE(MSC01_PCI_BAR0, mask);
 253                 MSC_WRITE(MSC01_PCI_HEAD4, mask);
 254
 255                 mask &= MSC01_PCI_BAR0_SIZE_MSK;
 256                 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
 257                 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
 258
 259                 /* Don't handle target retries indefinitely.  */
 260                 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
 261                     MSC01_PCI_CFG_MAXRTRY_MSK)
 262                         data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
 263                                          MSC01_PCI_CFG_MAXRTRY_SHF)) |
 264                                ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
 265                                 MSC01_PCI_CFG_MAXRTRY_SHF);
 266
 267                 wmb();
 268                 MSC_WRITE(MSC01_PCI_CFG, data);
 269                 mb();
 270
 271                 set_io_port_base(MALTA_MSC_PORT_BASE);
 272                 break;
 273
 274         case MIPS_REVISION_SCON_SOCITSC:
 275         case MIPS_REVISION_SCON_SOCITSCP:
 276                 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
 277                 goto mips_pci_controller;
 278
 279         default:
 280                 /* Unknown system controller */
 281                 mips_display_message("SC Error");
 282                 while (1);      /* We die here... */
 283         }
 284         board_nmi_handler_setup = mips_nmi_setup;
 285         board_ejtag_handler_setup = mips_ejtag_setup;
 286
 287         fw_init_cmdline();
 288         fw_meminit();
 289 #ifdef CONFIG_SERIAL_8250_CONSOLE
 290         console_config();
 291 #endif
 292         /* Early detection of CMP support */
 293         mips_cpc_probe();
 294
 295         if (!register_cps_smp_ops())
 296                 return;
 297         if (!register_cmp_smp_ops())
 298                 return;
 299         if (!register_vsmp_smp_ops())
 300                 return;
 301         register_up_smp_ops();
 302 }