2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 * Routines for generic manipulation of the interrupts found on the MIPS
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
24 #include <linux/init.h>
25 #include <linux/irq.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/kernel.h>
32 #include <linux/random.h>
34 #include <asm/traps.h>
35 #include <asm/i8259.h>
36 #include <asm/irq_cpu.h>
37 #include <asm/irq_regs.h>
38 #include <asm/mips-boards/malta.h>
39 #include <asm/mips-boards/maltaint.h>
40 #include <asm/gt64120.h>
41 #include <asm/mips-boards/generic.h>
42 #include <asm/mips-boards/msc01_pci.h>
43 #include <asm/msc01_ic.h>
45 #include <asm/gcmpregs.h>
46 #include <asm/setup.h>
48 int gcmp_present = -1;
49 static unsigned long _msc01_biu_base;
50 static unsigned long _gcmp_base;
51 static unsigned int ipi_map[NR_CPUS];
53 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
55 static inline int mips_pcibios_iack(void)
60 * Determine highest priority pending interrupt by performing
61 * a PCI Interrupt Acknowledge cycle.
63 switch (mips_revision_sconid) {
64 case MIPS_REVISION_SCON_SOCIT:
65 case MIPS_REVISION_SCON_ROCIT:
66 case MIPS_REVISION_SCON_SOCITSC:
67 case MIPS_REVISION_SCON_SOCITSCP:
68 MSC_READ(MSC01_PCI_IACK, irq);
71 case MIPS_REVISION_SCON_GT64120:
72 irq = GT_READ(GT_PCI0_IACK_OFS);
75 case MIPS_REVISION_SCON_BONITO:
76 /* The following will generate a PCI IACK cycle on the
77 * Bonito controller. It's a little bit kludgy, but it
78 * was the easiest way to implement it in hardware at
81 BONITO_PCIMAP_CFG = 0x20000;
83 /* Flush Bonito register block */
84 (void) BONITO_PCIMAP_CFG;
87 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
90 BONITO_PCIMAP_CFG = 0;
93 printk(KERN_WARNING "Unknown system controller.\n");
99 static inline int get_int(void)
103 raw_spin_lock_irqsave(&mips_irq_lock, flags);
105 irq = mips_pcibios_iack();
108 * The only way we can decide if an interrupt is spurious
109 * is by checking the 8259 registers. This needs a spinlock
110 * on an SMP system, so leave it up to the generic code...
113 raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
118 static void malta_hw0_irqdispatch(void)
124 /* interrupt has already been cleared */
128 do_IRQ(MALTA_INT_BASE + irq);
131 static void malta_ipi_irqdispatch(void)
135 if (gic_compare_int())
136 do_IRQ(MIPS_GIC_IRQ_BASE);
140 return; /* interrupt has already been cleared */
142 do_IRQ(MIPS_GIC_IRQ_BASE + irq);
145 static void corehi_irqdispatch(void)
147 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
148 unsigned int pcimstat, intisr, inten, intpol;
149 unsigned int intrcause, datalo, datahi;
150 struct pt_regs *regs = get_irq_regs();
152 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
153 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
154 "Cause : %08lx\nbadVaddr : %08lx\n",
155 regs->cp0_epc, regs->cp0_status,
156 regs->cp0_cause, regs->cp0_badvaddr);
158 /* Read all the registers and then print them as there is a
159 problem with interspersed printk's upsetting the Bonito controller.
160 Do it for the others too.
163 switch (mips_revision_sconid) {
164 case MIPS_REVISION_SCON_SOCIT:
165 case MIPS_REVISION_SCON_ROCIT:
166 case MIPS_REVISION_SCON_SOCITSC:
167 case MIPS_REVISION_SCON_SOCITSCP:
170 case MIPS_REVISION_SCON_GT64120:
171 intrcause = GT_READ(GT_INTRCAUSE_OFS);
172 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
173 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
174 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
175 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
178 case MIPS_REVISION_SCON_BONITO:
179 pcibadaddr = BONITO_PCIBADADDR;
180 pcimstat = BONITO_PCIMSTAT;
181 intisr = BONITO_INTISR;
182 inten = BONITO_INTEN;
183 intpol = BONITO_INTPOL;
184 intedge = BONITO_INTEDGE;
185 intsteer = BONITO_INTSTEER;
186 pcicmd = BONITO_PCICMD;
187 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
188 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
189 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
190 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
191 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
192 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
193 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
194 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
198 die("CoreHi interrupt", regs);
201 static inline int clz(unsigned long x)
215 * Version of ffs that only looks at bits 12..15.
217 static inline unsigned int irq_ffs(unsigned int pending)
219 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
220 return -clz(pending) + 31 - CAUSEB_IP;
225 t0 = pending & 0xf000;
229 pending = pending << t0;
231 t0 = pending & 0xc000;
235 pending = pending << t0;
237 t0 = pending & 0x8000;
241 /* pending = pending << t0; */
248 * IRQs on the Malta board look basically (barring software IRQs which we
249 * don't use at all and all external interrupt sources are combined together
250 * on hardware interrupt 0 (MIPS IRQ 2)) like:
254 * 0 Software (ignored)
255 * 1 Software (ignored)
256 * 2 Combined hardware interrupt (hw0)
257 * 3 Hardware (ignored)
258 * 4 Hardware (ignored)
259 * 5 Hardware (ignored)
260 * 6 Hardware (ignored)
261 * 7 R4k timer (what we use)
263 * We handle the IRQ according to _our_ priority which is:
265 * Highest ---- R4k Timer
266 * Lowest ---- Combined hardware interrupt
268 * then we just return, if multiple IRQs are pending then we will just take
269 * another exception, big deal.
272 asmlinkage void plat_irq_dispatch(void)
274 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
277 if (unlikely(!pending)) {
278 spurious_interrupt();
282 irq = irq_ffs(pending);
284 if (irq == MIPSCPU_INT_I8259A)
285 malta_hw0_irqdispatch();
286 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
287 malta_ipi_irqdispatch();
289 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
292 #ifdef CONFIG_MIPS_MT_SMP
295 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
296 #define GIC_MIPS_CPU_IPI_CALL_IRQ 4
298 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
299 #define C_RESCHED C_SW0
300 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
302 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
304 static void ipi_resched_dispatch(void)
306 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
309 static void ipi_call_dispatch(void)
311 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
314 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
321 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
323 smp_call_function_interrupt();
328 static struct irqaction irq_resched = {
329 .handler = ipi_resched_interrupt,
330 .flags = IRQF_PERCPU,
331 .name = "IPI_resched"
334 static struct irqaction irq_call = {
335 .handler = ipi_call_interrupt,
336 .flags = IRQF_PERCPU,
339 #endif /* CONFIG_MIPS_MT_SMP */
341 static int gic_resched_int_base;
342 static int gic_call_int_base;
343 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
344 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
346 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
348 return GIC_CALL_INT(cpu);
351 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
353 return GIC_RESCHED_INT(cpu);
356 static struct irqaction i8259irq = {
357 .handler = no_action,
358 .name = "XT-PIC cascade",
359 .flags = IRQF_NO_THREAD,
362 static struct irqaction corehi_irqaction = {
363 .handler = no_action,
365 .flags = IRQF_NO_THREAD,
368 static msc_irqmap_t __initdata msc_irqmap[] = {
369 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
370 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
372 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
374 static msc_irqmap_t __initdata msc_eicirqmap[] = {
375 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
376 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
377 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
378 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
379 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
380 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
381 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
382 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
383 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
384 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
387 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
390 * This GIC specific tabular array defines the association between External
391 * Interrupts and CPUs/Core Interrupts. The nature of the External
392 * Interrupts is also defined here - polarity/trigger.
395 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
398 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
402 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
403 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
404 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
405 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
406 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
407 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
408 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
411 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
412 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
413 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
415 /* The remainder of this table is initialised by fill_ipi_map */
420 * GCMP needs to be detected before any SMP initialisation
422 int __init gcmp_probe(unsigned long addr, unsigned long size)
424 if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) &&
425 (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) {
427 pr_debug("GCMP NOT present\n");
431 if (gcmp_present >= 0)
434 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
435 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
436 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
439 pr_debug("GCMP present\n");
443 /* Return the number of IOCU's present */
444 int __init gcmp_niocu(void)
446 return gcmp_present ?
447 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
451 /* Set GCMP region attributes */
452 void __init gcmp_setregion(int region, unsigned long base,
453 unsigned long mask, int type)
455 GCMPGCBn(CMxBASE, region) = base;
456 GCMPGCBn(CMxMASK, region) = mask | type;
459 #if defined(CONFIG_MIPS_MT_SMP)
460 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
462 int intr = baseintr + cpu;
463 gic_intr_map[intr].cpunum = cpu;
464 gic_intr_map[intr].pin = cpupin;
465 gic_intr_map[intr].polarity = GIC_POL_POS;
466 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
467 gic_intr_map[intr].flags = GIC_FLAG_IPI;
468 ipi_map[cpu] |= (1 << (cpupin + 2));
471 static void __init fill_ipi_map(void)
475 for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
476 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
477 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
482 void __init arch_init_ipiirq(int irq, struct irqaction *action)
484 setup_irq(irq, action);
485 irq_set_handler(irq, handle_percpu_irq);
488 void __init arch_init_irq(void)
496 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
499 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
500 _msc01_biu_base = (unsigned long)
501 ioremap_nocache(MSC01_BIU_REG_BASE,
502 MSC01_BIU_ADDRSPACE_SZ);
503 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
504 MSC01_SC_CFG_GICPRES_MSK) >>
505 MSC01_SC_CFG_GICPRES_SHF;
509 pr_debug("GIC present\n");
511 switch (mips_revision_sconid) {
512 case MIPS_REVISION_SCON_SOCIT:
513 case MIPS_REVISION_SCON_ROCIT:
515 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
516 MSC01E_INT_BASE, msc_eicirqmap,
519 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
520 MSC01C_INT_BASE, msc_irqmap,
524 case MIPS_REVISION_SCON_SOCITSC:
525 case MIPS_REVISION_SCON_SOCITSCP:
527 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
528 MSC01E_INT_BASE, msc_eicirqmap,
531 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
532 MSC01C_INT_BASE, msc_irqmap,
537 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
538 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
539 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
540 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
541 } else if (cpu_has_vint) {
542 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
543 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
544 #ifdef CONFIG_MIPS_MT_SMTC
545 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
546 (0x100 << MIPSCPU_INT_I8259A));
547 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
548 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
550 * Temporary hack to ensure that the subsidiary device
551 * interrupts coing in via the i8259A, but associated
552 * with low IRQ numbers, will restore the Status.IM
553 * value associated with the i8259A.
558 for (i = 0; i < 16; i++)
559 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
562 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
563 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
565 #endif /* CONFIG_MIPS_MT_SMTC */
567 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
568 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
575 #if defined(CONFIG_MIPS_MT_SMP)
576 gic_call_int_base = GIC_NUM_INTRS -
577 (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids;
578 gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
581 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
582 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
585 i = REG(_msc01_biu_base, MSC01_SC_CFG);
586 REG(_msc01_biu_base, MSC01_SC_CFG) =
587 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
588 pr_debug("GIC Enabled\n");
590 #if defined(CONFIG_MIPS_MT_SMP)
591 /* set up ipi interrupts */
593 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
594 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
596 /* Argh.. this really needs sorting out.. */
597 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
598 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
599 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
600 write_c0_status(0x1100dc00);
601 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
602 for (i = 0; i < nr_cpu_ids; i++) {
603 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
604 GIC_RESCHED_INT(i), &irq_resched);
605 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
606 GIC_CALL_INT(i), &irq_call);
610 #if defined(CONFIG_MIPS_MT_SMP)
611 /* set up ipi interrupts */
613 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
614 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
615 cpu_ipi_resched_irq = MSC01E_INT_SW0;
616 cpu_ipi_call_irq = MSC01E_INT_SW1;
619 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
620 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
622 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
623 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
625 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
626 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
631 void malta_be_init(void)
634 /* Could change CM error mask register */
639 static char *tr[8] = {
640 "mem", "gcr", "gic", "mmio",
641 "0x04", "0x05", "0x06", "0x07"
644 static char *mcmd[32] = {
646 [0x01] = "Legacy Write",
647 [0x02] = "Legacy Read",
653 [0x08] = "Coherent Read Own",
654 [0x09] = "Coherent Read Share",
655 [0x0a] = "Coherent Read Discard",
656 [0x0b] = "Coherent Ready Share Always",
657 [0x0c] = "Coherent Upgrade",
658 [0x0d] = "Coherent Writeback",
661 [0x10] = "Coherent Copyback",
662 [0x11] = "Coherent Copyback Invalidate",
663 [0x12] = "Coherent Invalidate",
664 [0x13] = "Coherent Write Invalidate",
665 [0x14] = "Coherent Completion Sync",
679 static char *core[8] = {
680 "Invalid/OK", "Invalid/Data",
681 "Shared/OK", "Shared/Data",
682 "Modified/OK", "Modified/Data",
683 "Exclusive/OK", "Exclusive/Data"
686 static char *causes[32] = {
687 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
688 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
689 "0x08", "0x09", "0x0a", "0x0b",
690 "0x0c", "0x0d", "0x0e", "0x0f",
691 "0x10", "0x11", "0x12", "0x13",
692 "0x14", "0x15", "0x16", "INTVN_WR_ERR",
693 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
694 "0x1c", "0x1d", "0x1e", "0x1f"
697 int malta_be_handler(struct pt_regs *regs, int is_fixup)
699 /* This duplicates the handling in do_be which seems wrong */
700 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
703 unsigned long cm_error = GCMPGCB(GCMEC);
704 unsigned long cm_addr = GCMPGCB(GCMEA);
705 unsigned long cm_other = GCMPGCB(GCMEO);
706 unsigned long cause, ocause;
709 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
711 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
713 unsigned long cca_bits = (cm_error >> 15) & 7;
714 unsigned long tr_bits = (cm_error >> 12) & 7;
715 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
716 unsigned long stag_bits = (cm_error >> 3) & 15;
717 unsigned long sport_bits = (cm_error >> 0) & 7;
719 snprintf(buf, sizeof(buf),
720 "CCA=%lu TR=%s MCmd=%s STag=%lu "
722 cca_bits, tr[tr_bits], mcmd[mcmd_bits],
723 stag_bits, sport_bits);
725 /* glob state & sresp together */
726 unsigned long c3_bits = (cm_error >> 18) & 7;
727 unsigned long c2_bits = (cm_error >> 15) & 7;
728 unsigned long c1_bits = (cm_error >> 12) & 7;
729 unsigned long c0_bits = (cm_error >> 9) & 7;
730 unsigned long sc_bit = (cm_error >> 8) & 1;
731 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
732 unsigned long sport_bits = (cm_error >> 0) & 7;
733 snprintf(buf, sizeof(buf),
734 "C3=%s C2=%s C1=%s C0=%s SC=%s "
735 "MCmd=%s SPort=%lu\n",
736 core[c3_bits], core[c2_bits],
737 core[c1_bits], core[c0_bits],
738 sc_bit ? "True" : "False",
739 mcmd[mcmd_bits], sport_bits);
742 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
743 GCMP_GCB_GMEO_ERROR_2ND_SHF;
745 printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
747 printk("CM_ADDR =%08lx\n", cm_addr);
748 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
750 /* reprime cause register */
758 void gic_enable_interrupt(int irq_vec)
760 GIC_SET_INTR_MASK(irq_vec);
763 void gic_disable_interrupt(int irq_vec)
765 GIC_CLR_INTR_MASK(irq_vec);
768 void gic_irq_ack(struct irq_data *d)
770 int irq = (d->irq - gic_irq_base);
772 GIC_CLR_INTR_MASK(irq);
774 if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
775 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
778 void gic_finish_irq(struct irq_data *d)
780 /* Enable interrupts. */
781 GIC_SET_INTR_MASK(d->irq - gic_irq_base);
784 void __init gic_platform_init(int irqs, struct irq_chip *irq_controller)
788 for (i = gic_irq_base; i < (gic_irq_base + irqs); i++)
789 irq_set_chip(i, irq_controller);