2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
8 * Copyright (C) 2001 Ralf Baechle
9 * Copyright (C) 2013 Imagination Technologies Ltd.
11 * Routines for generic manipulation of the interrupts found on the MIPS
12 * Malta board. The interrupt controller is located in the South Bridge
13 * a PIIX4 device with two internal 82C95 interrupt controllers.
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/irqchip.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/interrupt.h>
22 #include <linux/irqchip/mips-gic.h>
23 #include <linux/of_irq.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/kernel.h>
26 #include <linux/random.h>
28 #include <asm/traps.h>
29 #include <asm/i8259.h>
30 #include <asm/irq_cpu.h>
31 #include <asm/irq_regs.h>
32 #include <asm/mips-cm.h>
33 #include <asm/mips-boards/malta.h>
34 #include <asm/mips-boards/maltaint.h>
35 #include <asm/gt64120.h>
36 #include <asm/mips-boards/generic.h>
37 #include <asm/mips-boards/msc01_pci.h>
38 #include <asm/msc01_ic.h>
39 #include <asm/setup.h>
42 static inline int mips_pcibios_iack(void)
47 * Determine highest priority pending interrupt by performing
48 * a PCI Interrupt Acknowledge cycle.
50 switch (mips_revision_sconid) {
51 case MIPS_REVISION_SCON_SOCIT:
52 case MIPS_REVISION_SCON_ROCIT:
53 case MIPS_REVISION_SCON_SOCITSC:
54 case MIPS_REVISION_SCON_SOCITSCP:
55 MSC_READ(MSC01_PCI_IACK, irq);
58 case MIPS_REVISION_SCON_GT64120:
59 irq = GT_READ(GT_PCI0_IACK_OFS);
62 case MIPS_REVISION_SCON_BONITO:
63 /* The following will generate a PCI IACK cycle on the
64 * Bonito controller. It's a little bit kludgy, but it
65 * was the easiest way to implement it in hardware at
68 BONITO_PCIMAP_CFG = 0x20000;
70 /* Flush Bonito register block */
71 (void) BONITO_PCIMAP_CFG;
74 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
77 BONITO_PCIMAP_CFG = 0;
80 pr_emerg("Unknown system controller.\n");
86 static void corehi_irqdispatch(void)
88 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
89 unsigned int pcimstat, intisr, inten, intpol;
90 unsigned int intrcause, datalo, datahi;
91 struct pt_regs *regs = get_irq_regs();
93 pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
94 pr_emerg("epc : %08lx\nStatus: %08lx\n"
95 "Cause : %08lx\nbadVaddr : %08lx\n",
96 regs->cp0_epc, regs->cp0_status,
97 regs->cp0_cause, regs->cp0_badvaddr);
99 /* Read all the registers and then print them as there is a
100 problem with interspersed printk's upsetting the Bonito controller.
101 Do it for the others too.
104 switch (mips_revision_sconid) {
105 case MIPS_REVISION_SCON_SOCIT:
106 case MIPS_REVISION_SCON_ROCIT:
107 case MIPS_REVISION_SCON_SOCITSC:
108 case MIPS_REVISION_SCON_SOCITSCP:
111 case MIPS_REVISION_SCON_GT64120:
112 intrcause = GT_READ(GT_INTRCAUSE_OFS);
113 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
114 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
115 pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
116 pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
119 case MIPS_REVISION_SCON_BONITO:
120 pcibadaddr = BONITO_PCIBADADDR;
121 pcimstat = BONITO_PCIMSTAT;
122 intisr = BONITO_INTISR;
123 inten = BONITO_INTEN;
124 intpol = BONITO_INTPOL;
125 intedge = BONITO_INTEDGE;
126 intsteer = BONITO_INTSTEER;
127 pcicmd = BONITO_PCICMD;
128 pr_emerg("BONITO_INTISR = %08x\n", intisr);
129 pr_emerg("BONITO_INTEN = %08x\n", inten);
130 pr_emerg("BONITO_INTPOL = %08x\n", intpol);
131 pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
132 pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
133 pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
134 pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
135 pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
139 die("CoreHi interrupt", regs);
142 static irqreturn_t corehi_handler(int irq, void *dev_id)
144 corehi_irqdispatch();
148 #ifdef CONFIG_MIPS_MT_SMP
150 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
151 #define C_RESCHED C_SW0
152 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
154 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
156 static void ipi_resched_dispatch(void)
158 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
161 static void ipi_call_dispatch(void)
163 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
166 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
168 #ifdef CONFIG_MIPS_VPE_APSP_API_CMP
178 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
180 generic_smp_call_function_interrupt();
185 static struct irqaction irq_resched = {
186 .handler = ipi_resched_interrupt,
187 .flags = IRQF_PERCPU,
188 .name = "IPI_resched"
191 static struct irqaction irq_call = {
192 .handler = ipi_call_interrupt,
193 .flags = IRQF_PERCPU,
196 #endif /* CONFIG_MIPS_MT_SMP */
198 static struct irqaction corehi_irqaction = {
199 .handler = corehi_handler,
201 .flags = IRQF_NO_THREAD,
204 static msc_irqmap_t msc_irqmap[] __initdata = {
205 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
206 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
208 static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
210 static msc_irqmap_t msc_eicirqmap[] __initdata = {
211 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
212 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
213 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
214 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
215 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
216 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
217 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
218 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
219 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
220 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
223 static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
225 void __init arch_init_ipiirq(int irq, struct irqaction *action)
227 setup_irq(irq, action);
228 irq_set_handler(irq, handle_percpu_irq);
231 void __init arch_init_irq(void)
236 * Preallocate the i8259's expected virq's here. Since irqchip_init()
237 * will probe the irqchips in hierarchial order, i8259 is probed last.
238 * If anything allocates a virq before the i8259 is probed, it will
239 * be given one of the i8259's expected range and consequently setup
240 * of the i8259 will fail.
242 WARN(irq_alloc_descs(I8259A_IRQ_BASE, I8259A_IRQ_BASE,
243 16, numa_node_id()) < 0,
244 "Cannot reserve i8259 virqs at IRQ%d\n", I8259A_IRQ_BASE);
246 i8259_set_poll(mips_pcibios_iack);
249 switch (mips_revision_sconid) {
250 case MIPS_REVISION_SCON_SOCIT:
251 case MIPS_REVISION_SCON_ROCIT:
253 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
254 MSC01E_INT_BASE, msc_eicirqmap,
257 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
258 MSC01C_INT_BASE, msc_irqmap,
262 case MIPS_REVISION_SCON_SOCITSC:
263 case MIPS_REVISION_SCON_SOCITSCP:
265 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
266 MSC01E_INT_BASE, msc_eicirqmap,
269 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
270 MSC01C_INT_BASE, msc_irqmap,
275 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
277 #if defined(CONFIG_MIPS_MT_SMP)
278 /* set up ipi interrupts */
280 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
281 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
282 cpu_ipi_resched_irq = MSC01E_INT_SW0;
283 cpu_ipi_call_irq = MSC01E_INT_SW1;
285 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
286 MIPS_CPU_IPI_RESCHED_IRQ;
287 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
288 MIPS_CPU_IPI_CALL_IRQ;
290 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
291 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
294 set_vi_handler(MSC01E_INT_COREHI,
296 corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
298 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
302 setup_irq(corehi_irq, &corehi_irqaction);