2 * Just-In-Time compiler for BPF filters on MIPS
4 * Copyright (c) 2014 Imagination Technologies Ltd.
5 * Author: Markos Chandras <markos.chandras@imgtec.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2 of the License.
12 #include <linux/bitops.h>
13 #include <linux/compiler.h>
14 #include <linux/errno.h>
15 #include <linux/filter.h>
16 #include <linux/if_vlan.h>
17 #include <linux/kconfig.h>
18 #include <linux/moduleloader.h>
19 #include <linux/netdevice.h>
20 #include <linux/string.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <asm/bitops.h>
24 #include <asm/cacheflush.h>
25 #include <asm/cpu-features.h>
32 * s0 1st scratch register
33 * s1 2nd scratch register
40 * On entry (*bpf_func)(*skb, *filter)
41 * a0 = MIPS_R_A0 = skb;
42 * a1 = MIPS_R_A1 = filter;
54 * saved reg 0 <-- r_sp
59 * <--------------------- len ------------------------>
60 * <--skb-len(r_skb_hl)-->< ----- skb->data_len ------>
61 * ----------------------------------------------------
63 * ----------------------------------------------------
66 #define RSIZE (sizeof(unsigned long))
67 #define ptr typeof(unsigned long)
69 /* ABI specific return values */
70 #ifdef CONFIG_32BIT /* O32 */
71 #ifdef CONFIG_CPU_LITTLE_ENDIAN
72 #define r_err MIPS_R_V1
73 #define r_val MIPS_R_V0
74 #else /* CONFIG_CPU_LITTLE_ENDIAN */
75 #define r_err MIPS_R_V0
76 #define r_val MIPS_R_V1
79 #define r_err MIPS_R_V0
80 #define r_val MIPS_R_V0
83 #define r_ret MIPS_R_V0
86 * Use 2 scratch registers to avoid pipeline interlocks.
87 * There is no overhead during epilogue and prologue since
88 * any of the $s0-$s6 registers will only be preserved if
89 * they are going to actually be used.
91 #define r_s0 MIPS_R_S0 /* scratch reg 1 */
92 #define r_s1 MIPS_R_S1 /* scratch reg 2 */
93 #define r_off MIPS_R_S2
96 #define r_skb MIPS_R_S5
98 #define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
99 #define r_tmp MIPS_R_T7 /* No need to preserve this */
100 #define r_zero MIPS_R_ZERO
101 #define r_sp MIPS_R_SP
102 #define r_ra MIPS_R_RA
104 #define SCRATCH_OFF(k) (4 * (k))
107 #define SEEN_CALL (1 << BPF_MEMWORDS)
108 #define SEEN_SREG_SFT (BPF_MEMWORDS + 1)
109 #define SEEN_SREG_BASE (1 << SEEN_SREG_SFT)
110 #define SEEN_SREG(x) (SEEN_SREG_BASE << (x))
111 #define SEEN_S0 SEEN_SREG(0)
112 #define SEEN_S1 SEEN_SREG(1)
113 #define SEEN_OFF SEEN_SREG(2)
114 #define SEEN_A SEEN_SREG(3)
115 #define SEEN_X SEEN_SREG(4)
116 #define SEEN_SKB SEEN_SREG(5)
117 #define SEEN_MEM SEEN_SREG(6)
119 /* Arguments used by JIT */
120 #define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */
122 #define FLAG_NEED_X_RESET (1 << 0)
124 #define SBIT(x) (1 << (x)) /* Signed version of BIT() */
127 * struct jit_ctx - JIT context
128 * @skf: The sk_filter
129 * @prologue_bytes: Number of bytes for prologue
130 * @idx: Instruction index
132 * @offsets: Instruction offsets
133 * @target: Memory location for the compiled filter
136 const struct sk_filter *skf;
137 unsigned int prologue_bytes;
145 static inline int optimize_div(u32 *k)
147 /* power of 2 divides can be implemented with right shift */
148 if (!(*k & (*k-1))) {
156 /* Simply emit the instruction if the JIT memory space has been allocated */
157 #define emit_instr(ctx, func, ...) \
159 if ((ctx)->target != NULL) { \
160 u32 *p = &(ctx)->target[ctx->idx]; \
161 uasm_i_##func(&p, ##__VA_ARGS__); \
166 /* Determine if immediate is within the 16-bit signed range */
167 static inline bool is_range16(s32 imm)
169 if (imm >= SBIT(15) || imm < -SBIT(15))
174 static inline void emit_addu(unsigned int dst, unsigned int src1,
175 unsigned int src2, struct jit_ctx *ctx)
177 emit_instr(ctx, addu, dst, src1, src2);
180 static inline void emit_nop(struct jit_ctx *ctx)
182 emit_instr(ctx, nop);
185 /* Load a u32 immediate to a register */
186 static inline void emit_load_imm(unsigned int dst, u32 imm, struct jit_ctx *ctx)
188 if (ctx->target != NULL) {
189 /* addiu can only handle s16 */
190 if (is_range16(imm)) {
191 u32 *p = &ctx->target[ctx->idx];
192 uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16);
193 p = &ctx->target[ctx->idx + 1];
194 uasm_i_ori(&p, dst, r_tmp_imm, imm & 0xffff);
196 u32 *p = &ctx->target[ctx->idx];
197 uasm_i_addiu(&p, dst, r_zero, imm);
206 static inline void emit_or(unsigned int dst, unsigned int src1,
207 unsigned int src2, struct jit_ctx *ctx)
209 emit_instr(ctx, or, dst, src1, src2);
212 static inline void emit_ori(unsigned int dst, unsigned src, u32 imm,
215 if (imm >= BIT(16)) {
216 emit_load_imm(r_tmp, imm, ctx);
217 emit_or(dst, src, r_tmp, ctx);
219 emit_instr(ctx, ori, dst, src, imm);
224 static inline void emit_daddu(unsigned int dst, unsigned int src1,
225 unsigned int src2, struct jit_ctx *ctx)
227 emit_instr(ctx, daddu, dst, src1, src2);
230 static inline void emit_daddiu(unsigned int dst, unsigned int src,
231 int imm, struct jit_ctx *ctx)
234 * Only used for stack, so the imm is relatively small
235 * and it fits in 15-bits
237 emit_instr(ctx, daddiu, dst, src, imm);
240 static inline void emit_addiu(unsigned int dst, unsigned int src,
241 u32 imm, struct jit_ctx *ctx)
243 if (is_range16(imm)) {
244 emit_load_imm(r_tmp, imm, ctx);
245 emit_addu(dst, r_tmp, src, ctx);
247 emit_instr(ctx, addiu, dst, src, imm);
251 static inline void emit_and(unsigned int dst, unsigned int src1,
252 unsigned int src2, struct jit_ctx *ctx)
254 emit_instr(ctx, and, dst, src1, src2);
257 static inline void emit_andi(unsigned int dst, unsigned int src,
258 u32 imm, struct jit_ctx *ctx)
260 /* If imm does not fit in u16 then load it to register */
261 if (imm >= BIT(16)) {
262 emit_load_imm(r_tmp, imm, ctx);
263 emit_and(dst, src, r_tmp, ctx);
265 emit_instr(ctx, andi, dst, src, imm);
269 static inline void emit_xor(unsigned int dst, unsigned int src1,
270 unsigned int src2, struct jit_ctx *ctx)
272 emit_instr(ctx, xor, dst, src1, src2);
275 static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx)
277 /* If imm does not fit in u16 then load it to register */
278 if (imm >= BIT(16)) {
279 emit_load_imm(r_tmp, imm, ctx);
280 emit_xor(dst, src, r_tmp, ctx);
282 emit_instr(ctx, xori, dst, src, imm);
286 static inline void emit_stack_offset(int offset, struct jit_ctx *ctx)
288 if (config_enabled(CONFIG_64BIT))
289 emit_instr(ctx, daddiu, r_sp, r_sp, offset);
291 emit_instr(ctx, addiu, r_sp, r_sp, offset);
295 static inline void emit_subu(unsigned int dst, unsigned int src1,
296 unsigned int src2, struct jit_ctx *ctx)
298 emit_instr(ctx, subu, dst, src1, src2);
301 static inline void emit_neg(unsigned int reg, struct jit_ctx *ctx)
303 emit_subu(reg, r_zero, reg, ctx);
306 static inline void emit_sllv(unsigned int dst, unsigned int src,
307 unsigned int sa, struct jit_ctx *ctx)
309 emit_instr(ctx, sllv, dst, src, sa);
312 static inline void emit_sll(unsigned int dst, unsigned int src,
313 unsigned int sa, struct jit_ctx *ctx)
315 /* sa is 5-bits long */
316 BUG_ON(sa >= BIT(5));
317 emit_instr(ctx, sll, dst, src, sa);
320 static inline void emit_srlv(unsigned int dst, unsigned int src,
321 unsigned int sa, struct jit_ctx *ctx)
323 emit_instr(ctx, srlv, dst, src, sa);
326 static inline void emit_srl(unsigned int dst, unsigned int src,
327 unsigned int sa, struct jit_ctx *ctx)
329 /* sa is 5-bits long */
330 BUG_ON(sa >= BIT(5));
331 emit_instr(ctx, srl, dst, src, sa);
334 static inline void emit_sltu(unsigned int dst, unsigned int src1,
335 unsigned int src2, struct jit_ctx *ctx)
337 emit_instr(ctx, sltu, dst, src1, src2);
340 static inline void emit_sltiu(unsigned dst, unsigned int src,
341 unsigned int imm, struct jit_ctx *ctx)
343 /* 16 bit immediate */
344 if (is_range16((s32)imm)) {
345 emit_load_imm(r_tmp, imm, ctx);
346 emit_sltu(dst, src, r_tmp, ctx);
348 emit_instr(ctx, sltiu, dst, src, imm);
353 /* Store register on the stack */
354 static inline void emit_store_stack_reg(ptr reg, ptr base,
358 if (config_enabled(CONFIG_64BIT))
359 emit_instr(ctx, sd, reg, offset, base);
361 emit_instr(ctx, sw, reg, offset, base);
364 static inline void emit_store(ptr reg, ptr base, unsigned int offset,
367 emit_instr(ctx, sw, reg, offset, base);
370 static inline void emit_load_stack_reg(ptr reg, ptr base,
374 if (config_enabled(CONFIG_64BIT))
375 emit_instr(ctx, ld, reg, offset, base);
377 emit_instr(ctx, lw, reg, offset, base);
380 static inline void emit_load(unsigned int reg, unsigned int base,
381 unsigned int offset, struct jit_ctx *ctx)
383 emit_instr(ctx, lw, reg, offset, base);
386 static inline void emit_load_byte(unsigned int reg, unsigned int base,
387 unsigned int offset, struct jit_ctx *ctx)
389 emit_instr(ctx, lb, reg, offset, base);
392 static inline void emit_half_load(unsigned int reg, unsigned int base,
393 unsigned int offset, struct jit_ctx *ctx)
395 emit_instr(ctx, lh, reg, offset, base);
398 static inline void emit_mul(unsigned int dst, unsigned int src1,
399 unsigned int src2, struct jit_ctx *ctx)
401 emit_instr(ctx, mul, dst, src1, src2);
404 static inline void emit_div(unsigned int dst, unsigned int src,
407 if (ctx->target != NULL) {
408 u32 *p = &ctx->target[ctx->idx];
409 uasm_i_divu(&p, dst, src);
410 p = &ctx->target[ctx->idx + 1];
411 uasm_i_mfhi(&p, dst);
413 ctx->idx += 2; /* 2 insts */
416 static inline void emit_mod(unsigned int dst, unsigned int src,
419 if (ctx->target != NULL) {
420 u32 *p = &ctx->target[ctx->idx];
421 uasm_i_divu(&p, dst, src);
422 p = &ctx->target[ctx->idx + 1];
423 uasm_i_mflo(&p, dst);
425 ctx->idx += 2; /* 2 insts */
428 static inline void emit_dsll(unsigned int dst, unsigned int src,
429 unsigned int sa, struct jit_ctx *ctx)
431 emit_instr(ctx, dsll, dst, src, sa);
434 static inline void emit_dsrl32(unsigned int dst, unsigned int src,
435 unsigned int sa, struct jit_ctx *ctx)
437 emit_instr(ctx, dsrl32, dst, src, sa);
440 static inline void emit_wsbh(unsigned int dst, unsigned int src,
443 emit_instr(ctx, wsbh, dst, src);
446 /* load a function pointer to register */
447 static inline void emit_load_func(unsigned int reg, ptr imm,
450 if (config_enabled(CONFIG_64BIT)) {
451 /* At this point imm is always 64-bit */
452 emit_load_imm(r_tmp, (u64)imm >> 32, ctx);
453 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
454 emit_ori(r_tmp, r_tmp_imm, (imm >> 16) & 0xffff, ctx);
455 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
456 emit_ori(reg, r_tmp_imm, imm & 0xffff, ctx);
458 emit_load_imm(reg, imm, ctx);
462 /* Move to real MIPS register */
463 static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
465 if (config_enabled(CONFIG_64BIT))
466 emit_daddu(dst, src, r_zero, ctx);
468 emit_addu(dst, src, r_zero, ctx);
471 /* Move to JIT (32-bit) register */
472 static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
474 emit_addu(dst, src, r_zero, ctx);
477 /* Compute the immediate value for PC-relative branches. */
478 static inline u32 b_imm(unsigned int tgt, struct jit_ctx *ctx)
480 if (ctx->target == NULL)
484 * We want a pc-relative branch. We only do forward branches
485 * so tgt is always after pc. tgt is the instruction offset
486 * we want to jump to.
489 * I: target_offset <- sign_extend(offset)
490 * I+1: PC += target_offset (delay slot)
492 * ctx->idx currently points to the branch instruction
493 * but the offset is added to the delay slot so we need
496 return ctx->offsets[tgt] -
497 (ctx->idx * 4 - ctx->prologue_bytes) - 4;
500 static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2,
501 unsigned int imm, struct jit_ctx *ctx)
503 if (ctx->target != NULL) {
504 u32 *p = &ctx->target[ctx->idx];
508 uasm_i_beq(&p, reg1, reg2, imm);
511 uasm_i_bne(&p, reg1, reg2, imm);
517 pr_warn("%s: Unhandled branch conditional: %d\n",
524 static inline void emit_b(unsigned int imm, struct jit_ctx *ctx)
526 emit_bcond(MIPS_COND_ALL, r_zero, r_zero, imm, ctx);
529 static inline void emit_jalr(unsigned int link, unsigned int reg,
532 emit_instr(ctx, jalr, link, reg);
535 static inline void emit_jr(unsigned int reg, struct jit_ctx *ctx)
537 emit_instr(ctx, jr, reg);
540 static inline u16 align_sp(unsigned int num)
542 /* Double word alignment for 32-bit, quadword for 64-bit */
543 unsigned int align = config_enabled(CONFIG_64BIT) ? 16 : 8;
544 num = (num + (align - 1)) & -align;
548 static inline void update_on_xread(struct jit_ctx *ctx)
550 if (!(ctx->flags & SEEN_X))
551 ctx->flags |= FLAG_NEED_X_RESET;
553 ctx->flags |= SEEN_X;
556 static bool is_load_to_a(u16 inst)
564 case BPF_S_ANC_IFINDEX:
566 case BPF_S_ANC_PROTOCOL:
567 case BPF_S_ANC_RXHASH:
568 case BPF_S_ANC_VLAN_TAG:
569 case BPF_S_ANC_VLAN_TAG_PRESENT:
570 case BPF_S_ANC_QUEUE:
577 static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset)
579 int i = 0, real_off = 0;
580 u32 sflags, tmp_flags;
582 /* Adjust the stack pointer */
583 emit_stack_offset(-align_sp(offset), ctx);
585 if (ctx->flags & SEEN_CALL) {
586 /* Argument save area */
587 if (config_enabled(CONFIG_64BIT))
588 /* Bottom of current frame */
589 real_off = align_sp(offset) - RSIZE;
591 /* Top of previous frame */
592 real_off = align_sp(offset) + RSIZE;
593 emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
594 emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
599 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
600 /* sflags is essentially a bitmap */
602 if ((sflags >> i) & 0x1) {
603 emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
611 /* save return address */
612 if (ctx->flags & SEEN_CALL) {
613 emit_store_stack_reg(r_ra, r_sp, real_off, ctx);
617 /* Setup r_M leaving the alignment gap if necessary */
618 if (ctx->flags & SEEN_MEM) {
619 if (real_off % (RSIZE * 2))
621 emit_addiu(r_M, r_sp, real_off, ctx);
625 static void restore_bpf_jit_regs(struct jit_ctx *ctx,
629 u32 sflags, tmp_flags;
631 if (ctx->flags & SEEN_CALL) {
632 if (config_enabled(CONFIG_64BIT))
633 /* Bottom of current frame */
634 real_off = align_sp(offset) - RSIZE;
636 /* Top of previous frame */
637 real_off = align_sp(offset) + RSIZE;
638 emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
639 emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
644 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
645 /* sflags is a bitmap */
648 if ((sflags >> i) & 0x1) {
649 emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
657 /* restore return address */
658 if (ctx->flags & SEEN_CALL)
659 emit_load_stack_reg(r_ra, r_sp, real_off, ctx);
661 /* Restore the sp and discard the scrach memory */
662 emit_stack_offset(align_sp(offset), ctx);
665 static unsigned int get_stack_depth(struct jit_ctx *ctx)
670 /* How may s* regs do we need to preserved? */
671 sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * RSIZE;
673 if (ctx->flags & SEEN_MEM)
674 sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */
676 if (ctx->flags & SEEN_CALL)
678 * The JIT code make calls to external functions using 2
679 * arguments. Therefore, for o32 we don't need to allocate
680 * space because we don't care if the argumetns are lost
681 * across calls. We do need however to preserve incoming
682 * arguments but the space is already allocated for us by
683 * the caller. On the other hand, for n64, we need to allocate
684 * this space ourselves. We need to preserve $ra as well.
686 sp_off += config_enabled(CONFIG_64BIT) ?
687 (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE;
690 * Subtract the bytes for the last registers since we only care about
691 * the location on the stack pointer.
693 return sp_off - RSIZE;
696 static void build_prologue(struct jit_ctx *ctx)
698 u16 first_inst = ctx->skf->insns[0].code;
701 /* Calculate the total offset for the stack pointer */
702 sp_off = get_stack_depth(ctx);
703 save_bpf_jit_regs(ctx, sp_off);
705 if (ctx->flags & SEEN_SKB)
706 emit_reg_move(r_skb, MIPS_R_A0, ctx);
708 if (ctx->flags & FLAG_NEED_X_RESET)
709 emit_jit_reg_move(r_X, r_zero, ctx);
711 /* Do not leak kernel data to userspace */
712 if ((first_inst != BPF_S_RET_K) && !(is_load_to_a(first_inst)))
713 emit_jit_reg_move(r_A, r_zero, ctx);
716 static void build_epilogue(struct jit_ctx *ctx)
720 /* Calculate the total offset for the stack pointer */
722 sp_off = get_stack_depth(ctx);
723 restore_bpf_jit_regs(ctx, sp_off);
730 static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
735 err = skb_copy_bits(skb, offset, &ret, 1);
737 return (u64)err << 32 | ret;
740 static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
745 err = skb_copy_bits(skb, offset, &ret, 2);
747 return (u64)err << 32 | ntohs(ret);
750 static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
755 err = skb_copy_bits(skb, offset, &ret, 4);
757 return (u64)err << 32 | ntohl(ret);
760 #define PKT_TYPE_MAX 7
761 static int pkt_type_offset(void)
763 struct sk_buff skb_probe = {
766 char *ct = (char *)&skb_probe;
769 for (off = 0; off < sizeof(struct sk_buff); off++) {
770 if (ct[off] == PKT_TYPE_MAX)
773 pr_err_once("Please fix pkt_type_offset(), as pkt_type couldn't be found\n");
777 static int build_body(struct jit_ctx *ctx)
779 void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
780 const struct sk_filter *prog = ctx->skf;
781 const struct sock_filter *inst;
782 unsigned int i, off, load_order, condt;
783 u32 k, b_off __maybe_unused;
785 for (i = 0; i < prog->len; i++) {
786 inst = &(prog->insns[i]);
787 pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n",
788 __func__, inst->code, inst->jt, inst->jf, inst->k);
791 if (ctx->target == NULL)
792 ctx->offsets[i] = ctx->idx * 4;
794 switch (inst->code) {
796 /* A <- k ==> li r_A, k */
797 ctx->flags |= SEEN_A;
798 emit_load_imm(r_A, k, ctx);
801 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
802 /* A <- len ==> lw r_A, offset(skb) */
803 ctx->flags |= SEEN_SKB | SEEN_A;
804 off = offsetof(struct sk_buff, len);
805 emit_load(r_A, r_skb, off, ctx);
808 /* A <- M[k] ==> lw r_A, offset(M) */
809 ctx->flags |= SEEN_MEM | SEEN_A;
810 emit_load(r_A, r_M, SCRATCH_OFF(k), ctx);
824 emit_load_imm(r_off, k, ctx);
826 ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 |
829 emit_load_func(r_s0, (ptr)load_func[load_order],
831 emit_reg_move(MIPS_R_A0, r_skb, ctx);
832 emit_jalr(MIPS_R_RA, r_s0, ctx);
833 /* Load second argument to delay slot */
834 emit_reg_move(MIPS_R_A1, r_off, ctx);
835 /* Check the error value */
836 if (config_enabled(CONFIG_64BIT)) {
837 /* Get error code from the top 32-bits */
838 emit_dsrl32(r_s0, r_val, 0, ctx);
839 /* Branch to 3 instructions ahead */
840 emit_bcond(MIPS_COND_NE, r_s0, r_zero, 3 << 2,
843 /* Branch to 3 instructions ahead */
844 emit_bcond(MIPS_COND_NE, r_err, r_zero, 3 << 2,
849 emit_b(b_imm(i + 1, ctx), ctx);
850 emit_jit_reg_move(r_A, r_val, ctx);
851 /* Return with error */
852 emit_b(b_imm(prog->len, ctx), ctx);
853 emit_reg_move(r_ret, r_zero, ctx);
856 /* A <- P[X + k:4] */
860 /* A <- P[X + k:2] */
864 /* A <- P[X + k:1] */
867 update_on_xread(ctx);
868 ctx->flags |= SEEN_OFF | SEEN_X;
869 emit_addiu(r_off, r_X, k, ctx);
873 ctx->flags |= SEEN_X;
874 emit_load_imm(r_X, k, ctx);
878 ctx->flags |= SEEN_X | SEEN_MEM;
879 emit_load(r_X, r_M, SCRATCH_OFF(k), ctx);
881 case BPF_S_LDX_W_LEN:
883 ctx->flags |= SEEN_X | SEEN_SKB;
884 off = offsetof(struct sk_buff, len);
885 emit_load(r_X, r_skb, off, ctx);
887 case BPF_S_LDX_B_MSH:
888 /* X <- 4 * (P[k:1] & 0xf) */
889 ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB;
890 /* Load offset to a1 */
891 emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx);
893 * This may emit two instructions so it may not fit
894 * in the delay slot. So use a0 in the delay slot.
896 emit_load_imm(MIPS_R_A1, k, ctx);
897 emit_jalr(MIPS_R_RA, r_s0, ctx);
898 emit_reg_move(MIPS_R_A0, r_skb, ctx); /* delay slot */
899 /* Check the error value */
900 if (config_enabled(CONFIG_64BIT)) {
901 /* Top 32-bits of $v0 on 64-bit */
902 emit_dsrl32(r_s0, r_val, 0, ctx);
903 emit_bcond(MIPS_COND_NE, r_s0, r_zero,
906 emit_bcond(MIPS_COND_NE, r_err, r_zero,
909 /* No need for delay slot */
911 /* X <- P[1:K] & 0xf */
912 emit_andi(r_X, r_val, 0xf, ctx);
914 emit_b(b_imm(i + 1, ctx), ctx);
915 emit_sll(r_X, r_X, 2, ctx); /* delay slot */
916 /* Return with error */
917 emit_b(b_imm(prog->len, ctx), ctx);
918 emit_load_imm(r_ret, 0, ctx); /* delay slot */
922 ctx->flags |= SEEN_MEM | SEEN_A;
923 emit_store(r_A, r_M, SCRATCH_OFF(k), ctx);
927 ctx->flags |= SEEN_MEM | SEEN_X;
928 emit_store(r_X, r_M, SCRATCH_OFF(k), ctx);
930 case BPF_S_ALU_ADD_K:
932 ctx->flags |= SEEN_A;
933 emit_addiu(r_A, r_A, k, ctx);
935 case BPF_S_ALU_ADD_X:
937 ctx->flags |= SEEN_A | SEEN_X;
938 emit_addu(r_A, r_A, r_X, ctx);
940 case BPF_S_ALU_SUB_K:
942 ctx->flags |= SEEN_A;
943 emit_addiu(r_A, r_A, -k, ctx);
945 case BPF_S_ALU_SUB_X:
947 ctx->flags |= SEEN_A | SEEN_X;
948 emit_subu(r_A, r_A, r_X, ctx);
950 case BPF_S_ALU_MUL_K:
952 /* Load K to scratch register before MUL */
953 ctx->flags |= SEEN_A | SEEN_S0;
954 emit_load_imm(r_s0, k, ctx);
955 emit_mul(r_A, r_A, r_s0, ctx);
957 case BPF_S_ALU_MUL_X:
959 update_on_xread(ctx);
960 ctx->flags |= SEEN_A | SEEN_X;
961 emit_mul(r_A, r_A, r_X, ctx);
963 case BPF_S_ALU_DIV_K:
967 if (optimize_div(&k)) {
968 ctx->flags |= SEEN_A;
969 emit_srl(r_A, r_A, k, ctx);
972 ctx->flags |= SEEN_A | SEEN_S0;
973 emit_load_imm(r_s0, k, ctx);
974 emit_div(r_A, r_s0, ctx);
976 case BPF_S_ALU_MOD_K:
978 if (k == 1 || optimize_div(&k)) {
979 ctx->flags |= SEEN_A;
980 emit_jit_reg_move(r_A, r_zero, ctx);
982 ctx->flags |= SEEN_A | SEEN_S0;
983 emit_load_imm(r_s0, k, ctx);
984 emit_mod(r_A, r_s0, ctx);
987 case BPF_S_ALU_DIV_X:
989 update_on_xread(ctx);
990 ctx->flags |= SEEN_X | SEEN_A;
991 /* Check if r_X is zero */
992 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
993 b_imm(prog->len, ctx), ctx);
994 emit_load_imm(r_val, 0, ctx); /* delay slot */
995 emit_div(r_A, r_X, ctx);
997 case BPF_S_ALU_MOD_X:
999 update_on_xread(ctx);
1000 ctx->flags |= SEEN_X | SEEN_A;
1001 /* Check if r_X is zero */
1002 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
1003 b_imm(prog->len, ctx), ctx);
1004 emit_load_imm(r_val, 0, ctx); /* delay slot */
1005 emit_mod(r_A, r_X, ctx);
1007 case BPF_S_ALU_OR_K:
1009 ctx->flags |= SEEN_A;
1010 emit_ori(r_A, r_A, k, ctx);
1012 case BPF_S_ALU_OR_X:
1014 update_on_xread(ctx);
1015 ctx->flags |= SEEN_A;
1016 emit_ori(r_A, r_A, r_X, ctx);
1018 case BPF_S_ALU_XOR_K:
1020 ctx->flags |= SEEN_A;
1021 emit_xori(r_A, r_A, k, ctx);
1023 case BPF_S_ANC_ALU_XOR_X:
1024 case BPF_S_ALU_XOR_X:
1026 update_on_xread(ctx);
1027 ctx->flags |= SEEN_A;
1028 emit_xor(r_A, r_A, r_X, ctx);
1030 case BPF_S_ALU_AND_K:
1032 ctx->flags |= SEEN_A;
1033 emit_andi(r_A, r_A, k, ctx);
1035 case BPF_S_ALU_AND_X:
1037 update_on_xread(ctx);
1038 ctx->flags |= SEEN_A | SEEN_X;
1039 emit_and(r_A, r_A, r_X, ctx);
1041 case BPF_S_ALU_LSH_K:
1043 ctx->flags |= SEEN_A;
1044 emit_sll(r_A, r_A, k, ctx);
1046 case BPF_S_ALU_LSH_X:
1048 ctx->flags |= SEEN_A | SEEN_X;
1049 update_on_xread(ctx);
1050 emit_sllv(r_A, r_A, r_X, ctx);
1052 case BPF_S_ALU_RSH_K:
1054 ctx->flags |= SEEN_A;
1055 emit_srl(r_A, r_A, k, ctx);
1057 case BPF_S_ALU_RSH_X:
1058 ctx->flags |= SEEN_A | SEEN_X;
1059 update_on_xread(ctx);
1060 emit_srlv(r_A, r_A, r_X, ctx);
1064 ctx->flags |= SEEN_A;
1069 emit_b(b_imm(i + k + 1, ctx), ctx);
1072 case BPF_S_JMP_JEQ_K:
1073 /* pc += ( A == K ) ? pc->jt : pc->jf */
1074 condt = MIPS_COND_EQ | MIPS_COND_K;
1076 case BPF_S_JMP_JEQ_X:
1077 ctx->flags |= SEEN_X;
1078 /* pc += ( A == X ) ? pc->jt : pc->jf */
1079 condt = MIPS_COND_EQ | MIPS_COND_X;
1081 case BPF_S_JMP_JGE_K:
1082 /* pc += ( A >= K ) ? pc->jt : pc->jf */
1083 condt = MIPS_COND_GE | MIPS_COND_K;
1085 case BPF_S_JMP_JGE_X:
1086 ctx->flags |= SEEN_X;
1087 /* pc += ( A >= X ) ? pc->jt : pc->jf */
1088 condt = MIPS_COND_GE | MIPS_COND_X;
1090 case BPF_S_JMP_JGT_K:
1091 /* pc += ( A > K ) ? pc->jt : pc->jf */
1092 condt = MIPS_COND_GT | MIPS_COND_K;
1094 case BPF_S_JMP_JGT_X:
1095 ctx->flags |= SEEN_X;
1096 /* pc += ( A > X ) ? pc->jt : pc->jf */
1097 condt = MIPS_COND_GT | MIPS_COND_X;
1099 /* Greater or Equal */
1100 if ((condt & MIPS_COND_GE) ||
1101 (condt & MIPS_COND_GT)) {
1102 if (condt & MIPS_COND_K) { /* K */
1103 ctx->flags |= SEEN_S0 | SEEN_A;
1104 emit_sltiu(r_s0, r_A, k, ctx);
1106 ctx->flags |= SEEN_S0 | SEEN_A |
1108 emit_sltu(r_s0, r_A, r_X, ctx);
1110 /* A < (K|X) ? r_scrach = 1 */
1111 b_off = b_imm(i + inst->jf + 1, ctx);
1112 emit_bcond(MIPS_COND_GT, r_s0, r_zero, b_off,
1115 /* A > (K|X) ? scratch = 0 */
1116 if (condt & MIPS_COND_GT) {
1117 /* Checking for equality */
1118 ctx->flags |= SEEN_S0 | SEEN_A | SEEN_X;
1119 if (condt & MIPS_COND_K)
1120 emit_load_imm(r_s0, k, ctx);
1122 emit_jit_reg_move(r_s0, r_X,
1124 b_off = b_imm(i + inst->jf + 1, ctx);
1125 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1128 /* Finally, A > K|X */
1129 b_off = b_imm(i + inst->jt + 1, ctx);
1133 /* A >= (K|X) so jump */
1134 b_off = b_imm(i + inst->jt + 1, ctx);
1140 if (condt & MIPS_COND_K) { /* K */
1141 ctx->flags |= SEEN_S0 | SEEN_A;
1142 emit_load_imm(r_s0, k, ctx);
1144 b_off = b_imm(i + inst->jt + 1, ctx);
1145 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1149 b_off = b_imm(i + inst->jf + 1,
1151 emit_bcond(MIPS_COND_NE, r_A, r_s0,
1156 ctx->flags |= SEEN_A | SEEN_X;
1157 b_off = b_imm(i + inst->jt + 1,
1159 emit_bcond(MIPS_COND_EQ, r_A, r_X,
1163 b_off = b_imm(i + inst->jf + 1, ctx);
1164 emit_bcond(MIPS_COND_NE, r_A, r_X,
1170 case BPF_S_JMP_JSET_K:
1171 ctx->flags |= SEEN_S0 | SEEN_S1 | SEEN_A;
1172 /* pc += (A & K) ? pc -> jt : pc -> jf */
1173 emit_load_imm(r_s1, k, ctx);
1174 emit_and(r_s0, r_A, r_s1, ctx);
1176 b_off = b_imm(i + inst->jt + 1, ctx);
1177 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1180 b_off = b_imm(i + inst->jf + 1, ctx);
1184 case BPF_S_JMP_JSET_X:
1185 ctx->flags |= SEEN_S0 | SEEN_X | SEEN_A;
1186 /* pc += (A & X) ? pc -> jt : pc -> jf */
1187 emit_and(r_s0, r_A, r_X, ctx);
1189 b_off = b_imm(i + inst->jt + 1, ctx);
1190 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1193 b_off = b_imm(i + inst->jf + 1, ctx);
1198 ctx->flags |= SEEN_A;
1199 if (i != prog->len - 1)
1201 * If this is not the last instruction
1202 * then jump to the epilogue
1204 emit_b(b_imm(prog->len, ctx), ctx);
1205 emit_reg_move(r_ret, r_A, ctx); /* delay slot */
1209 * It can emit two instructions so it does not fit on
1212 emit_load_imm(r_ret, k, ctx);
1213 if (i != prog->len - 1) {
1215 * If this is not the last instruction
1216 * then jump to the epilogue
1218 emit_b(b_imm(prog->len, ctx), ctx);
1222 case BPF_S_MISC_TAX:
1224 ctx->flags |= SEEN_X | SEEN_A;
1225 emit_jit_reg_move(r_X, r_A, ctx);
1227 case BPF_S_MISC_TXA:
1229 ctx->flags |= SEEN_A | SEEN_X;
1230 update_on_xread(ctx);
1231 emit_jit_reg_move(r_A, r_X, ctx);
1234 case BPF_S_ANC_PROTOCOL:
1235 /* A = ntohs(skb->protocol */
1236 ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A;
1237 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1239 off = offsetof(struct sk_buff, protocol);
1240 emit_half_load(r_A, r_skb, off, ctx);
1241 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1242 /* This needs little endian fixup */
1243 if (cpu_has_mips_r2) {
1244 /* R2 and later have the wsbh instruction */
1245 emit_wsbh(r_A, r_A, ctx);
1247 /* Get first byte */
1248 emit_andi(r_tmp_imm, r_A, 0xff, ctx);
1250 emit_sll(r_tmp, r_tmp_imm, 8, ctx);
1251 /* Get second byte */
1252 emit_srl(r_tmp_imm, r_A, 8, ctx);
1253 emit_andi(r_tmp_imm, r_tmp_imm, 0xff, ctx);
1254 /* Put everyting together in r_A */
1255 emit_or(r_A, r_tmp, r_tmp_imm, ctx);
1260 ctx->flags |= SEEN_A | SEEN_OFF;
1261 /* A = current_thread_info()->cpu */
1262 BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info,
1264 off = offsetof(struct thread_info, cpu);
1265 /* $28/gp points to the thread_info struct */
1266 emit_load(r_A, 28, off, ctx);
1268 case BPF_S_ANC_IFINDEX:
1269 /* A = skb->dev->ifindex */
1270 ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0;
1271 off = offsetof(struct sk_buff, dev);
1272 emit_load(r_s0, r_skb, off, ctx);
1273 /* error (0) in the delay slot */
1274 emit_bcond(MIPS_COND_EQ, r_s0, r_zero,
1275 b_imm(prog->len, ctx), ctx);
1276 emit_reg_move(r_ret, r_zero, ctx);
1277 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
1279 off = offsetof(struct net_device, ifindex);
1280 emit_load(r_A, r_s0, off, ctx);
1282 case BPF_S_ANC_MARK:
1283 ctx->flags |= SEEN_SKB | SEEN_A;
1284 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
1285 off = offsetof(struct sk_buff, mark);
1286 emit_load(r_A, r_skb, off, ctx);
1288 case BPF_S_ANC_RXHASH:
1289 ctx->flags |= SEEN_SKB | SEEN_A;
1290 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
1291 off = offsetof(struct sk_buff, hash);
1292 emit_load(r_A, r_skb, off, ctx);
1294 case BPF_S_ANC_VLAN_TAG:
1295 case BPF_S_ANC_VLAN_TAG_PRESENT:
1296 ctx->flags |= SEEN_SKB | SEEN_S0 | SEEN_A;
1297 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1299 off = offsetof(struct sk_buff, vlan_tci);
1300 emit_half_load(r_s0, r_skb, off, ctx);
1301 if (inst->code == BPF_S_ANC_VLAN_TAG)
1302 emit_and(r_A, r_s0, VLAN_VID_MASK, ctx);
1304 emit_and(r_A, r_s0, VLAN_TAG_PRESENT, ctx);
1306 case BPF_S_ANC_PKTTYPE:
1307 off = pkt_type_offset();
1311 emit_load_byte(r_tmp, r_skb, off, ctx);
1312 /* Keep only the last 3 bits */
1313 emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx);
1315 case BPF_S_ANC_QUEUE:
1316 ctx->flags |= SEEN_SKB | SEEN_A;
1317 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1318 queue_mapping) != 2);
1319 BUILD_BUG_ON(offsetof(struct sk_buff,
1320 queue_mapping) > 0xff);
1321 off = offsetof(struct sk_buff, queue_mapping);
1322 emit_half_load(r_A, r_skb, off, ctx);
1325 pr_warn("%s: Unhandled opcode: 0x%02x\n", __FILE__,
1331 /* compute offsets only during the first pass */
1332 if (ctx->target == NULL)
1333 ctx->offsets[i] = ctx->idx * 4;
1338 int bpf_jit_enable __read_mostly;
1340 void bpf_jit_compile(struct sk_filter *fp)
1343 unsigned int alloc_size, tmp_idx;
1345 if (!bpf_jit_enable)
1348 memset(&ctx, 0, sizeof(ctx));
1350 ctx.offsets = kcalloc(fp->len, sizeof(*ctx.offsets), GFP_KERNEL);
1351 if (ctx.offsets == NULL)
1356 if (build_body(&ctx))
1360 build_prologue(&ctx);
1361 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1362 /* just to complete the ctx.idx count */
1363 build_epilogue(&ctx);
1365 alloc_size = 4 * ctx.idx;
1366 ctx.target = module_alloc(alloc_size);
1367 if (ctx.target == NULL)
1371 memset(ctx.target, 0, alloc_size);
1375 /* Generate the actual JIT code */
1376 build_prologue(&ctx);
1378 build_epilogue(&ctx);
1380 /* Update the icache */
1381 flush_icache_range((ptr)ctx.target, (ptr)(ctx.target + ctx.idx));
1383 if (bpf_jit_enable > 1)
1385 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
1387 fp->bpf_func = (void *)ctx.target;
1394 void bpf_jit_free(struct sk_filter *fp)
1397 module_free(NULL, fp->bpf_func);