2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004, 05, 06 by Ralf Baechle
7 * Copyright (C) 2005 by MIPS Technologies, Inc.
9 #include <linux/cpumask.h>
10 #include <linux/oprofile.h>
11 #include <linux/interrupt.h>
12 #include <linux/smp.h>
13 #include <asm/irq_regs.h>
18 #define M_PERFCTL_EXL (1UL << 0)
19 #define M_PERFCTL_KERNEL (1UL << 1)
20 #define M_PERFCTL_SUPERVISOR (1UL << 2)
21 #define M_PERFCTL_USER (1UL << 3)
22 #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
23 #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
24 #define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
25 #define M_PERFCTL_MT_EN(filter) ((filter) << 20)
26 #define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
27 #define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
28 #define M_TC_EN_TC M_PERFCTL_MT_EN(2)
29 #define M_PERFCTL_TCID(tcid) ((tcid) << 22)
30 #define M_PERFCTL_WIDE (1UL << 30)
31 #define M_PERFCTL_MORE (1UL << 31)
33 #define M_COUNTER_OVERFLOW (1UL << 31)
35 /* Netlogic XLR specific, count events in all threads in a core */
36 #define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13)
38 static int (*save_perf_irq)(void);
39 static int perfcount_irq;
42 * XLR has only one set of counters per core. Designate the
43 * first hardware thread in the core for setup and init.
44 * Skip CPUs with non-zero hardware thread id (4 hwt per core)
46 #if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
47 #define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0)
49 #define oprofile_skip_cpu(c) 0
52 #ifdef CONFIG_MIPS_MT_SMP
53 static int cpu_has_mipsmt_pertccounters;
54 #define WHAT (M_TC_EN_VPE | \
55 M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
56 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
57 0 : cpu_data[smp_processor_id()].vpe_id)
60 * The number of bits to shift to convert between counters per core and
61 * counters per VPE. There is no reasonable interface atm to obtain the
62 * number of VPEs used by Linux and in the 34K this number is fixed to two
63 * anyways so we hardcore a few things here for the moment. The way it's
64 * done here will ensure that oprofile VSMP kernel will run right on a lesser
65 * core like a 24K also or with maxcpus=1.
67 static inline unsigned int vpe_shift(void)
69 if (num_possible_cpus() > 1)
80 static inline unsigned int vpe_shift(void)
87 static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
89 return counters >> vpe_shift();
92 static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
94 return counters << vpe_shift();
97 #define __define_perf_accessors(r, n, np) \
99 static inline unsigned int r_c0_ ## r ## n(void) \
101 unsigned int cpu = vpe_id(); \
105 return read_c0_ ## r ## n(); \
107 return read_c0_ ## r ## np(); \
114 static inline void w_c0_ ## r ## n(unsigned int value) \
116 unsigned int cpu = vpe_id(); \
120 write_c0_ ## r ## n(value); \
123 write_c0_ ## r ## np(value); \
131 __define_perf_accessors(perfcntr, 0, 2)
132 __define_perf_accessors(perfcntr, 1, 3)
133 __define_perf_accessors(perfcntr, 2, 0)
134 __define_perf_accessors(perfcntr, 3, 1)
136 __define_perf_accessors(perfctrl, 0, 2)
137 __define_perf_accessors(perfctrl, 1, 3)
138 __define_perf_accessors(perfctrl, 2, 0)
139 __define_perf_accessors(perfctrl, 3, 1)
141 struct op_mips_model op_model_mipsxx_ops;
143 static struct mipsxx_register_config {
144 unsigned int control[4];
145 unsigned int counter[4];
148 /* Compute all of the registers in preparation for enabling profiling. */
150 static void mipsxx_reg_setup(struct op_counter_config *ctr)
152 unsigned int counters = op_model_mipsxx_ops.num_counters;
155 /* Compute the performance counter control word. */
156 for (i = 0; i < counters; i++) {
163 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
164 M_PERFCTL_INTERRUPT_ENABLE;
166 reg.control[i] |= M_PERFCTL_KERNEL;
168 reg.control[i] |= M_PERFCTL_USER;
170 reg.control[i] |= M_PERFCTL_EXL;
171 if (boot_cpu_type() == CPU_XLR)
172 reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
173 reg.counter[i] = 0x80000000 - ctr[i].count;
177 /* Program all of the registers in preparation for enabling profiling. */
179 static void mipsxx_cpu_setup(void *args)
181 unsigned int counters = op_model_mipsxx_ops.num_counters;
183 if (oprofile_skip_cpu(smp_processor_id()))
189 w_c0_perfcntr3(reg.counter[3]);
192 w_c0_perfcntr2(reg.counter[2]);
195 w_c0_perfcntr1(reg.counter[1]);
198 w_c0_perfcntr0(reg.counter[0]);
202 /* Start all counters on current CPU */
203 static void mipsxx_cpu_start(void *args)
205 unsigned int counters = op_model_mipsxx_ops.num_counters;
207 if (oprofile_skip_cpu(smp_processor_id()))
212 w_c0_perfctrl3(WHAT | reg.control[3]);
214 w_c0_perfctrl2(WHAT | reg.control[2]);
216 w_c0_perfctrl1(WHAT | reg.control[1]);
218 w_c0_perfctrl0(WHAT | reg.control[0]);
222 /* Stop all counters on current CPU */
223 static void mipsxx_cpu_stop(void *args)
225 unsigned int counters = op_model_mipsxx_ops.num_counters;
227 if (oprofile_skip_cpu(smp_processor_id()))
242 static int mipsxx_perfcount_handler(void)
244 unsigned int counters = op_model_mipsxx_ops.num_counters;
245 unsigned int control;
246 unsigned int counter;
247 int handled = IRQ_NONE;
249 if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
253 #define HANDLE_COUNTER(n) \
255 control = r_c0_perfctrl ## n(); \
256 counter = r_c0_perfcntr ## n(); \
257 if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
258 (counter & M_COUNTER_OVERFLOW)) { \
259 oprofile_add_sample(get_irq_regs(), n); \
260 w_c0_perfcntr ## n(reg.counter[n]); \
261 handled = IRQ_HANDLED; \
272 static inline int __n_counters(void)
276 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
278 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
280 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
286 static inline int n_counters(void)
290 switch (current_cpu_type()) {
302 counters = __n_counters();
308 static void reset_counters(void *arg)
310 int counters = (int)(long)arg;
327 static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
329 return mipsxx_perfcount_handler();
332 static int __init mipsxx_init(void)
336 counters = n_counters();
338 printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
342 #ifdef CONFIG_MIPS_MT_SMP
343 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
344 if (!cpu_has_mipsmt_pertccounters)
345 counters = counters_total_to_per_cpu(counters);
347 on_each_cpu(reset_counters, (void *)(long)counters, 1);
349 op_model_mipsxx_ops.num_counters = counters;
350 switch (current_cpu_type()) {
352 op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
356 op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
360 op_model_mipsxx_ops.cpu_type = "mips/20K";
364 op_model_mipsxx_ops.cpu_type = "mips/24K";
368 op_model_mipsxx_ops.cpu_type = "mips/25K";
373 op_model_mipsxx_ops.cpu_type = "mips/34K";
378 op_model_mipsxx_ops.cpu_type = "mips/74K";
382 op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
386 op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
390 op_model_mipsxx_ops.cpu_type = "mips/P5600";
394 op_model_mipsxx_ops.cpu_type = "mips/I6400";
398 op_model_mipsxx_ops.cpu_type = "mips/M5150";
402 op_model_mipsxx_ops.cpu_type = "mips/5K";
406 if ((current_cpu_data.processor_id & 0xff) == 0x20)
407 op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
409 op_model_mipsxx_ops.cpu_type = "mips/r10000";
414 op_model_mipsxx_ops.cpu_type = "mips/r12000";
418 op_model_mipsxx_ops.cpu_type = "mips/r16000";
423 op_model_mipsxx_ops.cpu_type = "mips/sb1";
427 op_model_mipsxx_ops.cpu_type = "mips/loongson1";
431 op_model_mipsxx_ops.cpu_type = "mips/xlr";
435 printk(KERN_ERR "Profiling unsupported for this CPU\n");
440 save_perf_irq = perf_irq;
441 perf_irq = mipsxx_perfcount_handler;
443 if (get_c0_perfcount_int)
444 perfcount_irq = get_c0_perfcount_int();
445 else if (cp0_perfcount_irq >= 0)
446 perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
450 if (perfcount_irq >= 0)
451 return request_irq(perfcount_irq, mipsxx_perfcount_int,
452 IRQF_PERCPU | IRQF_NOBALANCING |
453 IRQF_NO_THREAD | IRQF_NO_SUSPEND |
455 "Perfcounter", save_perf_irq);
460 static void mipsxx_exit(void)
462 int counters = op_model_mipsxx_ops.num_counters;
464 if (perfcount_irq >= 0)
465 free_irq(perfcount_irq, save_perf_irq);
467 counters = counters_per_cpu_to_total(counters);
468 on_each_cpu(reset_counters, (void *)(long)counters, 1);
470 perf_irq = save_perf_irq;
473 struct op_mips_model op_model_mipsxx_ops = {
474 .reg_setup = mipsxx_reg_setup,
475 .cpu_setup = mipsxx_cpu_setup,
478 .cpu_start = mipsxx_cpu_start,
479 .cpu_stop = mipsxx_cpu_stop,