2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004, 05, 06 by Ralf Baechle
7 * Copyright (C) 2005 by MIPS Technologies, Inc.
9 #include <linux/cpumask.h>
10 #include <linux/oprofile.h>
11 #include <linux/interrupt.h>
12 #include <linux/smp.h>
13 #include <asm/irq_regs.h>
17 #define M_PERFCTL_EXL (1UL << 0)
18 #define M_PERFCTL_KERNEL (1UL << 1)
19 #define M_PERFCTL_SUPERVISOR (1UL << 2)
20 #define M_PERFCTL_USER (1UL << 3)
21 #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
22 #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
23 #define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
24 #define M_PERFCTL_MT_EN(filter) ((filter) << 20)
25 #define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
26 #define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
27 #define M_TC_EN_TC M_PERFCTL_MT_EN(2)
28 #define M_PERFCTL_TCID(tcid) ((tcid) << 22)
29 #define M_PERFCTL_WIDE (1UL << 30)
30 #define M_PERFCTL_MORE (1UL << 31)
32 #define M_COUNTER_OVERFLOW (1UL << 31)
34 /* Netlogic XLR specific, count events in all threads in a core */
35 #define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13)
37 static int (*save_perf_irq)(void);
40 * XLR has only one set of counters per core. Designate the
41 * first hardware thread in the core for setup and init.
42 * Skip CPUs with non-zero hardware thread id (4 hwt per core)
44 #if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
45 #define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0)
47 #define oprofile_skip_cpu(c) 0
50 #ifdef CONFIG_MIPS_MT_SMP
51 static int cpu_has_mipsmt_pertccounters;
52 #define WHAT (M_TC_EN_VPE | \
53 M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
54 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
55 0 : cpu_data[smp_processor_id()].vpe_id)
58 * The number of bits to shift to convert between counters per core and
59 * counters per VPE. There is no reasonable interface atm to obtain the
60 * number of VPEs used by Linux and in the 34K this number is fixed to two
61 * anyways so we hardcore a few things here for the moment. The way it's
62 * done here will ensure that oprofile VSMP kernel will run right on a lesser
63 * core like a 24K also or with maxcpus=1.
65 static inline unsigned int vpe_shift(void)
67 if (num_possible_cpus() > 1)
78 static inline unsigned int vpe_shift(void)
85 static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
87 return counters >> vpe_shift();
90 static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
92 return counters << vpe_shift();
95 #define __define_perf_accessors(r, n, np) \
97 static inline unsigned int r_c0_ ## r ## n(void) \
99 unsigned int cpu = vpe_id(); \
103 return read_c0_ ## r ## n(); \
105 return read_c0_ ## r ## np(); \
112 static inline void w_c0_ ## r ## n(unsigned int value) \
114 unsigned int cpu = vpe_id(); \
118 write_c0_ ## r ## n(value); \
121 write_c0_ ## r ## np(value); \
129 __define_perf_accessors(perfcntr, 0, 2)
130 __define_perf_accessors(perfcntr, 1, 3)
131 __define_perf_accessors(perfcntr, 2, 0)
132 __define_perf_accessors(perfcntr, 3, 1)
134 __define_perf_accessors(perfctrl, 0, 2)
135 __define_perf_accessors(perfctrl, 1, 3)
136 __define_perf_accessors(perfctrl, 2, 0)
137 __define_perf_accessors(perfctrl, 3, 1)
139 struct op_mips_model op_model_mipsxx_ops;
141 static struct mipsxx_register_config {
142 unsigned int control[4];
143 unsigned int counter[4];
146 /* Compute all of the registers in preparation for enabling profiling. */
148 static void mipsxx_reg_setup(struct op_counter_config *ctr)
150 unsigned int counters = op_model_mipsxx_ops.num_counters;
153 /* Compute the performance counter control word. */
154 for (i = 0; i < counters; i++) {
161 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
162 M_PERFCTL_INTERRUPT_ENABLE;
164 reg.control[i] |= M_PERFCTL_KERNEL;
166 reg.control[i] |= M_PERFCTL_USER;
168 reg.control[i] |= M_PERFCTL_EXL;
169 if (boot_cpu_type() == CPU_XLR)
170 reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
171 reg.counter[i] = 0x80000000 - ctr[i].count;
175 /* Program all of the registers in preparation for enabling profiling. */
177 static void mipsxx_cpu_setup(void *args)
179 unsigned int counters = op_model_mipsxx_ops.num_counters;
181 if (oprofile_skip_cpu(smp_processor_id()))
187 w_c0_perfcntr3(reg.counter[3]);
190 w_c0_perfcntr2(reg.counter[2]);
193 w_c0_perfcntr1(reg.counter[1]);
196 w_c0_perfcntr0(reg.counter[0]);
200 /* Start all counters on current CPU */
201 static void mipsxx_cpu_start(void *args)
203 unsigned int counters = op_model_mipsxx_ops.num_counters;
205 if (oprofile_skip_cpu(smp_processor_id()))
210 w_c0_perfctrl3(WHAT | reg.control[3]);
212 w_c0_perfctrl2(WHAT | reg.control[2]);
214 w_c0_perfctrl1(WHAT | reg.control[1]);
216 w_c0_perfctrl0(WHAT | reg.control[0]);
220 /* Stop all counters on current CPU */
221 static void mipsxx_cpu_stop(void *args)
223 unsigned int counters = op_model_mipsxx_ops.num_counters;
225 if (oprofile_skip_cpu(smp_processor_id()))
240 static int mipsxx_perfcount_handler(void)
242 unsigned int counters = op_model_mipsxx_ops.num_counters;
243 unsigned int control;
244 unsigned int counter;
245 int handled = IRQ_NONE;
247 if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
251 #define HANDLE_COUNTER(n) \
253 control = r_c0_perfctrl ## n(); \
254 counter = r_c0_perfcntr ## n(); \
255 if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
256 (counter & M_COUNTER_OVERFLOW)) { \
257 oprofile_add_sample(get_irq_regs(), n); \
258 w_c0_perfcntr ## n(reg.counter[n]); \
259 handled = IRQ_HANDLED; \
270 #define M_CONFIG1_PC (1 << 4)
272 static inline int __n_counters(void)
274 if (!(read_c0_config1() & M_CONFIG1_PC))
276 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
278 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
280 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
286 static inline int n_counters(void)
290 switch (current_cpu_type()) {
301 counters = __n_counters();
307 static void reset_counters(void *arg)
309 int counters = (int)(long)arg;
326 static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
328 return mipsxx_perfcount_handler();
331 static int __init mipsxx_init(void)
335 counters = n_counters();
337 printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
341 #ifdef CONFIG_MIPS_MT_SMP
342 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
343 if (!cpu_has_mipsmt_pertccounters)
344 counters = counters_total_to_per_cpu(counters);
346 on_each_cpu(reset_counters, (void *)(long)counters, 1);
348 op_model_mipsxx_ops.num_counters = counters;
349 switch (current_cpu_type()) {
351 op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
355 op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
359 op_model_mipsxx_ops.cpu_type = "mips/20K";
363 op_model_mipsxx_ops.cpu_type = "mips/24K";
367 op_model_mipsxx_ops.cpu_type = "mips/25K";
372 op_model_mipsxx_ops.cpu_type = "mips/34K";
377 op_model_mipsxx_ops.cpu_type = "mips/74K";
381 op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
385 op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
389 op_model_mipsxx_ops.cpu_type = "mips/P5600";
393 op_model_mipsxx_ops.cpu_type = "mips/M5150";
397 op_model_mipsxx_ops.cpu_type = "mips/5K";
401 if ((current_cpu_data.processor_id & 0xff) == 0x20)
402 op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
404 op_model_mipsxx_ops.cpu_type = "mips/r10000";
409 op_model_mipsxx_ops.cpu_type = "mips/r12000";
414 op_model_mipsxx_ops.cpu_type = "mips/sb1";
418 op_model_mipsxx_ops.cpu_type = "mips/loongson1";
422 op_model_mipsxx_ops.cpu_type = "mips/xlr";
426 printk(KERN_ERR "Profiling unsupported for this CPU\n");
431 save_perf_irq = perf_irq;
432 perf_irq = mipsxx_perfcount_handler;
434 if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
435 return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
436 0, "Perfcounter", save_perf_irq);
441 static void mipsxx_exit(void)
443 int counters = op_model_mipsxx_ops.num_counters;
445 if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
446 free_irq(cp0_perfcount_irq, save_perf_irq);
448 counters = counters_per_cpu_to_total(counters);
449 on_each_cpu(reset_counters, (void *)(long)counters, 1);
451 perf_irq = save_perf_irq;
454 struct op_mips_model op_model_mipsxx_ops = {
455 .reg_setup = mipsxx_reg_setup,
456 .cpu_setup = mipsxx_cpu_setup,
459 .cpu_start = mipsxx_cpu_start,
460 .cpu_stop = mipsxx_cpu_stop,