2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000, 2001 Keith M Wesolowski
8 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <asm/ip32/mace.h>
14 # define DPRINTK(args...) printk(args);
16 # define DPRINTK(args...)
20 * O2 has up to 5 PCI devices connected into the MACE bridge. The device
21 * map looks like this:
30 static inline int mkaddr(struct pci_bus *bus, unsigned int devfn,
33 return ((bus->number & 0xff) << 16) |
34 ((devfn & 0xff) << 8) |
40 mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
41 int reg, int size, u32 *val)
43 u32 control = mace->pci.control;
45 /* disable master aborts interrupts during config read */
46 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
47 mace->pci.config_addr = mkaddr(bus, devfn, reg);
50 *val = mace->pci.config_data.b[(reg & 3) ^ 3];
53 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
56 *val = mace->pci.config_data.l;
59 /* ack possible master abort */
60 mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
61 mace->pci.control = control;
63 * someone forgot to set the ultra bit for the onboard
64 * scsi chips; we fake it here
66 if (bus->number == 0 && reg == 0x40 && size == 4 &&
67 (devfn == (1 << 3) || devfn == (2 << 3)))
70 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
72 return PCIBIOS_SUCCESSFUL;
76 mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
77 int reg, int size, u32 val)
79 mace->pci.config_addr = mkaddr(bus, devfn, reg);
82 mace->pci.config_data.b[(reg & 3) ^ 3] = val;
85 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
88 mace->pci.config_data.l = val;
92 DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
94 return PCIBIOS_SUCCESSFUL;
97 struct pci_ops mace_pci_ops = {
98 .read = mace_pci_read_config,
99 .write = mace_pci_write_config,