2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2011 Wind River Systems,
9 * written by Ralf Baechle (ralf@linux-mips.org)
11 #include <linux/bug.h>
12 #include <linux/kernel.h>
14 #include <linux/bootmem.h>
15 #include <linux/export.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/of_address.h>
21 #include <asm/cpu-info.h>
24 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
29 * The PCI controller list.
31 static LIST_HEAD(controllers);
33 unsigned long PCIBIOS_MIN_IO;
34 unsigned long PCIBIOS_MIN_MEM;
36 static int pci_initialized;
39 * We need to avoid collisions with `mirrored' VGA ports
40 * and other strange ISA hardware, so we always want the
41 * addresses to be allocated in the 0x000-0x0ff region
44 * Why? Because some silly external IO cards only decode
45 * the low 10 bits of the IO address. The 0x00-0xff region
46 * is reserved for motherboard devices that decode all 16
47 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
48 * but we want to try to avoid allocating at 0x2900-0x2bff
49 * which might have be mirrored at 0x0100-0x03ff..
52 pcibios_align_resource(void *data, const struct resource *res,
53 resource_size_t size, resource_size_t align)
55 struct pci_dev *dev = data;
56 struct pci_controller *hose = dev->sysdata;
57 resource_size_t start = res->start;
59 if (res->flags & IORESOURCE_IO) {
60 /* Make sure we start at our min on all hoses */
61 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
62 start = PCIBIOS_MIN_IO + hose->io_resource->start;
65 * Put everything into 0x00-0xff region modulo 0x400
68 start = (start + 0x3ff) & ~0x3ff;
69 } else if (res->flags & IORESOURCE_MEM) {
70 /* Make sure we start at our min on all hoses */
71 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
72 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
78 static void pcibios_scanbus(struct pci_controller *hose)
80 static int next_busno;
81 static int need_domain_info;
85 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
86 next_busno = (*hose->get_busno)();
88 pci_add_resource_offset(&resources,
89 hose->mem_resource, hose->mem_offset);
90 pci_add_resource_offset(&resources,
91 hose->io_resource, hose->io_offset);
92 pci_add_resource_offset(&resources,
93 hose->busn_resource, hose->busn_offset);
94 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
98 need_domain_info = need_domain_info || pci_domain_nr(bus);
99 set_pci_need_domain_info(hose, need_domain_info);
102 pci_free_resource_list(&resources);
106 next_busno = bus->busn_res.end + 1;
107 /* Don't allow 8-bit bus number overflow inside the hose -
108 reserve some space for bridges. */
109 if (next_busno > 224) {
111 need_domain_info = 1;
115 * We insert PCI resources into the iomem_resource and
116 * ioport_resource trees in either pci_bus_claim_resources()
117 * or pci_bus_assign_resources().
119 if (pci_has_flag(PCI_PROBE_ONLY)) {
120 pci_bus_claim_resources(bus);
122 pci_bus_size_bridges(bus);
123 pci_bus_assign_resources(bus);
125 pci_bus_add_devices(bus);
129 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
131 struct of_pci_range range;
132 struct of_pci_range_parser parser;
134 pr_info("PCI host bridge %s ranges:\n", node->full_name);
135 hose->of_node = node;
137 if (of_pci_range_parser_init(&parser, node))
140 for_each_of_pci_range(&parser, &range) {
141 struct resource *res = NULL;
143 switch (range.flags & IORESOURCE_TYPE_BITS) {
145 pr_info(" IO 0x%016llx..0x%016llx\n",
147 range.cpu_addr + range.size - 1);
149 (unsigned long)ioremap(range.cpu_addr,
151 res = hose->io_resource;
154 pr_info(" MEM 0x%016llx..0x%016llx\n",
156 range.cpu_addr + range.size - 1);
157 res = hose->mem_resource;
161 of_pci_range_to_resource(&range, node, res);
165 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
167 struct pci_controller *hose = bus->sysdata;
169 return of_node_get(hose->of_node);
173 static DEFINE_MUTEX(pci_scan_mutex);
175 void register_pci_controller(struct pci_controller *hose)
177 struct resource *parent;
179 parent = hose->mem_resource->parent;
181 parent = &iomem_resource;
183 if (request_resource(parent, hose->mem_resource) < 0)
186 parent = hose->io_resource->parent;
188 parent = &ioport_resource;
190 if (request_resource(parent, hose->io_resource) < 0) {
191 release_resource(hose->mem_resource);
195 INIT_LIST_HEAD(&hose->list);
196 list_add(&hose->list, &controllers);
199 * Do not panic here but later - this might happen before console init.
201 if (!hose->io_map_base) {
203 "registering PCI controller with io_map_base unset\n");
207 * Scan the bus if it is register after the PCI subsystem
210 if (pci_initialized) {
211 mutex_lock(&pci_scan_mutex);
212 pcibios_scanbus(hose);
213 mutex_unlock(&pci_scan_mutex);
220 "Skipping PCI bus scan due to resource conflict\n");
223 static int __init pcibios_set_cache_line_size(void)
225 struct cpuinfo_mips *c = ¤t_cpu_data;
229 * Set PCI cacheline size to that of the highest level in the
232 lsize = c->dcache.linesz;
233 lsize = c->scache.linesz ? : lsize;
234 lsize = c->tcache.linesz ? : lsize;
238 pci_dfl_cache_line_size = lsize >> 2;
240 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
243 arch_initcall(pcibios_set_cache_line_size);
245 static int __init pcibios_init(void)
247 struct pci_controller *hose;
249 /* Scan all of the recorded PCI controllers. */
250 list_for_each_entry(hose, &controllers, list)
251 pcibios_scanbus(hose);
253 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
260 subsys_initcall(pcibios_init);
262 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
268 pci_read_config_word(dev, PCI_COMMAND, &cmd);
270 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
271 /* Only set up the requested stuff */
272 if (!(mask & (1<<idx)))
275 r = &dev->resource[idx];
276 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
278 if ((idx == PCI_ROM_RESOURCE) &&
279 (!(r->flags & IORESOURCE_ROM_ENABLE)))
281 if (!r->start && r->end) {
282 printk(KERN_ERR "PCI: Device %s not available "
283 "because of resource collisions\n",
287 if (r->flags & IORESOURCE_IO)
288 cmd |= PCI_COMMAND_IO;
289 if (r->flags & IORESOURCE_MEM)
290 cmd |= PCI_COMMAND_MEMORY;
292 if (cmd != old_cmd) {
293 printk("PCI: Enabling device %s (%04x -> %04x)\n",
294 pci_name(dev), old_cmd, cmd);
295 pci_write_config_word(dev, PCI_COMMAND, cmd);
300 unsigned int pcibios_assign_all_busses(void)
305 int pcibios_enable_device(struct pci_dev *dev, int mask)
309 if ((err = pcibios_enable_resources(dev, mask)) < 0)
312 return pcibios_plat_dev_init(dev);
315 void pcibios_fixup_bus(struct pci_bus *bus)
317 struct pci_dev *dev = bus->self;
319 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
320 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
321 pci_read_bridge_bases(bus);
325 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
326 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
328 void pci_resource_to_user(const struct pci_dev *dev, int bar,
329 const struct resource *rsrc, resource_size_t *start,
330 resource_size_t *end)
332 phys_addr_t size = resource_size(rsrc);
334 *start = fixup_bigphys_addr(rsrc->start, size);
335 *end = rsrc->start + size;
338 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
339 enum pci_mmap_state mmap_state, int write_combine)
344 * I/O space can be accessed via normal processor loads and stores on
345 * this platform but for now we elect not to do this and portable
346 * drivers should not do this anyway.
348 if (mmap_state == pci_mmap_io)
352 * Ignore write-combine; for now only return uncached mappings.
354 prot = pgprot_val(vma->vm_page_prot);
355 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
356 vma->vm_page_prot = __pgprot(prot);
358 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
359 vma->vm_end - vma->vm_start, vma->vm_page_prot);
362 char * (*pcibios_plat_setup)(char *str) __initdata;
364 char *__init pcibios_setup(char *str)
366 if (pcibios_plat_setup)
367 return pcibios_plat_setup(str);