2 * RouterBoard 500 Platform devices
4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/ctype.h>
20 #include <linux/string.h>
21 #include <linux/platform_device.h>
22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/gpio_keys.h>
26 #include <linux/input.h>
27 #include <linux/serial_8250.h>
29 #include <asm/bootinfo.h>
31 #include <asm/mach-rc32434/rc32434.h>
32 #include <asm/mach-rc32434/dma.h>
33 #include <asm/mach-rc32434/dma_v.h>
34 #include <asm/mach-rc32434/eth.h>
35 #include <asm/mach-rc32434/rb.h>
36 #include <asm/mach-rc32434/integ.h>
37 #include <asm/mach-rc32434/gpio.h>
38 #include <asm/mach-rc32434/irq.h>
40 #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
41 #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
43 extern unsigned int idt_cpu_freq;
45 static struct mpmc_device dev3;
47 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
51 spin_lock_irqsave(&dev3.lock, flags);
53 dev3.state = (dev3.state | or_mask) & ~nand_mask;
54 writeb(dev3.state, dev3.base);
56 spin_unlock_irqrestore(&dev3.lock, flags);
58 EXPORT_SYMBOL(set_latch_u5);
60 unsigned char get_latch_u5(void)
64 EXPORT_SYMBOL(get_latch_u5);
66 static struct resource rb532_dev3_ctl_res[] = {
69 .flags = IORESOURCE_MEM,
73 static struct resource korina_dev0_res[] = {
75 .name = "korina_regs",
76 .start = ETH0_BASE_ADDR,
77 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
78 .flags = IORESOURCE_MEM,
81 .start = ETH0_DMA_RX_IRQ,
82 .end = ETH0_DMA_RX_IRQ,
83 .flags = IORESOURCE_IRQ
86 .start = ETH0_DMA_TX_IRQ,
87 .end = ETH0_DMA_TX_IRQ,
88 .flags = IORESOURCE_IRQ
91 .start = ETH0_RX_OVR_IRQ,
92 .end = ETH0_RX_OVR_IRQ,
93 .flags = IORESOURCE_IRQ
96 .start = ETH0_TX_UND_IRQ,
97 .end = ETH0_TX_UND_IRQ,
98 .flags = IORESOURCE_IRQ
100 .name = "korina_dma_rx",
101 .start = ETH0_RX_DMA_ADDR,
102 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
103 .flags = IORESOURCE_MEM,
105 .name = "korina_dma_tx",
106 .start = ETH0_TX_DMA_ADDR,
107 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
108 .flags = IORESOURCE_MEM,
112 static struct korina_device korina_dev0_data = {
114 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
117 static struct platform_device korina_dev0 = {
120 .dev.driver_data = &korina_dev0_data,
121 .resource = korina_dev0_res,
122 .num_resources = ARRAY_SIZE(korina_dev0_res),
125 static struct resource cf_slot0_res[] = {
127 .name = "cf_membase",
128 .flags = IORESOURCE_MEM
131 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
132 .end = (8 + 4 * 32 + CF_GPIO_NUM),
133 .flags = IORESOURCE_IRQ
137 static struct cf_device cf_slot0_data = {
138 .gpio_pin = CF_GPIO_NUM
141 static struct platform_device cf_slot0 = {
143 .name = "pata-rb532-cf",
144 .dev.platform_data = &cf_slot0_data,
145 .resource = cf_slot0_res,
146 .num_resources = ARRAY_SIZE(cf_slot0_res),
149 /* Resources and device for NAND */
150 static int rb532_dev_ready(struct mtd_info *mtd)
152 return gpio_get_value(GPIO_RDY);
155 static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
157 struct nand_chip *chip = mtd->priv;
158 unsigned char orbits, nandbits;
160 if (ctrl & NAND_CTRL_CHANGE) {
161 orbits = (ctrl & NAND_CLE) << 1;
162 orbits |= (ctrl & NAND_ALE) >> 1;
164 nandbits = (~ctrl & NAND_CLE) << 1;
165 nandbits |= (~ctrl & NAND_ALE) >> 1;
167 set_latch_u5(orbits, nandbits);
169 if (cmd != NAND_CMD_NONE)
170 writeb(cmd, chip->IO_ADDR_W);
173 static struct resource nand_slot0_res[] = {
175 .name = "nand_membase",
176 .flags = IORESOURCE_MEM
180 static struct platform_nand_data rb532_nand_data = {
181 .ctrl.dev_ready = rb532_dev_ready,
182 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
185 static struct platform_device nand_slot0 = {
188 .resource = nand_slot0_res,
189 .num_resources = ARRAY_SIZE(nand_slot0_res),
190 .dev.platform_data = &rb532_nand_data,
193 static struct mtd_partition rb532_partition_info[] = {
195 .name = "Routerboard NAND boot",
197 .size = 4 * 1024 * 1024,
200 .offset = MTDPART_OFS_NXTBLK,
201 .size = MTDPART_SIZ_FULL,
205 static struct platform_device rb532_led = {
210 static struct gpio_keys_button rb532_gpio_btn[] = {
219 static struct gpio_keys_platform_data rb532_gpio_btn_data = {
220 .buttons = rb532_gpio_btn,
221 .nbuttons = ARRAY_SIZE(rb532_gpio_btn),
224 static struct platform_device rb532_button = {
228 .platform_data = &rb532_gpio_btn_data,
232 static struct resource rb532_wdt_res[] = {
234 .name = "rb532_wdt_res",
235 .start = INTEG0_BASE_ADDR,
236 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
237 .flags = IORESOURCE_MEM,
241 static struct platform_device rb532_wdt = {
242 .name = "rc32434_wdt",
244 .resource = rb532_wdt_res,
245 .num_resources = ARRAY_SIZE(rb532_wdt_res),
248 static struct plat_serial8250_port rb532_uart_res[] = {
250 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
254 .flags = UPF_BOOT_AUTOCONF,
261 static struct platform_device rb532_uart = {
262 .name = "serial8250",
263 .id = PLAT8250_DEV_PLATFORM,
264 .dev.platform_data = &rb532_uart_res,
267 static struct platform_device *rb532_devs[] = {
277 static void __init parse_mac_addr(char *macstr)
280 unsigned char result, value;
282 for (i = 0; i < 6; i++) {
285 if (i != 5 && *(macstr + 2) != ':')
288 for (j = 0; j < 2; j++) {
289 if (isxdigit(*macstr)
291 isdigit(*macstr) ? *macstr -
292 '0' : toupper(*macstr) - 'A' + 10) < 16) {
293 result = result * 16 + value;
300 korina_dev0_data.mac[i] = result;
305 /* NAND definitions */
306 #define NAND_CHIP_DELAY 25
308 static void __init rb532_nand_setup(void)
310 switch (mips_machtype) {
311 case MACH_MIKROTIK_RB532A:
312 set_latch_u5(LO_FOFF | LO_CEX,
313 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
316 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
317 LO_ULED | LO_ALE | LO_CLE);
321 /* Setup NAND specific settings */
322 rb532_nand_data.chip.nr_chips = 1;
323 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
324 rb532_nand_data.chip.partitions = rb532_partition_info;
325 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
326 rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
330 static int __init plat_setup_devices(void)
332 /* Look for the CF card reader */
333 if (!readl(IDT434_REG_BASE + DEV1MASK))
334 rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
336 cf_slot0_res[0].start =
337 readl(IDT434_REG_BASE + DEV1BASE);
338 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
341 /* Read the NAND resources from the device controller */
342 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
343 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
345 /* Read the third (multi purpose) resources from the DC */
346 rb532_dev3_ctl_res[0].start = readl(IDT434_REG_BASE + DEV3BASE);
347 rb532_dev3_ctl_res[0].end = rb532_dev3_ctl_res[0].start + 0x1000;
349 dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, 0x1000);
352 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
356 /* Initialise the NAND device */
359 /* set the uart clock to the current cpu frequency */
360 rb532_uart_res[0].uartclk = idt_cpu_freq;
362 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
365 static int __init setup_kmac(char *s)
367 printk(KERN_INFO "korina mac = %s\n", s);
372 __setup("kmac=", setup_kmac);
374 arch_initcall(plat_setup_devices);