2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
17 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
18 * Copyright (C) 2007 MIPS Technologies, Inc.
19 * written by Ralf Baechle <ralf@linux-mips.org>
24 #include <linux/device.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/vmalloc.h>
33 #include <linux/errno.h>
34 #include <linux/wait.h>
36 #include <asm/sibyte/sb1250.h>
38 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
39 #include <asm/sibyte/bcm1480_regs.h>
40 #include <asm/sibyte/bcm1480_scd.h>
41 #include <asm/sibyte/bcm1480_int.h>
42 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
43 #include <asm/sibyte/sb1250_regs.h>
44 #include <asm/sibyte/sb1250_scd.h>
45 #include <asm/sibyte/sb1250_int.h>
47 #error invalid SiByte UART configuration
50 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
51 #undef K_INT_TRACE_FREEZE
52 #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
54 #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
57 #include <asm/uaccess.h>
59 #define SBPROF_TB_MAJOR 240
61 typedef u64 tb_sample_t[6*256];
70 wait_queue_head_t tb_sync;
71 wait_queue_head_t tb_read;
73 enum open_status open;
74 tb_sample_t *sbprof_tbbuf;
77 volatile int tb_enable;
78 volatile int tb_armed;
82 static struct sbprof_tb sbp;
84 #define MAX_SAMPLE_BYTES (24*1024*1024)
85 #define MAX_TBSAMPLE_BYTES (12*1024*1024)
87 #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
88 #define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
89 #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
92 #define SBPROF_ZBSTART _IOW('s', 0, int)
93 #define SBPROF_ZBSTOP _IOW('s', 1, int)
94 #define SBPROF_ZBWAITFULL _IOW('s', 2, int)
97 * Routines for using 40-bit SCD cycle counter
99 * Client responsible for either handling interrupts or making sure
100 * the cycles counter never saturates, e.g., by doing
101 * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
105 * Configures SCD counter 0 to count ZCLKs starting from val;
106 * Configures SCD counters1,2,3 to count nothing.
107 * Must not be called while gathering ZBbus profiles.
110 #define zclk_timer_init(val) \
111 __asm__ __volatile__ (".set push;" \
113 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
114 "sd %0, 0x10($8);" /* write val to counter0 */ \
115 "sd %1, 0($8);" /* config counter0 for zclks*/ \
118 /* enable, counter0 */ \
119 : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
120 : /* modifies */ "$8" )
123 /* Reads SCD counter 0 and puts result in value
124 unsigned long long val; */
125 #define zclk_get(val) \
126 __asm__ __volatile__ (".set push;" \
128 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
129 "ld %0, 0x10($8);" /* write val to counter0 */ \
131 : /* outputs */ "=r"(val) \
133 : /* modifies */ "$8" )
135 #define DEVNAME "sb_tbprof"
137 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
140 * Support for ZBbus sampling using the trace buffer
142 * We use the SCD performance counter interrupt, caused by a Zclk counter
143 * overflow, to trigger the start of tracing.
145 * We set the trace buffer to sample everything and freeze on
148 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
152 static u64 tb_period;
154 static void arm_tb(void)
157 u64 next = (1ULL << 40) - tb_period;
158 u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
161 * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
162 * trigger start of trace. XXX vary sampling period
164 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
165 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
168 * Unfortunately, in Pass 2 we must clear all counters to knock down
169 * a previous interrupt request. This means that bus profiling
170 * requires ALL of the SCD perf counters.
172 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
173 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
174 /* keep counters 0,2,3,4,5,6,7 as is */
175 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
176 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
178 M_SPC_CFG_ENABLE | /* enable counting */
179 M_SPC_CFG_CLEAR | /* clear all counters */
180 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
181 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
183 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
184 /* keep counters 0,2,3 as is */
185 M_SPC_CFG_ENABLE | /* enable counting */
186 M_SPC_CFG_CLEAR | /* clear all counters */
187 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
188 IOADDR(A_SCD_PERF_CNT_CFG));
190 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
191 /* Reset the trace buffer */
192 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
193 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
194 /* XXXKW may want to expose control to the data-collector */
195 tb_options |= M_SCD_TRACE_CFG_FORCECNT;
197 __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
201 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
205 pr_debug(DEVNAME ": tb_intr\n");
207 if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
208 /* XXX should use XKPHYS to make writes bypass L2 */
209 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
211 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
212 IOADDR(A_SCD_TRACE_CFG));
213 __asm__ __volatile__ ("sync" : : : "memory");
214 /* Loop runs backwards because bundles are read out in reverse order */
215 for (i = 256 * 6; i > 0; i -= 6) {
216 /* Subscripts decrease to put bundle in the order */
217 /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
218 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
220 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
222 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
224 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
226 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
228 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
231 if (!sbp.tb_enable) {
232 pr_debug(DEVNAME ": tb_intr shutdown\n");
233 __raw_writeq(M_SCD_TRACE_CFG_RESET,
234 IOADDR(A_SCD_TRACE_CFG));
236 wake_up_interruptible(&sbp.tb_sync);
238 /* knock down current interrupt and get another one later */
242 /* No more trace buffer samples */
243 pr_debug(DEVNAME ": tb_intr full\n");
244 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
247 wake_up_interruptible(&sbp.tb_sync);
248 wake_up_interruptible(&sbp.tb_read);
253 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
255 printk(DEVNAME ": unexpected pc_intr");
260 * Requires: Already called zclk_timer_init with a value that won't
261 * saturate 40 bits. No subsequent use of SCD performance counters
265 static int sbprof_zbprof_start(struct file *filp)
270 if (xchg(&sbp.tb_enable, 1))
273 pr_debug(DEVNAME ": starting\n");
275 sbp.next_tb_sample = 0;
278 err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
279 DEVNAME " trace freeze", &sbp);
283 /* Make sure there isn't a perf-cnt interrupt waiting */
284 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
285 /* Disable and clear counters, override SRC_1 */
286 __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
287 M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
288 IOADDR(A_SCD_PERF_CNT_CFG));
291 * We grab this interrupt to prevent others from trying to use
292 * it, even though we don't want to service the interrupts
293 * (they only feed into the trace-on-interrupt mechanism)
295 if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
296 free_irq(K_INT_TRACE_FREEZE, &sbp);
301 * I need the core to mask these, but the interrupt mapper to
302 * pass them through. I am exploiting my knowledge that
303 * cp0_status masks out IP[5]. krw
305 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
306 __raw_writeq(K_BCM1480_INT_MAP_I3,
307 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
308 ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
310 __raw_writeq(K_INT_MAP_I3,
311 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
312 (K_INT_PERF_CNT << 3)));
315 /* Initialize address traps */
316 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
317 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
318 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
319 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
321 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
322 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
323 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
324 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
326 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
327 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
328 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
329 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
331 /* Initialize Trace Event 0-7 */
333 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
334 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
335 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
336 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
337 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
338 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
339 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
340 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
342 /* Initialize Trace Sequence 0-7 */
343 /* Start on event 0 (interrupt) */
344 __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
345 IOADDR(A_SCD_TRACE_SEQUENCE_0));
346 /* dsamp when d used | asamp when a used */
347 __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
348 K_SCD_TRSEQ_TRIGGER_ALL,
349 IOADDR(A_SCD_TRACE_SEQUENCE_1));
350 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
351 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
352 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
353 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
354 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
355 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
357 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
358 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
359 __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
360 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
362 __raw_writeq(1ULL << K_INT_PERF_CNT,
363 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
367 pr_debug(DEVNAME ": done starting\n");
372 static int sbprof_zbprof_stop(void)
376 pr_debug(DEVNAME ": stopping\n");
380 * XXXKW there is a window here where the intr handler may run,
381 * see the disable, and do the wake_up before this sleep
384 pr_debug(DEVNAME ": wait for disarm\n");
385 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
386 pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
392 free_irq(K_INT_TRACE_FREEZE, &sbp);
393 free_irq(K_INT_PERF_CNT, &sbp);
396 pr_debug(DEVNAME ": done stopping\n");
401 static int sbprof_tb_open(struct inode *inode, struct file *filp)
405 minor = iminor(inode);
409 if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
412 memset(&sbp, 0, sizeof(struct sbprof_tb));
413 sbp.sbprof_tbbuf = vzalloc(MAX_TBSAMPLE_BYTES);
414 if (!sbp.sbprof_tbbuf) {
415 sbp.open = SB_CLOSED;
420 init_waitqueue_head(&sbp.tb_sync);
421 init_waitqueue_head(&sbp.tb_read);
422 mutex_init(&sbp.lock);
430 static int sbprof_tb_release(struct inode *inode, struct file *filp)
434 minor = iminor(inode);
435 if (minor != 0 || sbp.open != SB_CLOSED)
438 mutex_lock(&sbp.lock);
440 if (sbp.tb_armed || sbp.tb_enable)
441 sbprof_zbprof_stop();
443 vfree(sbp.sbprof_tbbuf);
444 sbp.open = SB_CLOSED;
447 mutex_unlock(&sbp.lock);
452 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
453 size_t size, loff_t *offp)
455 int cur_sample, sample_off, cur_count, sample_left;
459 long cur_off = *offp;
461 if (!access_ok(VERIFY_WRITE, buf, size))
464 mutex_lock(&sbp.lock);
467 cur_sample = cur_off / TB_SAMPLE_SIZE;
468 sample_off = cur_off % TB_SAMPLE_SIZE;
469 sample_left = TB_SAMPLE_SIZE - sample_off;
471 while (size && (cur_sample < sbp.next_tb_sample)) {
474 cur_count = size < sample_left ? size : sample_left;
475 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
476 err = __copy_to_user(dest, src, cur_count);
478 *offp = cur_off + cur_count - err;
479 mutex_unlock(&sbp.lock);
482 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
483 cur_sample, cur_count);
485 sample_left -= cur_count;
489 sample_left = TB_SAMPLE_SIZE;
491 sample_off += cur_count;
493 cur_off += cur_count;
498 mutex_unlock(&sbp.lock);
503 static long sbprof_tb_ioctl(struct file *filp,
504 unsigned int command,
511 mutex_lock(&sbp.lock);
512 err = sbprof_zbprof_start(filp);
513 mutex_unlock(&sbp.lock);
517 mutex_lock(&sbp.lock);
518 err = sbprof_zbprof_stop();
519 mutex_unlock(&sbp.lock);
522 case SBPROF_ZBWAITFULL: {
523 err = wait_event_interruptible(sbp.tb_read, TB_FULL);
527 err = put_user(TB_FULL, (int *) arg);
539 static const struct file_operations sbprof_tb_fops = {
540 .owner = THIS_MODULE,
541 .open = sbprof_tb_open,
542 .release = sbprof_tb_release,
543 .read = sbprof_tb_read,
544 .unlocked_ioctl = sbprof_tb_ioctl,
545 .compat_ioctl = sbprof_tb_ioctl,
547 .llseek = default_llseek,
550 static struct class *tb_class;
551 static struct device *tb_dev;
553 static int __init sbprof_tb_init(void)
559 if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
560 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
565 tbc = class_create(THIS_MODULE, "sb_tracebuffer");
573 dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), NULL, "tb");
580 sbp.open = SB_CLOSED;
582 tb_period = zbbus_mhz * 10000LL;
583 pr_info(DEVNAME ": initialized - tb_period = %lld\n",
584 (long long) tb_period);
588 class_destroy(tb_class);
590 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
595 static void __exit sbprof_tb_cleanup(void)
597 device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
598 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
599 class_destroy(tb_class);
602 module_init(sbprof_tb_init);
603 module_exit(sbprof_tb_cleanup);
605 MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
606 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
607 MODULE_LICENSE("GPL");