2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/smp.h>
25 #include <linux/slab.h>
26 #include <linux/kernel_stat.h>
28 #include <asm/errno.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
34 #include <asm/sibyte/sb1250_regs.h>
35 #include <asm/sibyte/sb1250_int.h>
36 #include <asm/sibyte/sb1250_uart.h>
37 #include <asm/sibyte/sb1250_scd.h>
38 #include <asm/sibyte/sb1250.h>
41 * These are the routines that handle all the low level interrupt stuff.
42 * Actions handled here are: initialization of the interrupt map, requesting of
43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
48 static void end_sb1250_irq(unsigned int irq);
49 static void enable_sb1250_irq(unsigned int irq);
50 static void disable_sb1250_irq(unsigned int irq);
51 static void ack_sb1250_irq(unsigned int irq);
53 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
56 #ifdef CONFIG_SIBYTE_HAS_LDT
57 extern unsigned long ldt_eoi_space;
63 /* Default to UART1 */
65 #ifdef CONFIG_SERIAL_SB1250_DUART
66 extern char sb1250_duart_present[];
70 static struct irq_chip sb1250_irq_type = {
72 .ack = ack_sb1250_irq,
73 .mask = disable_sb1250_irq,
74 .mask_ack = ack_sb1250_irq,
75 .unmask = enable_sb1250_irq,
76 .end = end_sb1250_irq,
78 .set_affinity = sb1250_set_affinity
82 /* Store the CPU id (not the logical number) */
83 int sb1250_irq_owner[SB1250_NR_IRQS];
85 DEFINE_SPINLOCK(sb1250_imr_lock);
87 void sb1250_mask_irq(int cpu, int irq)
92 spin_lock_irqsave(&sb1250_imr_lock, flags);
93 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
94 R_IMR_INTERRUPT_MASK));
95 cur_ints |= (((u64) 1) << irq);
96 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
97 R_IMR_INTERRUPT_MASK));
98 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
101 void sb1250_unmask_irq(int cpu, int irq)
106 spin_lock_irqsave(&sb1250_imr_lock, flags);
107 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
108 R_IMR_INTERRUPT_MASK));
109 cur_ints &= ~(((u64) 1) << irq);
110 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
111 R_IMR_INTERRUPT_MASK));
112 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
116 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
118 int i = 0, old_cpu, cpu, int_on;
120 struct irq_desc *desc = irq_desc + irq;
125 if (cpus_weight(mask) > 1) {
126 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
130 /* Convert logical CPU to physical CPU */
131 cpu = cpu_logical_map(i);
133 /* Protect against other affinity changers and IMR manipulation */
134 spin_lock_irqsave(&desc->lock, flags);
135 spin_lock(&sb1250_imr_lock);
137 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
138 old_cpu = sb1250_irq_owner[irq];
139 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
140 R_IMR_INTERRUPT_MASK));
141 int_on = !(cur_ints & (((u64) 1) << irq));
143 /* If it was on, mask it */
144 cur_ints |= (((u64) 1) << irq);
145 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
146 R_IMR_INTERRUPT_MASK));
148 sb1250_irq_owner[irq] = cpu;
150 /* unmask for the new CPU */
151 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
152 R_IMR_INTERRUPT_MASK));
153 cur_ints &= ~(((u64) 1) << irq);
154 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
155 R_IMR_INTERRUPT_MASK));
157 spin_unlock(&sb1250_imr_lock);
158 spin_unlock_irqrestore(&desc->lock, flags);
162 /*****************************************************************************/
164 static void disable_sb1250_irq(unsigned int irq)
166 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
169 static void enable_sb1250_irq(unsigned int irq)
171 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
175 static void ack_sb1250_irq(unsigned int irq)
177 #ifdef CONFIG_SIBYTE_HAS_LDT
181 * If the interrupt was an HT interrupt, now is the time to
182 * clear it. NOTE: we assume the HT bridge was set up to
183 * deliver the interrupts to all CPUs (which makes affinity
184 * changing easier for us)
186 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
187 R_IMR_LDT_INTERRUPT)));
188 pending &= ((u64)1 << (irq));
191 for (i=0; i<NR_CPUS; i++) {
194 cpu = cpu_logical_map(i);
199 * Clear for all CPUs so an affinity switch
200 * doesn't find an old status
202 __raw_writeq(pending,
203 IOADDR(A_IMR_REGISTER(cpu,
204 R_IMR_LDT_INTERRUPT_CLR)));
208 * Generate EOI. For Pass 1 parts, EOI is a nop. For
209 * Pass 2, the LDT world may be edge-triggered, but
210 * this EOI shouldn't hurt. If they are
211 * level-sensitive, the EOI is required.
213 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
216 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
220 static void end_sb1250_irq(unsigned int irq)
222 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
223 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
228 void __init init_sb1250_irqs(void)
232 for (i = 0; i < SB1250_NR_IRQS; i++) {
233 set_irq_chip(i, &sb1250_irq_type);
234 sb1250_irq_owner[i] = 0;
239 static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id)
244 static struct irqaction sb1250_dummy_action = {
245 .handler = sb1250_dummy_handler,
247 .mask = CPU_MASK_NONE,
248 .name = "sb1250-private",
254 * arch_init_irq is called early in the boot sequence from init/main.c via
255 * init_IRQ. It is responsible for setting up the interrupt mapper and
256 * installing the handler that will be responsible for dispatching interrupts
257 * to the "right" place.
260 * For now, map all interrupts to IP[2]. We could save
261 * some cycles by parceling out system interrupts to different
262 * IP lines, but keep it simple for bringup. We'll also direct
263 * all interrupts to a single CPU; we should probably route
264 * PCI and LDT to one cpu and everything else to the other
265 * to balance the load a bit.
267 * On the second cpu, everything is set to IP5, which is
268 * ignored, EXCEPT the mailbox interrupt. That one is
269 * set to IP[2] so it is handled. This is needed so we
270 * can do cross-cpu function calls, as requred by SMP
273 #define IMR_IP2_VAL K_INT_MAP_I0
274 #define IMR_IP3_VAL K_INT_MAP_I1
275 #define IMR_IP4_VAL K_INT_MAP_I2
276 #define IMR_IP5_VAL K_INT_MAP_I3
277 #define IMR_IP6_VAL K_INT_MAP_I4
279 void __init arch_init_irq(void)
284 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
285 STATUSF_IP1 | STATUSF_IP0;
287 /* Default everything to IP2 */
288 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
289 __raw_writeq(IMR_IP2_VAL,
290 IOADDR(A_IMR_REGISTER(0,
291 R_IMR_INTERRUPT_MAP_BASE) +
293 __raw_writeq(IMR_IP2_VAL,
294 IOADDR(A_IMR_REGISTER(1,
295 R_IMR_INTERRUPT_MAP_BASE) +
302 * Map the high 16 bits of the mailbox registers to IP[3], for
306 __raw_writeq(IMR_IP3_VAL,
307 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
308 (K_INT_MBOX_0 << 3)));
309 __raw_writeq(IMR_IP3_VAL,
310 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
311 (K_INT_MBOX_0 << 3)));
313 /* Clear the mailboxes. The firmware may leave them dirty */
314 __raw_writeq(0xffffffffffffffffULL,
315 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
316 __raw_writeq(0xffffffffffffffffULL,
317 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
319 /* Mask everything except the mailbox registers for both cpus */
320 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
321 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
322 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
325 * Note that the timer interrupts are also mapped, but this is
326 * done in sb1250_time_init(). Also, the profiling driver
327 * does its own management of IP7.
331 imask |= STATUSF_IP6;
333 /* Enable necessary IPs, disable the rest */
334 change_c0_status(ST0_IM, imask);
338 kgdb_irq = K_INT_UART_0 + kgdb_port;
340 #ifdef CONFIG_SERIAL_SB1250_DUART
341 sb1250_duart_present[kgdb_port] = 0;
343 /* Setup uart 1 settings, mapper */
344 __raw_writeq(M_DUART_IMR_BRK,
345 IOADDR(A_DUART_IMRREG(kgdb_port)));
347 __raw_writeq(IMR_IP6_VAL,
348 IOADDR(A_IMR_REGISTER(0,
349 R_IMR_INTERRUPT_MAP_BASE) +
351 sb1250_unmask_irq(0, kgdb_irq);
358 #include <linux/delay.h>
360 #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
361 #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
363 static void sb1250_kgdb_interrupt(void)
366 * Clear break-change status (allow some time for the remote
367 * host to stop the break, since we would see another
368 * interrupt on the end-of-break too)
370 kstat_this_cpu.irqs[kgdb_irq]++;
372 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
373 M_DUART_RX_EN | M_DUART_TX_EN);
374 set_async_breakpoint(&get_irq_regs()->cp0_epc);
377 #endif /* CONFIG_KGDB */
379 extern void sb1250_mailbox_interrupt(void);
381 static inline void dispatch_ip2(void)
383 unsigned int cpu = smp_processor_id();
384 unsigned long long mask;
387 * Default...we've hit an IP[2] interrupt, which means we've got to
388 * check the 1250 interrupt registers to figure out what to do. Need
389 * to detect which CPU we're on, now that smp_affinity is supported.
391 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
392 R_IMR_INTERRUPT_STATUS_BASE)));
394 do_IRQ(fls64(mask) - 1);
397 asmlinkage void plat_irq_dispatch(void)
399 unsigned int cpu = smp_processor_id();
400 unsigned int pending;
403 * What a pain. We have to be really careful saving the upper 32 bits
404 * of any * register across function calls if we don't want them
405 * trashed--since were running in -o32, the calling routing never saves
406 * the full 64 bits of a register across a function call. Being the
407 * interrupt handler, we're guaranteed that interrupts are disabled
408 * during this code so we don't have to worry about random interrupts
409 * blasting the high 32 bits.
412 pending = read_c0_cause() & read_c0_status() & ST0_IM;
414 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
415 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
416 else if (pending & CAUSEF_IP4)
417 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
420 else if (pending & CAUSEF_IP3)
421 sb1250_mailbox_interrupt();
425 else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
426 sb1250_kgdb_interrupt();
429 else if (pending & CAUSEF_IP2)
432 spurious_interrupt();