arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c

   1 /*
   2  * Toshiba rbtx4927 specific setup
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * Copyright (C) 2000 RidgeRun, Inc.
  11  * Author: RidgeRun, Inc.
  12  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  13  *
  14  * Copyright 2001 MontaVista Software Inc.
  15  * Author: jsun@mvista.com or jsun@junsun.net
  16  *
  17  * Copyright 2002 MontaVista Software Inc.
  18  * Author: Michael Pruznick, michael_pruznick@mvista.com
  19  *
  20  * Copyright (C) 2000-2001 Toshiba Corporation
  21  *
  22  * Copyright (C) 2004 MontaVista Software Inc.
  23  * Author: Manish Lachwani, mlachwani@mvista.com
  24  *
  25  *  This program is free software; you can redistribute it and/or modify it
  26  *  under the terms of the GNU General Public License as published by the
  27  *  Free Software Foundation; either version 2 of the License, or (at your
  28  *  option) any later version.
  29  *
  30  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  31  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  32  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  33  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  34  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  36  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  38  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  39  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *  You should have received a copy of the GNU General Public License along
  42  *  with this program; if not, write to the Free Software Foundation, Inc.,
  43  *  675 Mass Ave, Cambridge, MA 02139, USA.
  44  */
  45 #include <linux/config.h>
  46 #include <linux/init.h>
  47 #include <linux/kernel.h>
  48 #include <linux/types.h>
  49 #include <linux/mm.h>
  50 #include <linux/swap.h>
  51 #include <linux/ioport.h>
  52 #include <linux/sched.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/pci.h>
  55 #include <linux/timex.h>
  56 #include <asm/bootinfo.h>
  57 #include <asm/page.h>
  58 #include <asm/io.h>
  59 #include <asm/irq.h>
  60 #include <asm/processor.h>
  61 #include <asm/ptrace.h>
  62 #include <asm/reboot.h>
  63 #include <asm/time.h>
  64 #include <linux/bootmem.h>
  65 #include <linux/blkdev.h>
  66 #ifdef CONFIG_RTC_DS1742
  67 #include <linux/ds1742rtc.h>
  68 #endif
  69 #ifdef CONFIG_TOSHIBA_FPCIB0
  70 #include <asm/tx4927/smsc_fdc37m81x.h>
  71 #endif
  72 #include <asm/tx4927/toshiba_rbtx4927.h>
  73 #ifdef CONFIG_PCI
  74 #include <asm/tx4927/tx4927_pci.h>
  75 #endif
  76 #ifdef CONFIG_BLK_DEV_IDEPCI
  77 #include <linux/hdreg.h>
  78 #include <linux/ide.h>
  79 #endif
  80 #ifdef CONFIG_SERIAL_TXX9
  81 #include <linux/tty.h>
  82 #include <linux/serial.h>
  83 #include <linux/serial_core.h>
  84 #endif
  85
  86 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
  87
  88 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  89 #define TOSHIBA_RBTX4927_SETUP_NONE        0x00000000
  90
  91 #define TOSHIBA_RBTX4927_SETUP_INFO        ( 1 <<  0 )
  92 #define TOSHIBA_RBTX4927_SETUP_WARN        ( 1 <<  1 )
  93 #define TOSHIBA_RBTX4927_SETUP_EROR        ( 1 <<  2 )
  94
  95 #define TOSHIBA_RBTX4927_SETUP_EFWFU       ( 1 <<  3 )
  96 #define TOSHIBA_RBTX4927_SETUP_SETUP       ( 1 <<  4 )
  97 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT   ( 1 <<  5 )
  98 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 <<  6 )
  99 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS     ( 1 <<  7 )
 100 #define TOSHIBA_RBTX4927_SETUP_PCI1        ( 1 <<  8 )
 101 #define TOSHIBA_RBTX4927_SETUP_PCI2        ( 1 <<  9 )
 102 #define TOSHIBA_RBTX4927_SETUP_PCI66       ( 1 << 10 )
 103
 104 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 105 #endif
 106
 107 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 108 static const u32 toshiba_rbtx4927_setup_debug_flag =
 109     (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
 110      TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
 111      TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
 112      TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
 113      | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
 114      TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
 115 #endif
 116
 117 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 118 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
 119         if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
 120         { \
 121            char tmp[100]; \
 122            sprintf( tmp, str ); \
 123            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 124         }
 125 #else
 126 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
 127 #endif
 128
 129 /* These functions are used for rebooting or halting the machine*/
 130 extern void toshiba_rbtx4927_restart(char *command);
 131 extern void toshiba_rbtx4927_halt(void);
 132 extern void toshiba_rbtx4927_power_off(void);
 133
 134 int tx4927_using_backplane = 0;
 135
 136 extern void gt64120_time_init(void);
 137 extern void toshiba_rbtx4927_irq_setup(void);
 138
 139 #ifdef CONFIG_PCI
 140 #define CONFIG_TX4927BUG_WORKAROUND
 141 #undef TX4927_SUPPORT_COMMAND_IO
 142 #undef  TX4927_SUPPORT_PCI_66
 143 int tx4927_cpu_clock = 100000000;       /* 100MHz */
 144 unsigned long mips_pci_io_base;
 145 unsigned long mips_pci_io_size;
 146 unsigned long mips_pci_mem_base;
 147 unsigned long mips_pci_mem_size;
 148 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 149 unsigned long mips_pci_io_pciaddr = 0;
 150 unsigned long mips_memory_upper;
 151 static int tx4927_ccfg_toeon = 1;
 152 static int tx4927_pcic_trdyto = 0;      /* default: disabled */
 153 unsigned long tx4927_ce_base[8];
 154 void tx4927_pci_setup(void);
 155 void tx4927_reset_pci_pcic(void);
 156 int tx4927_pci66 = 0;           /* 0:auto */
 157 #endif
 158
 159 char *toshiba_name = "";
 160
 161 #ifdef CONFIG_PCI
 162 static void tx4927_pcierr_interrupt(int irq, void *dev_id,
 163                                     struct pt_regs *regs)
 164 {
 165 #ifdef CONFIG_BLK_DEV_IDEPCI
 166         /* ignore MasterAbort for ide probing... */
 167         if (irq == TX4927_IRQ_IRC_PCIERR &&
 168             ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
 169             PCI_STATUS_REC_MASTER_ABORT) {
 170                 tx4927_pcicptr->pcistatus =
 171                     (tx4927_pcicptr->
 172                      pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
 173                                                 << 16);
 174
 175                 return;
 176         }
 177 #endif
 178         printk("PCI error interrupt (irq 0x%x).\n", irq);
 179
 180         printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
 181                (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
 182                tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
 183         printk("ccfg:%08lx, tear:%02lx_%08lx\n",
 184                (unsigned long) tx4927_ccfgptr->ccfg,
 185                (unsigned long) (tx4927_ccfgptr->tear >> 32),
 186                (unsigned long) tx4927_ccfgptr->tear);
 187         show_regs(regs);
 188 }
 189
 190 void __init toshiba_rbtx4927_pci_irq_init(void)
 191 {
 192         return;
 193 }
 194
 195 void tx4927_reset_pci_pcic(void)
 196 {
 197         /* Reset PCI Bus */
 198         *tx4927_pcireset_ptr = 1;
 199         /* Reset PCIC */
 200         tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
 201         udelay(10000);
 202         /* clear PCIC reset */
 203         tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
 204         *tx4927_pcireset_ptr = 0;
 205 }
 206 #endif /* CONFIG_PCI */
 207
 208 #ifdef CONFIG_PCI
 209 void print_pci_status(void)
 210 {
 211         printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
 212         printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
 213 }
 214
 215 extern struct pci_controller tx4927_controller;
 216
 217 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
 218                                     int top_bus, int busnr, int devfn)
 219 {
 220         static struct pci_dev dev;
 221         static struct pci_bus bus;
 222
 223         dev.sysdata = (void *)hose;
 224         dev.devfn = devfn;
 225         bus.number = busnr;
 226         bus.ops = hose->pci_ops;
 227         bus.parent = NULL;
 228         dev.bus = &bus;
 229
 230         return &dev;
 231 }
 232
 233 #define EARLY_PCI_OP(rw, size, type)                                    \
 234 static int early_##rw##_config_##size(struct pci_controller *hose,      \
 235         int top_bus, int bus, int devfn, int offset, type value)        \
 236 {                                                                       \
 237         return pci_##rw##_config_##size(                                \
 238                 fake_pci_dev(hose, top_bus, bus, devfn),                \
 239                 offset, value);                                         \
 240 }
 241
 242 EARLY_PCI_OP(read, byte, u8 *)
 243 EARLY_PCI_OP(read, word, u16 *)
 244 EARLY_PCI_OP(read, dword, u32 *)
 245 EARLY_PCI_OP(write, byte, u8)
 246 EARLY_PCI_OP(write, word, u16)
 247 EARLY_PCI_OP(write, dword, u32)
 248
 249 static int __init tx4927_pcibios_init(void)
 250 {
 251         unsigned int id;
 252         u32 pci_devfn;
 253         int devfn_start = 0;
 254         int devfn_stop = 0xff;
 255         int busno = 0; /* One bus on the Toshiba */
 256         struct pci_controller *hose = &tx4927_controller;
 257
 258         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 259                                        "-\n");
 260
 261         for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
 262                 early_read_config_dword(hose, busno, busno, pci_devfn,
 263                                         PCI_VENDOR_ID, &id);
 264
 265                 if (id == 0xffffffff) {
 266                         continue;
 267                 }
 268
 269                 if (id == 0x94601055) {
 270                         u8 v08_64;
 271                         u32 v32_b0;
 272                         u8 v08_e1;
 273                         char *s = " sb/isa --";
 274
 275                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 276                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 277                              s);
 278
 279                         early_read_config_byte(hose, busno, busno,
 280                                                pci_devfn, 0x64, &v08_64);
 281                         early_read_config_dword(hose, busno, busno,
 282                                                 pci_devfn, 0xb0, &v32_b0);
 283                         early_read_config_byte(hose, busno, busno,
 284                                                pci_devfn, 0xe1, &v08_e1);
 285
 286                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 287                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 288                              ":%s beg 0x64 = 0x%02x\n", s, v08_64);
 289                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 290                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 291                              ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
 292                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 293                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 294                              ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
 295
 296                         /* serial irq control */
 297                         v08_64 = 0xd0;
 298
 299                         /* serial irq pin */
 300                         v32_b0 |= 0x00010000;
 301
 302                         /* ide irq on isa14 */
 303                         v08_e1 &= 0xf0;
 304                         v08_e1 |= 0x0d;
 305
 306                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 307                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 308                              ":%s mid 0x64 = 0x%02x\n", s, v08_64);
 309                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 310                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 311                              ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
 312                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 313                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 314                              ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
 315
 316                         early_write_config_byte(hose, busno, busno,
 317                                                 pci_devfn, 0x64, v08_64);
 318                         early_write_config_dword(hose, busno, busno,
 319                                                  pci_devfn, 0xb0, v32_b0);
 320                         early_write_config_byte(hose, busno, busno,
 321                                                 pci_devfn, 0xe1, v08_e1);
 322
 323 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 324                         {
 325                                 early_read_config_byte(hose, busno, busno,
 326                                                        pci_devfn, 0x64,
 327                                                        &v08_64);
 328                                 early_read_config_dword(hose, busno, busno,
 329                                                         pci_devfn, 0xb0,
 330                                                         &v32_b0);
 331                                 early_read_config_byte(hose, busno, busno,
 332                                                        pci_devfn, 0xe1,
 333                                                        &v08_e1);
 334
 335                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 336                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 337                                      ":%s end 0x64 = 0x%02x\n", s, v08_64);
 338                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 339                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 340                                      ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
 341                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 342                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 343                                      ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
 344                         }
 345 #endif
 346
 347                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 348                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 349                              s);
 350                 }
 351
 352                 if (id == 0x91301055) {
 353                         u8 v08_04;
 354                         u8 v08_09;
 355                         u8 v08_41;
 356                         u8 v08_43;
 357                         u8 v08_5c;
 358                         char *s = " sb/ide --";
 359
 360                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 361                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 362                              s);
 363
 364                         early_read_config_byte(hose, busno, busno,
 365                                                pci_devfn, 0x04, &v08_04);
 366                         early_read_config_byte(hose, busno, busno,
 367                                                pci_devfn, 0x09, &v08_09);
 368                         early_read_config_byte(hose, busno, busno,
 369                                                pci_devfn, 0x41, &v08_41);
 370                         early_read_config_byte(hose, busno, busno,
 371                                                pci_devfn, 0x43, &v08_43);
 372                         early_read_config_byte(hose, busno, busno,
 373                                                pci_devfn, 0x5c, &v08_5c);
 374
 375                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 376                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 377                              ":%s beg 0x04 = 0x%02x\n", s, v08_04);
 378                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 379                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 380                              ":%s beg 0x09 = 0x%02x\n", s, v08_09);
 381                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 382                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 383                              ":%s beg 0x41 = 0x%02x\n", s, v08_41);
 384                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 385                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 386                              ":%s beg 0x43 = 0x%02x\n", s, v08_43);
 387                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 388                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 389                              ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
 390
 391                         /* enable ide master/io */
 392                         v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 393
 394                         /* enable ide native mode */
 395                         v08_09 |= 0x05;
 396
 397                         /* enable primary ide */
 398                         v08_41 |= 0x80;
 399
 400                         /* enable secondary ide */
 401                         v08_43 |= 0x80;
 402
 403                         /*
 404                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 405                          *
 406                          * This line of code is intended to provide the user with a work
 407                          * around solution to the anomalies cited in SMSC's anomaly sheet
 408                          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 409                          *
 410                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 411                          */
 412                         v08_5c |= 0x01;
 413
 414                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 415                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 416                              ":%s mid 0x04 = 0x%02x\n", s, v08_04);
 417                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 418                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 419                              ":%s mid 0x09 = 0x%02x\n", s, v08_09);
 420                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 421                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 422                              ":%s mid 0x41 = 0x%02x\n", s, v08_41);
 423                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 424                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 425                              ":%s mid 0x43 = 0x%02x\n", s, v08_43);
 426                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 427                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 428                              ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
 429
 430                         early_write_config_byte(hose, busno, busno,
 431                                                 pci_devfn, 0x5c, v08_5c);
 432                         early_write_config_byte(hose, busno, busno,
 433                                                 pci_devfn, 0x04, v08_04);
 434                         early_write_config_byte(hose, busno, busno,
 435                                                 pci_devfn, 0x09, v08_09);
 436                         early_write_config_byte(hose, busno, busno,
 437                                                 pci_devfn, 0x41, v08_41);
 438                         early_write_config_byte(hose, busno, busno,
 439                                                 pci_devfn, 0x43, v08_43);
 440
 441 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 442                         {
 443                                 early_read_config_byte(hose, busno, busno,
 444                                                        pci_devfn, 0x04,
 445                                                        &v08_04);
 446                                 early_read_config_byte(hose, busno, busno,
 447                                                        pci_devfn, 0x09,
 448                                                        &v08_09);
 449                                 early_read_config_byte(hose, busno, busno,
 450                                                        pci_devfn, 0x41,
 451                                                        &v08_41);
 452                                 early_read_config_byte(hose, busno, busno,
 453                                                        pci_devfn, 0x43,
 454                                                        &v08_43);
 455                                 early_read_config_byte(hose, busno, busno,
 456                                                        pci_devfn, 0x5c,
 457                                                        &v08_5c);
 458
 459                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 460                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 461                                      ":%s end 0x04 = 0x%02x\n", s, v08_04);
 462                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 463                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 464                                      ":%s end 0x09 = 0x%02x\n", s, v08_09);
 465                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 466                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 467                                      ":%s end 0x41 = 0x%02x\n", s, v08_41);
 468                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 469                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 470                                      ":%s end 0x43 = 0x%02x\n", s, v08_43);
 471                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 472                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 473                                      ":%s end 0x5c = 0x%02x\n", s, v08_5c);
 474                         }
 475 #endif
 476
 477                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 478                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 479                              s);
 480                 }
 481
 482         }
 483
 484         register_pci_controller(&tx4927_controller);
 485         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 486                                        "+\n");
 487
 488         return 0;
 489 }
 490
 491 arch_initcall(tx4927_pcibios_init);
 492
 493 extern struct resource pci_io_resource;
 494 extern struct resource pci_mem_resource;
 495
 496 void tx4927_pci_setup(void)
 497 {
 498         static int called = 0;
 499         extern unsigned int tx4927_get_mem_size(void);
 500
 501         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
 502
 503         mips_memory_upper = tx4927_get_mem_size() << 20;
 504         mips_memory_upper += KSEG0;
 505         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 506                                        "0x%08lx=mips_memory_upper\n",
 507                                        mips_memory_upper);
 508         mips_pci_io_base = TX4927_PCIIO;
 509         mips_pci_io_size = TX4927_PCIIO_SIZE;
 510         mips_pci_mem_base = TX4927_PCIMEM;
 511         mips_pci_mem_size = TX4927_PCIMEM_SIZE;
 512
 513         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 514                                        "0x%08lx=mips_pci_io_base\n",
 515                                        mips_pci_io_base);
 516         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 517                                        "0x%08lx=mips_pci_io_size\n",
 518                                        mips_pci_io_size);
 519         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 520                                        "0x%08lx=mips_pci_mem_base\n",
 521                                        mips_pci_mem_base);
 522         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 523                                        "0x%08lx=mips_pci_mem_size\n",
 524                                        mips_pci_mem_size);
 525         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 526                                        "0x%08lx=pci_io_resource.start\n",
 527                                        pci_io_resource.start);
 528         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 529                                        "0x%08lx=pci_io_resource.end\n",
 530                                        pci_io_resource.end);
 531         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 532                                        "0x%08lx=pci_mem_resource.start\n",
 533                                        pci_mem_resource.start);
 534         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 535                                        "0x%08lx=pci_mem_resource.end\n",
 536                                        pci_mem_resource.end);
 537         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 538                                        "0x%08lx=mips_io_port_base",
 539                                        mips_io_port_base);
 540
 541         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 542                                        "setup pci_io_resource  to 0x%08lx 0x%08lx\n",
 543                                        pci_io_resource.start,
 544                                        pci_io_resource.end);
 545         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 546                                        "setup pci_mem_resource to 0x%08lx 0x%08lx\n",
 547                                        pci_mem_resource.start,
 548                                        pci_mem_resource.end);
 549
 550         if (!called) {
 551                 printk
 552                     ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
 553                      (unsigned short) (tx4927_pcicptr->pciid >> 16),
 554                      (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
 555                      (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
 556                      (!(tx4927_ccfgptr->
 557                         ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
 558                      "Internal");
 559                 called = 1;
 560         }
 561         printk("%s PCIC --%s PCICLK:",toshiba_name,
 562                (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
 563         if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
 564                 int pciclk = 0;
 565                 switch ((unsigned long) tx4927_ccfgptr->
 566                         ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 567                 case TX4927_CCFG_PCIDIVMODE_2_5:
 568                         pciclk = tx4927_cpu_clock * 2 / 5;
 569                         break;
 570                 case TX4927_CCFG_PCIDIVMODE_3:
 571                         pciclk = tx4927_cpu_clock / 3;
 572                         break;
 573                 case TX4927_CCFG_PCIDIVMODE_5:
 574                         pciclk = tx4927_cpu_clock / 5;
 575                         break;
 576                 case TX4927_CCFG_PCIDIVMODE_6:
 577                         pciclk = tx4927_cpu_clock / 6;
 578                         break;
 579                 }
 580                 printk("Internal(%dMHz)", pciclk / 1000000);
 581         } else {
 582                 int pciclk = 0;
 583                 int pciclk_setting = *tx4927_pci_clk_ptr;
 584                 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
 585                 case TX4927_PCI_CLK_33:
 586                         pciclk = 33333333;
 587                         break;
 588                 case TX4927_PCI_CLK_25:
 589                         pciclk = 25000000;
 590                         break;
 591                 case TX4927_PCI_CLK_66:
 592                         pciclk = 66666666;
 593                         break;
 594                 case TX4927_PCI_CLK_50:
 595                         pciclk = 50000000;
 596                         break;
 597                 }
 598                 printk("External(%dMHz)", pciclk / 1000000);
 599         }
 600         printk("\n");
 601
 602
 603
 604         /* GB->PCI mappings */
 605         tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
 606         tx4927_pcicptr->g2piogbase = mips_pci_io_base |
 607 #ifdef __BIG_ENDIAN
 608             TX4927_PCIC_G2PIOGBASE_ECHG
 609 #else
 610             TX4927_PCIC_G2PIOGBASE_BSDIS
 611 #endif
 612             ;
 613
 614         tx4927_pcicptr->g2piopbase = 0;
 615
 616         tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
 617         tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
 618 #ifdef __BIG_ENDIAN
 619             TX4927_PCIC_G2PMnGBASE_ECHG
 620 #else
 621             TX4927_PCIC_G2PMnGBASE_BSDIS
 622 #endif
 623             ;
 624         tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
 625
 626         tx4927_pcicptr->g2pmmask[1] = 0;
 627         tx4927_pcicptr->g2pmgbase[1] = 0;
 628         tx4927_pcicptr->g2pmpbase[1] = 0;
 629         tx4927_pcicptr->g2pmmask[2] = 0;
 630         tx4927_pcicptr->g2pmgbase[2] = 0;
 631         tx4927_pcicptr->g2pmpbase[2] = 0;
 632
 633
 634         /* PCI->GB mappings (I/O 256B) */
 635         tx4927_pcicptr->p2giopbase = 0; /* 256B */
 636
 637         /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
 638         tx4927_pcicptr->p2gm0plbase = 0;
 639         tx4927_pcicptr->p2gm0pubase = 0;
 640         tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
 641 #ifdef __BIG_ENDIAN
 642             TX4927_PCIC_P2GMnGBASE_TECHG
 643 #else
 644             TX4927_PCIC_P2GMnGBASE_TBSDIS
 645 #endif
 646             ;
 647
 648         /* PCI->GB mappings (MEM 16MB) -not used */
 649         tx4927_pcicptr->p2gm1plbase = 0xffffffff;
 650 #ifdef CONFIG_TX4927BUG_WORKAROUND
 651         /*
 652          * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
 653          * if P2GM0PUBASE was 0.
 654          */
 655         tx4927_pcicptr->p2gm1pubase = 0;
 656 #else
 657         tx4927_pcicptr->p2gm1pubase = 0xffffffff;
 658 #endif
 659         tx4927_pcicptr->p2gmgbase[1] = 0;
 660
 661         /* PCI->GB mappings (MEM 1MB) -not used */
 662         tx4927_pcicptr->p2gm2pbase = 0xffffffff;
 663         tx4927_pcicptr->p2gmgbase[2] = 0;
 664
 665
 666         /* Enable Initiator Memory 0 Space, I/O Space, Config */
 667         tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
 668         tx4927_pcicptr->pciccfg |=
 669             TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
 670             TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
 671
 672
 673         /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
 674         tx4927_pcicptr->pcicfg1 = 0;
 675
 676         if (tx4927_pcic_trdyto >= 0) {
 677                 tx4927_pcicptr->g2ptocnt &= ~0xff;
 678                 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
 679         }
 680
 681         /* Clear All Local Bus Status */
 682         tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
 683         /* Enable All Local Bus Interrupts */
 684         tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
 685         /* Clear All Initiator Status */
 686         tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
 687         /* Enable All Initiator Interrupts */
 688         tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
 689         /* Clear All PCI Status Error */
 690         tx4927_pcicptr->pcistatus =
 691             (tx4927_pcicptr->pcistatus & 0x0000ffff) |
 692             (TX4927_PCIC_PCISTATUS_ALL << 16);
 693         /* Enable All PCI Status Error Interrupts */
 694         tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
 695
 696         /* PCIC Int => IRC IRQ16 */
 697         tx4927_pcicptr->pcicfg2 =
 698             (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
 699
 700         if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
 701                 /* XXX */
 702         } else {
 703                 /* Reset Bus Arbiter */
 704                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
 705                 /* Enable Bus Arbiter */
 706                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
 707         }
 708
 709         tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
 710             PCI_COMMAND_MEMORY |
 711             PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 712
 713         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 714                                        ":pci setup complete:\n");
 715         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
 716 }
 717
 718 #endif /* CONFIG_PCI */
 719
 720 void toshiba_rbtx4927_restart(char *command)
 721 {
 722         printk(KERN_NOTICE "System Rebooting...\n");
 723
 724         /* enable the s/w reset register */
 725         reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
 726
 727         /* wait for enable to be seen */
 728         while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
 729                 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
 730
 731         /* do a s/w reset */
 732         reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
 733
 734         /* do something passive while waiting for reset */
 735         local_irq_disable();
 736         while (1)
 737                 asm_wait();
 738
 739         /* no return */
 740 }
 741
 742
 743 void toshiba_rbtx4927_halt(void)
 744 {
 745         printk(KERN_NOTICE "System Halted\n");
 746         local_irq_disable();
 747         while (1) {
 748                 asm_wait();
 749         }
 750         /* no return */
 751 }
 752
 753 void toshiba_rbtx4927_power_off(void)
 754 {
 755         toshiba_rbtx4927_halt();
 756         /* no return */
 757 }
 758
 759 void __init toshiba_rbtx4927_setup(void)
 760 {
 761         vu32 cp0_config;
 762         char *argptr;
 763
 764         printk("CPU is %s\n", toshiba_name);
 765
 766         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 767                                        "-\n");
 768
 769         /* f/w leaves this on at startup */
 770         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 771                                        ":Clearing STO_ERL.\n");
 772         clear_c0_status(ST0_ERL);
 773
 774         /* enable caches -- HCP5 does this, pmon does not */
 775         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 776                                        ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
 777         cp0_config = read_c0_config();
 778         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
 779         write_c0_config(cp0_config);
 780
 781 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 782         {
 783                 extern void dump_cp0(char *);
 784                 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
 785         }
 786 #endif
 787
 788         /* setup irq stuff */
 789         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 790                                        ":Setting up tx4927 pic.\n");
 791         TX4927_WR(0xff1ff604, 0x00000400);      /* irq trigger */
 792         TX4927_WR(0xff1ff608, 0x00000000);      /* irq trigger */
 793
 794         /* setup serial stuff */
 795         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 796                                        ":Setting up tx4927 sio.\n");
 797         TX4927_WR(0xff1ff314, 0x00000000);      /* h/w flow control off */
 798         TX4927_WR(0xff1ff414, 0x00000000);      /* h/w flow control off */
 799
 800         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 801                                        "+\n");
 802
 803         set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
 804         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 805                                        ":mips_io_port_base=0x%08lx\n",
 806                                        mips_io_port_base);
 807
 808         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 809                                        ":Resource\n");
 810         ioport_resource.end = 0xffffffff;
 811         iomem_resource.end = 0xffffffff;
 812
 813         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 814                                        ":ResetRoutines\n");
 815         _machine_restart = toshiba_rbtx4927_restart;
 816         _machine_halt = toshiba_rbtx4927_halt;
 817         _machine_power_off = toshiba_rbtx4927_power_off;
 818
 819 #ifdef CONFIG_PCI
 820
 821         /* PCIC */
 822         /*
 823            * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
 824            * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1).
 825            * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
 826            * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
 827            * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
 828            * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
 829            * i.e. S9[3]: ON (83MHz), OFF (100MHz)
 830          */
 831         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 832                                        "ccfg is %lx, DIV is %x\n",
 833                                        (unsigned long) tx4927_ccfgptr->
 834                                        ccfg, TX4927_CCFG_PCIDIVMODE_MASK);
 835
 836         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 837                                        "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
 838                                        (unsigned long) tx4927_ccfgptr->
 839                                        ccfg & TX4927_CCFG_PCI66,
 840                                        (unsigned long) tx4927_ccfgptr->
 841                                        ccfg & TX4927_CCFG_PCIMIDE,
 842                                        (unsigned long) tx4927_ccfgptr->
 843                                        ccfg & TX4927_CCFG_PCIXARB);
 844
 845         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 846                                        "PCIDIVMODE is %lx\n",
 847                                        (unsigned long) tx4927_ccfgptr->
 848                                        ccfg & TX4927_CCFG_PCIDIVMODE_MASK);
 849
 850         switch ((unsigned long) tx4927_ccfgptr->
 851                 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 852         case TX4927_CCFG_PCIDIVMODE_2_5:
 853         case TX4927_CCFG_PCIDIVMODE_5:
 854                 tx4927_cpu_clock = 166000000;   /* 166MHz */
 855                 break;
 856         default:
 857                 tx4927_cpu_clock = 200000000;   /* 200MHz */
 858         }
 859
 860         /* CCFG */
 861         /* enable Timeout BusError */
 862         if (tx4927_ccfg_toeon)
 863                 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
 864
 865         /* SDRAMC fixup */
 866 #ifdef CONFIG_TX4927BUG_WORKAROUND
 867         /*
 868          * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
 869          * G-bus timeout error detection is incorrect
 870          */
 871         if (tx4927_ccfg_toeon)
 872                 tx4927_sdramcptr->tr |= 0x02000000;     /* RCD:3tck */
 873 #endif
 874
 875         tx4927_pci_setup();
 876         if (tx4927_using_backplane == 1)
 877                 printk("backplane board IS installed\n");
 878         else
 879                 printk("No Backplane \n");
 880
 881         /* this is on ISA bus behind PCI bus, so need PCI up first */
 882 #ifdef CONFIG_TOSHIBA_FPCIB0
 883         {
 884                 if (tx4927_using_backplane) {
 885                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 886                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 887                              ":fpcibo=yes\n");
 888
 889                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 890                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 891                              ":smsc_fdc37m81x_init()\n");
 892                         smsc_fdc37m81x_init(0x3f0);
 893
 894                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 895                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 896                              ":smsc_fdc37m81x_config_beg()\n");
 897                         smsc_fdc37m81x_config_beg();
 898
 899                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 900                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 901                              ":smsc_fdc37m81x_config_set(KBD)\n");
 902                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 903                                                   SMSC_FDC37M81X_KBD);
 904                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 905                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 906                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 907                                                   1);
 908
 909                         smsc_fdc37m81x_config_end();
 910                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 911                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 912                              ":smsc_fdc37m81x_config_end()\n");
 913                 } else {
 914                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 915                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 916                              ":fpcibo=not_found\n");
 917                 }
 918         }
 919 #else
 920         {
 921                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 922                     (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
 923         }
 924 #endif
 925
 926 #endif /* CONFIG_PCI */
 927
 928 #ifdef CONFIG_SERIAL_TXX9
 929         {
 930                 extern int early_serial_txx9_setup(struct uart_port *port);
 931                 int i;
 932                 struct uart_port req;
 933                 for(i = 0; i < 2; i++) {
 934                         memset(&req, 0, sizeof(req));
 935                         req.line = i;
 936                         req.iotype = UPIO_MEM;
 937                         req.membase = (char *)(0xff1ff300 + i * 0x100);
 938                         req.mapbase = 0xff1ff300 + i * 0x100;
 939                         req.irq = 32 + i;
 940                         req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 941                         req.uartclk = 50000000;
 942                         early_serial_txx9_setup(&req);
 943                 }
 944         }
 945 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 946         argptr = prom_getcmdline();
 947         if (strstr(argptr, "console=") == NULL) {
 948                 strcat(argptr, " console=ttyS0,38400");
 949         }
 950 #endif
 951 #endif
 952
 953 #ifdef CONFIG_ROOT_NFS
 954         argptr = prom_getcmdline();
 955         if (strstr(argptr, "root=") == NULL) {
 956                 strcat(argptr, " root=/dev/nfs rw");
 957         }
 958 #endif
 959
 960
 961 #ifdef CONFIG_IP_PNP
 962         argptr = prom_getcmdline();
 963         if (strstr(argptr, "ip=") == NULL) {
 964                 strcat(argptr, " ip=any");
 965         }
 966 #endif
 967
 968
 969         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 970                                "+\n");
 971 }
 972
 973 #ifdef CONFIG_RTC_DS1742
 974 extern unsigned long rtc_ds1742_get_time(void);
 975 extern int rtc_ds1742_set_time(unsigned long);
 976 extern void rtc_ds1742_wait(void);
 977 #endif
 978
 979 void __init
 980 toshiba_rbtx4927_time_init(void)
 981 {
 982         u32 c1;
 983         u32 c2;
 984
 985         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
 986
 987 #ifdef CONFIG_RTC_DS1742
 988
 989         rtc_get_time = rtc_ds1742_get_time;
 990         rtc_set_time = rtc_ds1742_set_time;
 991
 992         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
 993                                        ":rtc_ds1742_init()-\n");
 994         rtc_ds1742_init(0xbc010000);
 995         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
 996                                        ":rtc_ds1742_init()+\n");
 997
 998         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
 999                                        ":Calibrate mips_hpt_frequency-\n");
1000         rtc_ds1742_wait();
1001
1002         /* get the count */
1003         c1 = read_c0_count();
1004
1005         /* wait for the seconds to change again */
1006         rtc_ds1742_wait();
1007
1008         /* get the count again */
1009         c2 = read_c0_count();
1010
1011         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1012                                        ":Calibrate mips_hpt_frequency+\n");
1013         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1014                                        ":c1=%12u\n", c1);
1015         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1016                                        ":c2=%12u\n", c2);
1017
1018         /* this diff is as close as we are going to get to counter ticks per sec */
1019         mips_hpt_frequency = abs(c2 - c1);
1020         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1021                                        ":f1=%12u\n", mips_hpt_frequency);
1022
1023         /* round to 1/10th of a MHz */
1024         mips_hpt_frequency /= (100 * 1000);
1025         mips_hpt_frequency *= (100 * 1000);
1026         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1027                                        ":f2=%12u\n", mips_hpt_frequency);
1028
1029         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
1030                                        ":mips_hpt_frequency=%uHz (%uMHz)\n",
1031                                        mips_hpt_frequency,
1032                                        mips_hpt_frequency / 1000000);
1033 #else
1034         mips_hpt_frequency = 100000000;
1035 #endif
1036
1037         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1038
1039 }
1040
1041 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1042 {
1043         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1044                                        "-\n");
1045         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1046                                        "+\n");
1047 }