2 * Toshiba rbtx4927 specific setup
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
20 * Copyright (C) 2000-2001 Toshiba Corporation
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/delay.h>
54 #include <asm/processor.h>
55 #include <asm/reboot.h>
56 #include <asm/txx9/generic.h>
57 #include <asm/txx9/pci.h>
58 #include <asm/txx9/rbtx4927.h>
59 #include <asm/txx9/tx4938.h> /* for TX4937 */
62 static void __init tx4927_pci_setup(void)
64 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
65 struct pci_controller *c = &txx9_primary_pcic;
67 register_pci_controller(c);
69 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
71 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
72 TXX9_PCI_OPT_CLK_66; /* already configured */
75 writeb(1, rbtx4927_pcireset_addr);
77 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
78 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
80 tx4927_pciclk66_setup();
82 /* clear PCIC reset */
83 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
84 writeb(0, rbtx4927_pcireset_addr);
87 tx4927_report_pciclk();
88 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
89 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
90 TXX9_PCI_OPT_CLK_AUTO &&
91 txx9_pci66_check(c, 0, 0)) {
93 writeb(1, rbtx4927_pcireset_addr);
95 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
96 tx4927_pciclk66_setup();
98 /* clear PCIC reset */
99 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
100 writeb(0, rbtx4927_pcireset_addr);
102 /* Reinitialize PCIC */
103 tx4927_report_pciclk();
104 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
108 static void __init tx4937_pci_setup(void)
110 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
111 struct pci_controller *c = &txx9_primary_pcic;
113 register_pci_controller(c);
115 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
117 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
118 TXX9_PCI_OPT_CLK_66; /* already configured */
121 writeb(1, rbtx4927_pcireset_addr);
123 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
124 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
126 tx4938_pciclk66_setup();
128 /* clear PCIC reset */
129 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
130 writeb(0, rbtx4927_pcireset_addr);
133 tx4938_report_pciclk();
134 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
135 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
136 TXX9_PCI_OPT_CLK_AUTO &&
137 txx9_pci66_check(c, 0, 0)) {
139 writeb(1, rbtx4927_pcireset_addr);
141 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
142 tx4938_pciclk66_setup();
144 /* clear PCIC reset */
145 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
146 writeb(0, rbtx4927_pcireset_addr);
148 /* Reinitialize PCIC */
149 tx4938_report_pciclk();
150 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
154 static void __init rbtx4927_arch_init(void)
159 static void __init rbtx4937_arch_init(void)
164 #define rbtx4927_arch_init NULL
165 #define rbtx4937_arch_init NULL
166 #endif /* CONFIG_PCI */
168 static void __noreturn wait_forever(void)
175 static void toshiba_rbtx4927_restart(char *command)
177 printk(KERN_NOTICE "System Rebooting...\n");
179 /* enable the s/w reset register */
180 writeb(1, rbtx4927_softresetlock_addr);
182 /* wait for enable to be seen */
183 while (!(readb(rbtx4927_softresetlock_addr) & 1))
187 writeb(1, rbtx4927_softreset_addr);
189 /* do something passive while waiting for reset */
195 static void toshiba_rbtx4927_halt(void)
197 printk(KERN_NOTICE "System Halted\n");
203 static void toshiba_rbtx4927_power_off(void)
205 toshiba_rbtx4927_halt();
209 static void __init rbtx4927_clock_init(void);
210 static void __init rbtx4937_clock_init(void);
212 static void __init rbtx4927_mem_setup(void)
217 /* f/w leaves this on at startup */
218 clear_c0_status(ST0_ERL);
220 /* enable caches -- HCP5 does this, pmon does not */
221 cp0_config = read_c0_config();
222 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
223 write_c0_config(cp0_config);
225 if (TX4927_REV_PCODE() == 0x4927) {
226 rbtx4927_clock_init();
229 rbtx4937_clock_init();
233 _machine_restart = toshiba_rbtx4927_restart;
234 _machine_halt = toshiba_rbtx4927_halt;
235 pm_power_off = toshiba_rbtx4927_power_off;
238 txx9_alloc_pci_controller(&txx9_primary_pcic,
239 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
240 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
242 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
245 tx4927_setup_serial();
246 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
247 argptr = prom_getcmdline();
248 if (strstr(argptr, "console=") == NULL) {
249 strcat(argptr, " console=ttyS0,38400");
253 #ifdef CONFIG_ROOT_NFS
254 argptr = prom_getcmdline();
255 if (strstr(argptr, "root=") == NULL) {
256 strcat(argptr, " root=/dev/nfs rw");
261 argptr = prom_getcmdline();
262 if (strstr(argptr, "ip=") == NULL) {
263 strcat(argptr, " ip=any");
268 static void __init rbtx4927_clock_init(void)
271 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
274 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
275 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
276 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
277 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
278 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
279 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
281 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
282 TX4927_CCFG_PCIDIVMODE_MASK) {
283 case TX4927_CCFG_PCIDIVMODE_2_5:
284 case TX4927_CCFG_PCIDIVMODE_5:
285 txx9_cpu_clock = 166666666; /* 166MHz */
288 txx9_cpu_clock = 200000000; /* 200MHz */
292 static void __init rbtx4937_clock_init(void)
295 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
298 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
299 * PCIDIVMODE[10] is 0.
300 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
301 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
302 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
303 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
304 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
305 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
307 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
308 TX4938_CCFG_PCIDIVMODE_MASK) {
309 case TX4938_CCFG_PCIDIVMODE_8:
310 case TX4938_CCFG_PCIDIVMODE_4:
311 txx9_cpu_clock = 266666666; /* 266MHz */
313 case TX4938_CCFG_PCIDIVMODE_9:
314 case TX4938_CCFG_PCIDIVMODE_4_5:
315 txx9_cpu_clock = 300000000; /* 300MHz */
318 txx9_cpu_clock = 333333333; /* 333MHz */
322 static void __init rbtx4927_time_init(void)
327 static int __init toshiba_rbtx4927_rtc_init(void)
329 struct resource res = {
330 .start = RBTX4927_BRAMRTC_BASE - IO_BASE,
331 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
332 .flags = IORESOURCE_MEM,
334 struct platform_device *dev =
335 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
336 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
339 static int __init rbtx4927_ne_init(void)
341 struct resource res[] = {
343 .start = RBTX4927_RTL_8019_BASE,
344 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
345 .flags = IORESOURCE_IO,
347 .start = RBTX4927_RTL_8019_IRQ,
348 .flags = IORESOURCE_IRQ,
351 struct platform_device *dev =
352 platform_device_register_simple("ne", -1,
353 res, ARRAY_SIZE(res));
354 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
357 /* Watchdog support */
359 static int __init txx9_wdt_init(unsigned long base)
361 struct resource res = {
363 .end = base + 0x100 - 1,
364 .flags = IORESOURCE_MEM,
366 struct platform_device *dev =
367 platform_device_register_simple("txx9wdt", -1, &res, 1);
368 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
371 static int __init rbtx4927_wdt_init(void)
373 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
376 static void __init rbtx4927_device_init(void)
378 toshiba_rbtx4927_rtc_init();
383 struct txx9_board_vec rbtx4927_vec __initdata = {
384 .system = "Toshiba RBTX4927",
385 .prom_init = rbtx4927_prom_init,
386 .mem_setup = rbtx4927_mem_setup,
387 .irq_setup = rbtx4927_irq_setup,
388 .time_init = rbtx4927_time_init,
389 .device_init = rbtx4927_device_init,
390 .arch_init = rbtx4927_arch_init,
392 .pci_map_irq = rbtx4927_pci_map_irq,
395 struct txx9_board_vec rbtx4937_vec __initdata = {
396 .system = "Toshiba RBTX4937",
397 .prom_init = rbtx4927_prom_init,
398 .mem_setup = rbtx4927_mem_setup,
399 .irq_setup = rbtx4927_irq_setup,
400 .time_init = rbtx4927_time_init,
401 .device_init = rbtx4927_device_init,
402 .arch_init = rbtx4937_arch_init,
404 .pci_map_irq = rbtx4927_pci_map_irq,