1 /* MN10300 Misalignment fixup handler
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/timer.h>
19 #include <linux/smp.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <asm/processor.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
29 #include <linux/atomic.h>
31 #include <asm/pgalloc.h>
32 #include <asm/cpu-regs.h>
33 #include <asm/busctl-regs.h>
35 #include <asm/gdb-stub.h>
36 #include <asm/asm-offsets.h>
39 #define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
41 #define kdebug(FMT, ...) do {} while (0)
44 static int misalignment_addr(unsigned long *registers, unsigned long sp,
45 unsigned params, unsigned opcode,
47 void **_address, unsigned long **_postinc,
50 static int misalignment_reg(unsigned long *registers, unsigned params,
51 unsigned opcode, unsigned long disp,
52 unsigned long **_register);
54 static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
56 static const unsigned Dreg_index[] = {
57 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
60 static const unsigned Areg_index[] = {
61 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
64 static const unsigned Rreg_index[] = {
65 REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
66 REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
67 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
68 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
88 u_int8_t opsz, dispsz;
96 [FMT_D2] = { 16, 16 },
97 [FMT_D4] = { 16, 32 },
100 [FMT_D8] = { 24, 24 },
101 [FMT_D9] = { 24, 32 },
102 [FMT_D10] = { 32, 0 },
106 DM0, /* data reg in opcode in bits 0-1 */
107 DM1, /* data reg in opcode in bits 2-3 */
108 DM2, /* data reg in opcode in bits 4-5 */
109 AM0, /* addr reg in opcode in bits 0-1 */
110 AM1, /* addr reg in opcode in bits 2-3 */
111 AM2, /* addr reg in opcode in bits 4-5 */
112 RM0, /* reg in opcode in bits 0-3 */
113 RM1, /* reg in opcode in bits 2-5 */
114 RM2, /* reg in opcode in bits 4-7 */
115 RM4, /* reg in opcode in bits 8-11 */
116 RM6, /* reg in opcode in bits 12-15 */
118 RD0, /* reg in displacement in bits 0-3 */
119 RD2, /* reg in displacement in bits 4-7 */
121 SP, /* stack pointer */
123 SD8, /* 8-bit signed displacement */
124 SD16, /* 16-bit signed displacement */
125 SD24, /* 24-bit signed displacement */
126 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
127 SIMM8, /* 8-bit signed immediate */
128 IMM8, /* 8-bit unsigned immediate */
129 IMM16, /* 16-bit unsigned immediate */
130 IMM24, /* 24-bit unsigned immediate */
131 IMM32, /* 32-bit unsigned immediate */
132 IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */
134 IMM32_MEM, /* 32-bit unsigned displacement */
135 IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */
153 struct mn10300_opcode {
159 enum format_id format;
165 #define MEM(ADDR) (0x80000000 | (ADDR))
166 #define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2))
167 #define MEMINC(ADDR) (0x81000000 | (ADDR))
168 #define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC))
171 /* LIBOPCODES EXCERPT
172 Assemble Matsushita MN10300 instructions.
173 Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
175 This program is free software; you can redistribute it and/or modify
176 it under the terms of the GNU General Public Licence as published by
177 the Free Software Foundation; either version 2 of the Licence, or
178 (at your option) any later version.
180 This program is distributed in the hope that it will be useful,
181 but WITHOUT ANY WARRANTY; without even the implied warranty of
182 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
183 GNU General Public Licence for more details.
185 You should have received a copy of the GNU General Public Licence
186 along with this program; if not, write to the Free Software
187 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
189 static const struct mn10300_opcode mn10300_opcodes[] = {
190 { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
191 { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
192 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
193 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
194 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
195 { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
196 { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
197 { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
198 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
199 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
200 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
201 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
202 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
203 { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
204 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
205 { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
206 { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
207 { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
208 { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
209 { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
210 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
211 { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
212 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
213 { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
214 { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
215 { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
216 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
217 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
218 { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
219 { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
220 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
221 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
222 { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
223 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
224 { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
225 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
226 { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
227 { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
228 { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
229 { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
230 { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
231 { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
232 { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
233 { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
234 { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
235 { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
236 { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
237 { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
238 { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
239 { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
240 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
241 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
242 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
243 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
244 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
245 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
246 { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
247 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
248 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
249 { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
250 { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
251 { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
252 { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
253 { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
255 { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
256 { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
257 { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
258 { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
259 { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
260 { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
261 { "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
262 { "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
263 { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
264 { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
265 { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
266 { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
267 { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
268 { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
269 { "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
270 { "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
271 { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
272 { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
273 { "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
274 { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
275 { "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
276 { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
277 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
278 { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
279 { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
280 { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
281 { "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
282 { "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
283 { "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
284 { "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
285 { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
286 { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
287 { "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
288 { "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
289 { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
290 { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
291 { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
292 { "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
293 { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
294 { "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
295 { "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
296 { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
297 { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
298 { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
300 { "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
301 { "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
302 { "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
303 { "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
304 { "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
305 { "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
306 { "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
307 { "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
308 { "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
309 { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
310 { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
312 { "", 0, 0, 0, 0, 0, {0}},
316 * fix up misalignment problems where possible
318 asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
320 const struct exception_table_entry *fixup;
321 const struct mn10300_opcode *pop;
322 unsigned long *registers = (unsigned long *) regs;
323 unsigned long data, *store, *postinc, disp, inc, sp;
326 uint32_t opcode, noc, xo, xm;
327 uint8_t *pc, byte, datasz;
329 unsigned tmp, npop, dispsz, loop;
331 /* we don't fix up userspace misalignment faults */
335 sp = (unsigned long) regs + sizeof(*regs);
337 kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp);
339 if (regs->epsw & EPSW_IE)
340 asm volatile("or %0,epsw" : : "i"(EPSW_IE));
345 fixup = search_exception_tables(regs->pc);
347 /* first thing to do is to match the opcode */
348 pc = (u_int8_t *) regs->pc;
350 if (__get_user(byte, pc) != 0)
355 for (pop = mn10300_opcodes; pop->name[0]; pop++) {
356 npop = ilog2(pop->opcode | pop->opmask);
357 if (npop <= 0 || npop > 31)
359 npop = (npop + 8) & ~7;
363 if ((opcode & pop->opmask) == pop->opcode)
365 } else if (npop > noc) {
366 xo = pop->opcode >> (npop - noc);
367 xm = pop->opmask >> (npop - noc);
369 if ((opcode & xm) != xo)
372 /* we've got a partial match (an exact match on the
373 * first N bytes), so we need to get some more data */
375 if (__get_user(byte, pc) != 0)
377 opcode = opcode << 8 | byte;
381 /* there's already been a partial match as long as the
382 * complete match we're now considering, so this one
388 /* didn't manage to find a fixup */
389 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
394 if (die_if_no_fixup("misalignment error", regs, code))
398 info.si_signo = SIGBUS;
400 info.si_code = BUS_ADRALN;
401 info.si_addr = (void *) regs->pc;
402 force_sig_info(SIGBUS, &info, current);
405 /* error reading opcodes */
408 "MISALIGN: %p: fault whilst reading instruction data\n",
414 "MISALIGN: %lx: unsupported addressing mode %x\n",
420 "MISALIGN: %lx: unsupported register mode %x\n",
424 unsupported_instruction:
426 "MISALIGN: %lx: unsupported instruction %x (%s)\n",
427 regs->pc, opcode, pop->name);
433 regs->pc = fixup->fixup;
436 if (die_if_no_fixup("misalignment fixup", regs, code))
439 info.si_signo = SIGSEGV;
442 info.si_addr = (void *) regs->pc;
443 force_sig_info(SIGSEGV, &info, current);
446 /* we matched the opcode */
448 kdebug("%lx: %x==%x { %x, %x }",
449 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
451 tmp = format_tbl[pop->format].opsz;
452 BUG_ON(tmp > noc); /* match was less complete than it ought to have been */
460 /* grab the extra displacement (note it's LSB first) */
462 dispsz = format_tbl[pop->format].dispsz;
463 for (loop = 0; loop < dispsz; loop += 8) {
465 if (__get_user(byte, pc) != 0)
467 disp |= byte << loop;
468 kdebug("{%p} disp[%02x]=%02x", pc, loop, byte);
471 kdebug("disp=%lx", disp);
477 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
480 "MISALIGN: %lx: insn not move to/from memory %x\n",
485 /* determine the data transfer size of the move */
486 if (pop->name[3] == 0 || /* "mov" */
487 pop->name[4] == 'l') /* mov_lcc */
489 else if (pop->name[3] == 'h') /* movhu */
492 goto unsupported_instruction;
494 if (pop->params[0] & 0x80000000) {
495 /* move memory to register */
496 if (!misalignment_addr(registers, sp,
497 pop->params[0], opcode, disp,
498 &address, &postinc, &inc))
501 if (!misalignment_reg(registers, pop->params[1], opcode, disp,
505 kdebug("mov%u (%p),DARn", datasz, address);
506 if (copy_from_user(&data, (void *) address, datasz) != 0)
507 goto transfer_failed;
508 if (pop->params[0] & 0x1000000) {
509 kdebug("inc=%lx", inc);
514 kdebug("loaded %lx", data);
516 /* move register to memory */
517 if (!misalignment_reg(registers, pop->params[0], opcode, disp,
521 if (!misalignment_addr(registers, sp,
522 pop->params[1], opcode, disp,
523 &address, &postinc, &inc))
528 kdebug("mov%u %lx,(%p)", datasz, data, address);
529 if (copy_to_user((void *) address, &data, datasz) != 0)
530 goto transfer_failed;
531 if (pop->params[1] & 0x1000000)
535 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
536 regs->pc += tmp >> 3;
538 /* handle MOV_Lcc, which are currently the only FMT_D10 insns that
540 if (pop->format == FMT_D10)
541 misalignment_MOV_Lcc(regs, opcode);
547 * determine the address that was being accessed
549 static int misalignment_addr(unsigned long *registers, unsigned long sp,
550 unsigned params, unsigned opcode,
552 void **_address, unsigned long **_postinc,
555 unsigned long *postinc = NULL, address = 0, tmp;
557 if (!(params & 0x1000000)) {
563 params &= 0x00ffffff;
566 switch (params & 0xff) {
568 postinc = ®isters[Dreg_index[opcode & 0x03]];
572 postinc = ®isters[Dreg_index[opcode >> 2 & 0x03]];
576 postinc = ®isters[Dreg_index[opcode >> 4 & 0x03]];
580 postinc = ®isters[Areg_index[opcode & 0x03]];
584 postinc = ®isters[Areg_index[opcode >> 2 & 0x03]];
588 postinc = ®isters[Areg_index[opcode >> 4 & 0x03]];
592 postinc = ®isters[Rreg_index[opcode & 0x0f]];
596 postinc = ®isters[Rreg_index[opcode >> 2 & 0x0f]];
600 postinc = ®isters[Rreg_index[opcode >> 4 & 0x0f]];
604 postinc = ®isters[Rreg_index[opcode >> 8 & 0x0f]];
608 postinc = ®isters[Rreg_index[opcode >> 12 & 0x0f]];
612 postinc = ®isters[Rreg_index[disp & 0x0f]];
616 postinc = ®isters[Rreg_index[disp >> 4 & 0x0f]];
623 /* displacements are either to be added to the address
624 * before use, or, in the case of post-inc addressing,
625 * to be added into the base register after use */
628 disp = (long) (int8_t) (disp & 0xff);
629 goto displace_or_inc;
631 disp = (long) (int16_t) (disp & 0xffff);
632 goto displace_or_inc;
635 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp) : "cc");
637 goto displace_or_inc;
639 tmp = opcode >> 4 & 0x0f;
641 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp) : "cc");
643 goto displace_or_inc;
646 goto displace_or_inc;
649 goto displace_or_inc;
652 goto displace_or_inc;
656 case IMM32_HIGH8_MEM:
658 kdebug("%s %lx", _inc ? "incr" : "disp", disp);
668 } while ((params >>= 8));
670 *_address = (void *) address;
676 * determine the register that is acting as source/dest
678 static int misalignment_reg(unsigned long *registers, unsigned params,
679 unsigned opcode, unsigned long disp,
680 unsigned long **_register)
682 params &= 0x7fffffff;
684 if (params & 0xffffff00)
687 switch (params & 0xff) {
689 *_register = ®isters[Dreg_index[opcode & 0x03]];
692 *_register = ®isters[Dreg_index[opcode >> 2 & 0x03]];
695 *_register = ®isters[Dreg_index[opcode >> 4 & 0x03]];
698 *_register = ®isters[Areg_index[opcode & 0x03]];
701 *_register = ®isters[Areg_index[opcode >> 2 & 0x03]];
704 *_register = ®isters[Areg_index[opcode >> 4 & 0x03]];
707 *_register = ®isters[Rreg_index[opcode & 0x0f]];
710 *_register = ®isters[Rreg_index[opcode >> 2 & 0x0f]];
713 *_register = ®isters[Rreg_index[opcode >> 4 & 0x0f]];
716 *_register = ®isters[Rreg_index[opcode >> 8 & 0x0f]];
719 *_register = ®isters[Rreg_index[opcode >> 12 & 0x0f]];
722 *_register = ®isters[Rreg_index[disp & 0x0f]];
725 *_register = ®isters[Rreg_index[disp >> 4 & 0x0f]];
728 *_register = ®isters[REG_SP >> 2];
740 * handle the conditional loop part of the move-and-loop instructions
742 static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode)
744 unsigned long epsw = regs->epsw;
747 kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf);
749 /* calculate N^V and shift onto the same bit position as Z */
750 NxorV = ((epsw >> 3) ^ epsw >> 1) & 1;
752 switch (opcode & 0xf) {
753 case 0x0: /* MOV_LLT: N^V */
757 case 0x1: /* MOV_LGT: ~(Z or (N^V))*/
758 if (!((epsw & EPSW_FLAG_Z) | NxorV))
761 case 0x2: /* MOV_LGE: ~(N^V) */
765 case 0x3: /* MOV_LLE: Z or (N^V) */
766 if ((epsw & EPSW_FLAG_Z) | NxorV)
770 case 0x4: /* MOV_LCS: C */
771 if (epsw & EPSW_FLAG_C)
774 case 0x5: /* MOV_LHI: ~(C or Z) */
775 if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)))
778 case 0x6: /* MOV_LCC: ~C */
779 if (!(epsw & EPSW_FLAG_C))
782 case 0x7: /* MOV_LLS: C or Z */
783 if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))
787 case 0x8: /* MOV_LEQ: Z */
788 if (epsw & EPSW_FLAG_Z)
791 case 0x9: /* MOV_LNE: ~Z */
792 if (!(epsw & EPSW_FLAG_Z))
795 case 0xa: /* MOV_LRA: always */
803 /* wind the PC back to just after the SETLB insn */
804 kdebug("loop LAR=%lx", regs->lar);
805 regs->pc = regs->lar - 4;
809 * misalignment handler tests
811 #ifdef CONFIG_TEST_MISALIGNMENT_HANDLER
812 static u8 __initdata testbuf[512] __attribute__((aligned(16))) = {
819 #define ASSERTCMP(X, OP, Y) \
821 if (unlikely(!((X) OP (Y)))) { \
822 printk(KERN_ERR "\n"); \
823 printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \
825 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
826 (unsigned long)(X), (unsigned long)(Y)); \
831 static int __init test_misalignment(void)
833 register void *r asm("e0");
834 register u32 y asm("e1");
835 void *p = testbuf, *q;
838 printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p);
841 printk(KERN_NOTICE "___ MOV (Am),Dn ___\n");
843 asm volatile("mov (%0),%1" : "+a"(q), "=d"(x));
844 ASSERTCMP(q, ==, p + 256);
845 ASSERTCMP(x, ==, 0x44332211);
847 printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n");
849 asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x));
851 ASSERTCMP(x, ==, 0x44332211);
853 printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n");
856 asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp));
858 ASSERTCMP(x, ==, 0x44332211);
859 ASSERTCMP(tmp, ==, 256);
861 printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n");
863 asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y));
865 ASSERTCMP(y, ==, 0x44332211);
867 printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n");
869 asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y));
870 ASSERTCMP(r, ==, p + 256 + 4);
871 ASSERTCMP(y, ==, 0x44332211);
873 printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n");
875 asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y));
876 ASSERTCMP(r, ==, p + 256 + 8);
877 ASSERTCMP(y, ==, 0x44332211);
879 printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n");
889 "movbu %0,(10,sp) \n"
893 ASSERTCMP(x, ==, 0x44332211);
895 printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n");
899 "movbu %0,(259,sp) \n"
901 "movbu %0,(260,sp) \n"
903 "movbu %0,(261,sp) \n"
905 "movbu %0,(262,sp) \n"
908 : "+d"(tmp), "=d"(x));
909 ASSERTCMP(x, ==, 0x55332211);
911 printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n");
915 "movbu %0,(260,sp) \n"
917 "movbu %0,(261,sp) \n"
919 "movbu %0,(262,sp) \n"
921 "movbu %0,(263,sp) \n"
924 : "+d"(tmp), "=d"(x));
925 ASSERTCMP(x, ==, 0x55332211);
928 printk(KERN_NOTICE "___ MOV_LNE ___\n");
938 : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
941 ASSERTCMP(q, ==, p + 256 + 12);
942 ASSERTCMP(x, ==, 0x44332211);
944 printk(KERN_NOTICE "___ MOV in SETLB ___\n");
954 : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
958 ASSERTCMP(q, ==, p + 256 + 8);
959 ASSERTCMP(x, ==, 0x44332211);
961 printk(KERN_NOTICE "<==test_misalignment()\n");
965 arch_initcall(test_misalignment);
967 #endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */