2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/macro.h>
31 #include <generated/asm-offsets.h>
34 * parameters for the SDRAM controller
36 #define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
37 #define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
38 #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
39 #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
40 #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
41 #define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
43 #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
44 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
45 #define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
46 #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
48 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
49 #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
52 * parameters for the static memory controller
54 #define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
55 #define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
57 #define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
58 #define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
61 * parameters for the ahbc controller
63 #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
64 #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
66 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
69 * parameters for the pmu controoler
71 #define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
74 * numeric 7 segment display
77 write32 CONFIG_DEBUG_LED, \num
81 * Waiting for SDRAM to set up
84 li $r0, CONFIG_FTSDMC021_BASE
86 lwi $r1, [$r0+FTSDMC021_CR2]
90 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
109 * There are 2 bank connected to FTSMC020 on AG101
110 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
111 * we need to set onboard SDRAM before remap and relocation.
114 write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052
115 write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151
118 * config AHB Controller
121 write32 AHBC_BSR6_A, AHBC_BSR6_D
124 * config PMU controller
126 /* ftpmu010_dlldis_disable, must do it in lowleve_init */
128 setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
131 * config SDRAM controller
134 write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
136 write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
138 write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
141 write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
145 write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
149 write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
158 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
165 #endif /* __NDS32_N1213_43U1H__ */
171 write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
172 write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001140
174 /* clear empty BSR registers */
176 li $r4, CONFIG_FTSDMC021_BASE
178 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
179 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
181 #ifdef CONFIG_MEM_REMAP
183 * Copy ROM code to SDRAM base for memory remap layout.
184 * This is not the real relocation, the real relocation is the function
185 * relocate_code() is start.S which supports the systems is memory
189 * Doing memory remap is essential for preparing some non-OS or RTOS
192 * This is also a must on ADP-AG101 board.
193 * The reason is because the ROM/FLASH circuit on PCB board.
194 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
195 * ROM/FLASH is used to boot.
197 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
198 * and the FLASH is connected to BANK1.
199 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
200 * and the FLASH is connected to BANK0.
201 * It will occur problem when doing flash probing if the flash is at
202 * BANK0 (0x00000000) while memory remapping was skipped.
204 * Other board like ADP-AG101P may not enable this since there is only
205 * a FLASH connected to bank0.
208 li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
210 la $r1, relo_base /* get $pc or $lp */
212 sethi $r6, hi20(_end)
213 ori $r6, $r6, lo12(_end)
222 * MEM remap bit is operational
223 * - use it to map writeable memory at 0x00000000, in place of flash
224 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
225 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
228 write32 SDMC_B0_BSR_A, 0x00001000
229 write32 SDMC_B1_BSR_A, 0x00001040
230 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
232 #endif /* #ifdef CONFIG_MEM_REMAP */
239 li $r8, (CONFIG_DEBUG_LED)
242 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */