2 * Andesboot - Startup Code for Whitiger core
4 * Copyright (C) 2006 Andes Technology Corporation
5 * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
6 * Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
7 * Greentime Hu <greentime@andestech.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
15 #include <asm/macro.h>
18 * Jump vector table for EVIC mode
21 #define DIS_DCAC ~ENA_DCAC
22 #define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
23 #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
24 #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
25 #define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
26 #define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
27 #define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
30 #define EIT_INTR_PSW $ir1 ! interruption $PSW
31 #define EIT_PREV_IPSW $ir2 ! previous $IPSW
32 #define EIT_IVB $ir3 ! intr vector base address
33 #define EIT_EVA $ir4 ! MMU related Exception VA reg
34 #define EIT_PREV_EVA $ir5 ! previous $eva
35 #define EIT_ITYPE $ir6 ! interruption type
36 #define EIT_PREV_ITYPE $ir7 ! prev intr type
37 #define EIT_MACH_ERR $ir8 ! machine error log
38 #define EIT_INTR_PC $ir9 ! Interruption PC
39 #define EIT_PREV_IPC $ir10 ! previous $IPC
40 #define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
41 #define EIT_PREV_P0 $ir12 ! prev $P0
42 #define EIT_PREV_P1 $ir13 ! prev $p1
43 #define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
44 #define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
45 #define MR_CAC_CTL $mr8
58 j internal_interrupt ! H0I
59 j internal_interrupt ! H1I
60 j internal_interrupt ! H2I
61 j internal_interrupt ! H3I
62 j internal_interrupt ! H4I
63 j internal_interrupt ! H5I
64 j software_interrupt ! S0I
69 * Andesboot Startup Code (reset vector)
72 * 1.1 reset - start of u-boot
73 * 1.2 to superuser mode - as is when reset
74 * 1.4 Do lowlevel_init
75 * - (this will jump out to lowlevel_init.S in SoC)
77 * 1.3 Turn off watchdog timer
78 * - (this will jump out to watchdog.S in SoC)
79 * - (turnoff_watchdog)
80 * 2. Do critical init when reboot (not from mem)
81 * 3. Relocate andesboot to ram
83 * 5. Jump to second stage (board_init_r)
86 /* Note: TEXT_BASE is defined by the (board-dependent) linker script */
89 .word CONFIG_SYS_TEXT_BASE
92 * These are defined in the board-specific linker script.
93 * Subtracting _start from them lets the linker put their
94 * relative position in the executable instead of leaving
98 /* IRQ stack memory (calculated at run-time) */
99 .globl IRQ_STACK_START
103 /* IRQ stack memory (calculated at run-time) */
104 .globl FIQ_STACK_START
109 /* IRQ stack memory (calculated at run-time) + 8 bytes */
110 .globl IRQ_STACK_START_IN
115 * The bootstrap code of nds32 core
124 /* set IVIC, vector size: 4 bytes, base: 0x0 */
128 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
129 jal load_lowlevel_init
134 * Set the N1213 (Whitiger) core to superuser mode
135 * According to spec, it is already when reset
138 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
139 jal load_turnoff_watchdog
144 * Do CPU critical regs init only at reboot,
145 * not when booting from ram
147 #ifdef CONFIG_INIT_CRITICAL
148 bal cpu_init_crit ! Do CPU critical regs init
152 * Set stackpointer in internal RAM to call board_init_f
153 * $sp must be 8-byte alignment for ABI compliance.
156 li $sp, CONFIG_SYS_INIT_SP_ADDR
160 #ifdef __NDS32_N1213_43U1H__
161 /* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
162 la $r15, board_init_f ! store function address into $r15
165 j board_init_f ! jump to board_init_f() in lib/board.c
168 * void relocate_code (addr_sp, gd, addr_moni)
170 * This "function" does not return, instead it continues in RAM
171 * after relocating the monitor code.
176 move $r4, $r0 /* save addr_sp */
177 move $r5, $r1 /* save addr of gd */
178 move $r6, $r2 /* save addr of destination */
180 /* Set up the stack */
186 beq $r0, $r6, clear_bss /* skip relocation */
188 move $r1, $r6 /* r1 <- scratch for copy_loop */
190 sub $r3, $r3, $r0 /* r3 <- __bss_start_ofs */
191 add $r2, $r0, $r3 /* r2 <- source end address */
196 blt $r0, $r2, copy_loop
199 * fix relocations related issues
202 l.w $r0, _TEXT_BASE /* r0 <- Text base */
203 sub $r9, $r6, $r0 /* r9 <- relocation offset */
207 * Now we want to update GOT.
209 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
210 * generated by GNU ld. Skip these reserved entries from relocation.
212 la $r2, __got_start /* r2 <- rel __got_start in FLASH */
213 add $r2, $r2, $r9 /* r2 <- rel __got_start in RAM */
214 la $r3, __got_end /* r3 <- rel __got_end in FLASH */
215 add $r3, $r3, $r9 /* r3 <- rel __got_end in RAM */
216 addi $r2, $r2, #8 /* skipping first two entries */
218 lwi $r0, [$r2] /* r0 <- location in FLASH to fix up */
219 add $r0, $r0, $r9 /* r0 <- location fix up to RAM */
220 swi.p $r0, [$r2], #4 /* r0 <- store fix into .got in RAM */
221 blt $r2, $r3, fix_got_loop
224 la $r0, __bss_start /* r0 <- rel __bss_start in FLASH */
225 add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
226 la $r1, __bss_end /* r1 <- rel __bss_end in RAM */
227 add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
228 li $r2, 0x00000000 /* clear */
231 sw $r2, [$r0] /* clear loop... */
233 bne $r0, $r1, clbss_l
236 * We are done. Do not return, instead branch to second part of board
237 * initialization, now running from RAM.
241 move $lp, $r0 /* offset of board_init_r() */
242 add $lp, $lp, $r9 /* real address of board_init_r() */
243 /* setup parameters for board_init_r */
244 move $r0, $r5 /* gd_t */
245 move $r1, $r6 /* dest_addr */
248 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
249 move $r15, $lp /* store function address into $r15 */
254 jr $lp /* jump to board_init_r() */
257 * Initialize CPU critical registers
259 * 1. Setup control registers
261 * 1.2 Flush cache and TLB
262 * 1.3 Disable MMU and cache
263 * 2. Setup memory timing
268 move $r0, $lp /* push ra */
270 /* Disable Interrupts by clear GIE in $PSW reg */
273 /* Flush caches and TLB */
274 /* Invalidate caches */
280 andi $p0, $p0, 0x3 ! MMPS
281 li $p1, 0x2 ! TLB MMU
283 tlbop flushall ! Flush TLB
286 ! Disable MMU, Dcache
287 ! Whitiger is MMU disabled when reset
289 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
291 and $p0, $p0, $p1 ! Set DC_EN bit
292 mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
299 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
301 la $r6, lowlevel_init
308 #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
309 load_turnoff_watchdog:
310 la $r6, turnoff_watchdog
311 la $r7, turnoff_wtdog + 4
321 ! read $cr1(I CAC/MEM cfg. reg.) configuration
322 mfsr $t0, CR_ICAC_MEM
325 andi $p0, $t0, ICAC_MEM_KBF_ISZ
327 ! if $p0=0, then no I CAC existed
328 beqz $p0, end_flush_icache
330 ! get $p0 the index of I$ block
333 ! $t1= bit width of I cache line size(ISZ)
337 sll $t5, $t4, $t1 ! get $t5 cache line size
338 andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
339 addi $t2, $p1, 6 ! $t2= bit width of ISET
340 andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
342 addi $p1, $p1, 1 ! then $p1 is I way number
343 add $t3, $t2, $t1 ! SHIFT
344 sll $p1, $p1, $t3 ! GET the total cache size
347 cctl $p1, L1I_IX_INVAL
356 ! read $cr2(D CAC/MEM cfg. reg.) configuration
357 mfsr $t0, CR_DCAC_MEM
360 andi $p0, $t0, DCAC_MEM_KBF_DSZ
362 ! if $p0=0, then no D CAC existed
363 beqz $p0, end_flush_dcache
365 ! get $p0 the index of D$ block
368 ! $t1= bit width of D cache line size(DSZ)
372 sll $t5, $t4, $t1 ! get $t5 cache line size
373 andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
374 addi $t2, $p1, 6 ! $t2= bit width of DSET
375 andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
377 addi $p1, $p1, 1 ! then $p1 is D way number
378 add $t3, $t2, $t1 ! SHIFT
379 sll $p1, $p1, $t3 ! GET the total cache size
382 cctl $p1, L1D_IX_INVAL
397 ! FIXME: Other way to get PC?
398 ! FIXME: Update according to the newest spec!!
402 mfsr $r28, PSW ! $PSW
404 mfsr $r28, EIT_EVA ! $ir1 $EVA
406 mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
408 mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
410 mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
412 mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
414 mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
416 mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
418 mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
420 mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
422 mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
432 pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
433 addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
439 move $r0, $sp ! To get the kernel stack
440 li $r1, 1 ! Determine interruption type
446 move $r0, $sp ! To get the kernel stack
447 li $r1, 2 ! Determine interruption type
453 move $r0, $sp ! To get the kernel stack
454 li $r1, 3 ! Determine interruption type
460 move $r0, $sp ! To get the kernel stack
461 li $r1, 4 ! Determine interruption type
467 move $r0, $sp ! To get the kernel stack
468 li $r1, 5 ! Determine interruption type
474 move $r0, $sp ! To get the kernel stack
475 li $r1, 6 ! Determine interruption type
481 move $r0, $sp ! To get the kernel stack
482 li $r1, 7 ! Determine interruption type
488 move $r0, $sp ! To get the kernel stack
489 li $r1, 8 ! Determine interruption type
495 move $r0, $sp ! To get the kernel stack
496 li $r1, 9 ! Determine interruption type
502 move $r0, $sp ! To get the kernel stack
503 li $r1, 10 ! Determine interruption type
509 * void reset_cpu(ulong addr);
510 * $r0: input address to jump to
514 /* No need to disable MMU because we never enable it */
519 andi $p0, $p0, 0x3 ! MMPS
520 li $p1, 0x2 ! TLB MMU
522 tlbop flushall ! Flush TLB
524 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
526 and $p0, $p0, $p1 ! Clear the DC_EN bit
527 mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
528 br $r0 ! Jump to the input address